[linux-2.6-block.git] / arch / arm / boot / dts / sun8i-a33.dtsi

/*
 * Copyright 2014 Chen-Yu Tsai
 *
 * Chen-Yu Tsai <wens@csie.org>
 *
 * This file is dual-licensed: you can use it either under the terms
 * of the GPL or the X11 license, at your option. Note that this dual
 * licensing only applies to this file, and not this project as a
 * whole.
 *
 *  a) This file is free software; you can redistribute it and/or
 *     modify it under the terms of the GNU General Public License as
 *     published by the Free Software Foundation; either version 2 of the
 *     License, or (at your option) any later version.
 *
 *     This file is distributed in the hope that it will be useful,
 *     but WITHOUT ANY WARRANTY; without even the implied warranty of
 *     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 *     GNU General Public License for more details.
 *
 * Or, alternatively,
 *
 *  b) Permission is hereby granted, free of charge, to any person
 *     obtaining a copy of this software and associated documentation
 *     files (the "Software"), to deal in the Software without
 *     restriction, including without limitation the rights to use,
 *     copy, modify, merge, publish, distribute, sublicense, and/or
 *     sell copies of the Software, and to permit persons to whom the
 *     Software is furnished to do so, subject to the following
 *     conditions:
 *
 *     The above copyright notice and this permission notice shall be
 *     included in all copies or substantial portions of the Software.
 *
 *     THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
 *     EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
 *     OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
 *     NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
 *     HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
 *     WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
 *     FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
 *     OTHER DEALINGS IN THE SOFTWARE.
 */

#include "sun8i-a23-a33.dtsi"

/ {
	cpus {
		cpu@2 {
			compatible = "arm,cortex-a7";
			device_type = "cpu";
			reg = <2>;
		};

		cpu@3 {
			compatible = "arm,cortex-a7";
			device_type = "cpu";
			reg = <3>;
		};
	};

	de: display-engine {
		compatible = "allwinner,sun8i-a33-display-engine";
		allwinner,pipelines = <&fe0>;
		status = "disabled";
	};

	memory {
		reg = <0x40000000 0x80000000>;
	};

	soc@01c00000 {
		tcon0: lcd-controller@01c0c000 {
			compatible = "allwinner,sun8i-a33-tcon";
			reg = <0x01c0c000 0x1000>;
			interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&ccu CLK_BUS_LCD>,
				 <&ccu CLK_LCD_CH0>;
			clock-names = "ahb",
				      "tcon-ch0";
			clock-output-names = "tcon-pixel-clock";
			resets = <&ccu RST_BUS_LCD>;
			reset-names = "lcd";
			status = "disabled";

			ports {
				#address-cells = <1>;
				#size-cells = <0>;

				tcon0_in: port@0 {
					#address-cells = <1>;
					#size-cells = <0>;
					reg = <0>;

					tcon0_in_drc0: endpoint@0 {
						reg = <0>;
						remote-endpoint = <&drc0_out_tcon0>;
					};
				};

				tcon0_out: port@1 {
					#address-cells = <1>;
					#size-cells = <0>;
					reg = <1>;
				};
			};
		};

		crypto: crypto-engine@01c15000 {
			compatible = "allwinner,sun4i-a10-crypto";
			reg = <0x01c15000 0x1000>;
			interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&ccu CLK_BUS_SS>, <&ccu CLK_SS>;
			clock-names = "ahb", "mod";
			resets = <&ccu RST_BUS_SS>;
			reset-names = "ahb";
		};

		usb_otg: usb@01c19000 {
			compatible = "allwinner,sun8i-a33-musb";
			reg = <0x01c19000 0x0400>;
			clocks = <&ccu CLK_BUS_OTG>;
			resets = <&ccu RST_BUS_OTG>;
			interrupts = <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>;
			interrupt-names = "mc";
			phys = <&usbphy 0>;
			phy-names = "usb";
			extcon = <&usbphy 0>;
			status = "disabled";
		};

		usbphy: phy@01c19400 {
			compatible = "allwinner,sun8i-a33-usb-phy";
			reg = <0x01c19400 0x14>,
			      <0x01c1a800 0x4>;
			reg-names = "phy_ctrl",
				    "pmu1";
			clocks = <&ccu CLK_USB_PHY0>,
				 <&ccu CLK_USB_PHY1>;
			clock-names = "usb0_phy",
				      "usb1_phy";
			resets = <&ccu RST_USB_PHY0>,
				 <&ccu RST_USB_PHY1>;
			reset-names = "usb0_reset",
				      "usb1_reset";
			status = "disabled";
			#phy-cells = <1>;
		};

		fe0: display-frontend@01e00000 {
			compatible = "allwinner,sun8i-a33-display-frontend";
			reg = <0x01e00000 0x20000>;
			interrupts = <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&ccu CLK_BUS_DE_FE>, <&ccu CLK_DE_FE>,
				 <&ccu CLK_DRAM_DE_FE>;
			clock-names = "ahb", "mod",
				      "ram";
			resets = <&ccu RST_BUS_DE_FE>;
			status = "disabled";

			ports {
				#address-cells = <1>;
				#size-cells = <0>;

				fe0_out: port@1 {
					#address-cells = <1>;
					#size-cells = <0>;
					reg = <1>;

					fe0_out_be0: endpoint@0 {
						reg = <0>;
						remote-endpoint = <&be0_in_fe0>;
					};
				};
			};
		};

		be0: display-backend@01e60000 {
			compatible = "allwinner,sun8i-a33-display-backend";
			reg = <0x01e60000 0x10000>, <0x01e80000 0x1000>;
			reg-names = "be", "sat";
			interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&ccu CLK_BUS_DE_BE>, <&ccu CLK_DE_BE>,
				 <&ccu CLK_DRAM_DE_BE>, <&ccu CLK_BUS_SAT>;
			clock-names = "ahb", "mod",
				      "ram", "sat";
			resets = <&ccu RST_BUS_DE_BE>, <&ccu RST_BUS_SAT>;
			reset-names = "be", "sat";
			assigned-clocks = <&ccu CLK_DE_BE>;
			assigned-clock-rates = <300000000>;

			ports {
				#address-cells = <1>;
				#size-cells = <0>;

				be0_in: port@0 {
					#address-cells = <1>;
					#size-cells = <0>;
					reg = <0>;

					be0_in_fe0: endpoint@0 {
						reg = <0>;
						remote-endpoint = <&fe0_out_be0>;
					};
				};

				be0_out: port@1 {
					#address-cells = <1>;
					#size-cells = <0>;
					reg = <1>;

					be0_out_drc0: endpoint@0 {
						reg = <0>;
						remote-endpoint = <&drc0_in_be0>;
					};
				};
			};
		};

		drc0: drc@01e70000 {
			compatible = "allwinner,sun8i-a33-drc";
			reg = <0x01e70000 0x10000>;
			interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&ccu CLK_BUS_DRC>, <&ccu CLK_DRC>,
				 <&ccu CLK_DRAM_DRC>;
			clock-names = "ahb", "mod", "ram";
			resets = <&ccu RST_BUS_DRC>;

			assigned-clocks = <&ccu CLK_DRC>;
			assigned-clock-rates = <300000000>;

			ports {
				#address-cells = <1>;
				#size-cells = <0>;

				drc0_in: port@0 {
					#address-cells = <1>;
					#size-cells = <0>;
					reg = <0>;

					drc0_in_be0: endpoint@0 {
						reg = <0>;
						remote-endpoint = <&be0_out_drc0>;
					};
				};

				drc0_out: port@1 {
					#address-cells = <1>;
					#size-cells = <0>;
					reg = <1>;

					drc0_out_tcon0: endpoint@0 {
						reg = <0>;
						remote-endpoint = <&tcon0_in_drc0>;
					};
				};
			};
		};
	};
};

&ccu {
	compatible = "allwinner,sun8i-a33-ccu";
};

&pio {
	compatible = "allwinner,sun8i-a33-pinctrl";
	interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>,
		     <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;

	uart0_pins_b: uart0@1 {
		allwinner,pins = "PB0", "PB1";
		allwinner,function = "uart0";
		allwinner,drive = <SUN4I_PINCTRL_10_MA>;
		allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
	};

};
Commit	Line	Data
35af8e4b VP	1	/*
	2	* Copyright 2014 Chen-Yu Tsai
	3	*
	4	* Chen-Yu Tsai <wens@csie.org>
	5	*
	6	* This file is dual-licensed: you can use it either under the terms
	7	* of the GPL or the X11 license, at your option. Note that this dual
	8	* licensing only applies to this file, and not this project as a
	9	* whole.
	10	*
	11	* a) This file is free software; you can redistribute it and/or
	12	* modify it under the terms of the GNU General Public License as
	13	* published by the Free Software Foundation; either version 2 of the
	14	* License, or (at your option) any later version.
	15	*
	16	* This file is distributed in the hope that it will be useful,
	17	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	18	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	19	* GNU General Public License for more details.
	20	*
	21	* Or, alternatively,
	22	*
	23	* b) Permission is hereby granted, free of charge, to any person
	24	* obtaining a copy of this software and associated documentation
	25	* files (the "Software"), to deal in the Software without
	26	* restriction, including without limitation the rights to use,
	27	* copy, modify, merge, publish, distribute, sublicense, and/or
	28	* sell copies of the Software, and to permit persons to whom the
	29	* Software is furnished to do so, subject to the following
	30	* conditions:
	31	*
	32	* The above copyright notice and this permission notice shall be
	33	* included in all copies or substantial portions of the Software.
	34	*
	35	* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
	36	* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
	37	* OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
	38	* NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
	39	* HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
	40	* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
	41	* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
	42	* OTHER DEALINGS IN THE SOFTWARE.
	43	*/
	44
	45	#include "sun8i-a23-a33.dtsi"
	46
	47	/ {
	48	cpus {
	49	cpu@2 {
	50	compatible = "arm,cortex-a7";
	51	device_type = "cpu";
	52	reg = <2>;
	53	};
	54
	55	cpu@3 {
	56	compatible = "arm,cortex-a7";
	57	device_type = "cpu";
	58	reg = <3>;
	59	};
	60	};
	61
b12684fe MR	62	de: display-engine {
	63	compatible = "allwinner,sun8i-a33-display-engine";
	64	allwinner,pipelines = <&fe0>;
	65	status = "disabled";
	66	};
	67
35af8e4b VP	68	memory {
	69	reg = <0x40000000 0x80000000>;
	70	};
	71
4f8449b1	72	soc@01c00000 {
b12684fe MR	73	tcon0: lcd-controller@01c0c000 {
	74	compatible = "allwinner,sun8i-a33-tcon";
	75	reg = <0x01c0c000 0x1000>;
	76	interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
	77	clocks = <&ccu CLK_BUS_LCD>,
	78	<&ccu CLK_LCD_CH0>;
	79	clock-names = "ahb",
	80	"tcon-ch0";
	81	clock-output-names = "tcon-pixel-clock";
	82	resets = <&ccu RST_BUS_LCD>;
	83	reset-names = "lcd";
	84	status = "disabled";
	85
	86	ports {
	87	#address-cells = <1>;
	88	#size-cells = <0>;
	89
	90	tcon0_in: port@0 {
	91	#address-cells = <1>;
	92	#size-cells = <0>;
	93	reg = <0>;
	94
	95	tcon0_in_drc0: endpoint@0 {
	96	reg = <0>;
	97	remote-endpoint = <&drc0_out_tcon0>;
	98	};
	99	};
	100
	101	tcon0_out: port@1 {
	102	#address-cells = <1>;
	103	#size-cells = <0>;
	104	reg = <1>;
	105	};
	106	};
	107	};
	108
f7ad082c CYT	109	crypto: crypto-engine@01c15000 {
	110	compatible = "allwinner,sun4i-a10-crypto";
	111	reg = <0x01c15000 0x1000>;
	112	interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>;
2c89ce4f	113	clocks = <&ccu CLK_BUS_SS>, <&ccu CLK_SS>;
f7ad082c	114	clock-names = "ahb", "mod";
2c89ce4f	115	resets = <&ccu RST_BUS_SS>;
f7ad082c CYT	116	reset-names = "ahb";
	117	};
	118
4f8449b1 HG	119	usb_otg: usb@01c19000 {
	120	compatible = "allwinner,sun8i-a33-musb";
	121	reg = <0x01c19000 0x0400>;
2c89ce4f MR	122	clocks = <&ccu CLK_BUS_OTG>;
2c89ce4f MR	123	resets = <&ccu RST_BUS_OTG>;
4f8449b1 HG	124	interrupts = <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>;
	125	interrupt-names = "mc";
	126	phys = <&usbphy 0>;
	127	phy-names = "usb";
	128	extcon = <&usbphy 0>;
	129	status = "disabled";
	130	};
	131
	132	usbphy: phy@01c19400 {
	133	compatible = "allwinner,sun8i-a33-usb-phy";
	134	reg = <0x01c19400 0x14>,
	135	<0x01c1a800 0x4>;
	136	reg-names = "phy_ctrl",
	137	"pmu1";
2c89ce4f MR	138	clocks = <&ccu CLK_USB_PHY0>,
2c89ce4f MR	139	<&ccu CLK_USB_PHY1>;
4f8449b1 HG	140	clock-names = "usb0_phy",
4f8449b1 HG	141	"usb1_phy";
2c89ce4f MR	142	resets = <&ccu RST_USB_PHY0>,
2c89ce4f MR	143	<&ccu RST_USB_PHY1>;
4f8449b1 HG	144	reset-names = "usb0_reset",
	145	"usb1_reset";
	146	status = "disabled";
	147	#phy-cells = <1>;
	148	};
b12684fe MR	149
	150	fe0: display-frontend@01e00000 {
	151	compatible = "allwinner,sun8i-a33-display-frontend";
	152	reg = <0x01e00000 0x20000>;
	153	interrupts = <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>;
	154	clocks = <&ccu CLK_BUS_DE_FE>, <&ccu CLK_DE_FE>,
	155	<&ccu CLK_DRAM_DE_FE>;
	156	clock-names = "ahb", "mod",
	157	"ram";
	158	resets = <&ccu RST_BUS_DE_FE>;
	159	status = "disabled";
	160
	161	ports {
	162	#address-cells = <1>;
	163	#size-cells = <0>;
	164
	165	fe0_out: port@1 {
	166	#address-cells = <1>;
	167	#size-cells = <0>;
	168	reg = <1>;
	169
	170	fe0_out_be0: endpoint@0 {
	171	reg = <0>;
	172	remote-endpoint = <&be0_in_fe0>;
	173	};
	174	};
	175	};
	176	};
	177
	178	be0: display-backend@01e60000 {
	179	compatible = "allwinner,sun8i-a33-display-backend";
	180	reg = <0x01e60000 0x10000>, <0x01e80000 0x1000>;
	181	reg-names = "be", "sat";
	182	interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>;
	183	clocks = <&ccu CLK_BUS_DE_BE>, <&ccu CLK_DE_BE>,
	184	<&ccu CLK_DRAM_DE_BE>, <&ccu CLK_BUS_SAT>;
	185	clock-names = "ahb", "mod",
	186	"ram", "sat";
	187	resets = <&ccu RST_BUS_DE_BE>, <&ccu RST_BUS_SAT>;
	188	reset-names = "be", "sat";
	189	assigned-clocks = <&ccu CLK_DE_BE>;
	190	assigned-clock-rates = <300000000>;
	191
	192	ports {
	193	#address-cells = <1>;
	194	#size-cells = <0>;
	195
	196	be0_in: port@0 {
	197	#address-cells = <1>;
	198	#size-cells = <0>;
	199	reg = <0>;
	200
	201	be0_in_fe0: endpoint@0 {
	202	reg = <0>;
	203	remote-endpoint = <&fe0_out_be0>;
	204	};
	205	};
	206
	207	be0_out: port@1 {
	208	#address-cells = <1>;
	209	#size-cells = <0>;
	210	reg = <1>;
	211
	212	be0_out_drc0: endpoint@0 {
213	reg = <0>;
214	remote-endpoint = <&drc0_in_be0>;
215	};
216	};
217	};
218	};
219
220	drc0: drc@01e70000 {
221	compatible = "allwinner,sun8i-a33-drc";
222	reg = <0x01e70000 0x10000>;
223	interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>;
224	clocks = <&ccu CLK_BUS_DRC>, <&ccu CLK_DRC>,
225	<&ccu CLK_DRAM_DRC>;
226	clock-names = "ahb", "mod", "ram";
227	resets = <&ccu RST_BUS_DRC>;
228
229	assigned-clocks = <&ccu CLK_DRC>;
230	assigned-clock-rates = <300000000>;
231
232	ports {
233	#address-cells = <1>;
234	#size-cells = <0>;
235
236	drc0_in: port@0 {
237	#address-cells = <1>;
238	#size-cells = <0>;
239	reg = <0>;
240
241	drc0_in_be0: endpoint@0 {
242	reg = <0>;
243	remote-endpoint = <&be0_out_drc0>;
244	};
245	};
246
247	drc0_out: port@1 {
248	#address-cells = <1>;
249	#size-cells = <0>;
250	reg = <1>;
251
252	drc0_out_tcon0: endpoint@0 {
253	reg = <0>;
254	remote-endpoint = <&tcon0_in_drc0>;
255	};
256	};
257	};
258	};
4f8449b1	259	};
35af8e4b VP	260	};
35af8e4b VP	261
2c89ce4f MR	262	&ccu {
	263	compatible = "allwinner,sun8i-a33-ccu";
	264	};
	265
35af8e4b VP	266	&pio {
	267	compatible = "allwinner,sun8i-a33-pinctrl";
	268	interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>,
	269	<GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
63c6509b CYT	270
	271	uart0_pins_b: uart0@1 {
	272	allwinner,pins = "PB0", "PB1";
	273	allwinner,function = "uart0";
	274	allwinner,drive = <SUN4I_PINCTRL_10_MA>;
	275	allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
	276	};
	277
35af8e4b	278	};