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35af8e4b VP |
1 | /* |
2 | * Copyright 2014 Chen-Yu Tsai | |
3 | * | |
4 | * Chen-Yu Tsai <wens@csie.org> | |
5 | * | |
6 | * This file is dual-licensed: you can use it either under the terms | |
7 | * of the GPL or the X11 license, at your option. Note that this dual | |
8 | * licensing only applies to this file, and not this project as a | |
9 | * whole. | |
10 | * | |
11 | * a) This file is free software; you can redistribute it and/or | |
12 | * modify it under the terms of the GNU General Public License as | |
13 | * published by the Free Software Foundation; either version 2 of the | |
14 | * License, or (at your option) any later version. | |
15 | * | |
16 | * This file is distributed in the hope that it will be useful, | |
17 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
18 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
19 | * GNU General Public License for more details. | |
20 | * | |
21 | * Or, alternatively, | |
22 | * | |
23 | * b) Permission is hereby granted, free of charge, to any person | |
24 | * obtaining a copy of this software and associated documentation | |
25 | * files (the "Software"), to deal in the Software without | |
26 | * restriction, including without limitation the rights to use, | |
27 | * copy, modify, merge, publish, distribute, sublicense, and/or | |
28 | * sell copies of the Software, and to permit persons to whom the | |
29 | * Software is furnished to do so, subject to the following | |
30 | * conditions: | |
31 | * | |
32 | * The above copyright notice and this permission notice shall be | |
33 | * included in all copies or substantial portions of the Software. | |
34 | * | |
35 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, | |
36 | * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES | |
37 | * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND | |
38 | * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT | |
39 | * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, | |
40 | * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING | |
41 | * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR | |
42 | * OTHER DEALINGS IN THE SOFTWARE. | |
43 | */ | |
44 | ||
45 | #include "sun8i-a23-a33.dtsi" | |
a5ce7a3d | 46 | #include <dt-bindings/thermal/thermal.h> |
35af8e4b VP |
47 | |
48 | / { | |
03749eb8 IZ |
49 | cpu0_opp_table: opp_table0 { |
50 | compatible = "operating-points-v2"; | |
51 | opp-shared; | |
52 | ||
84f1738a | 53 | opp-120000000 { |
e6bd3762 QS |
54 | opp-hz = /bits/ 64 <120000000>; |
55 | opp-microvolt = <1040000>; | |
56 | clock-latency-ns = <244144>; /* 8 32k periods */ | |
57 | }; | |
58 | ||
84f1738a | 59 | opp-240000000 { |
e6bd3762 QS |
60 | opp-hz = /bits/ 64 <240000000>; |
61 | opp-microvolt = <1040000>; | |
62 | clock-latency-ns = <244144>; /* 8 32k periods */ | |
63 | }; | |
64 | ||
84f1738a | 65 | opp-312000000 { |
e6bd3762 QS |
66 | opp-hz = /bits/ 64 <312000000>; |
67 | opp-microvolt = <1040000>; | |
68 | clock-latency-ns = <244144>; /* 8 32k periods */ | |
69 | }; | |
70 | ||
84f1738a | 71 | opp-408000000 { |
e6bd3762 QS |
72 | opp-hz = /bits/ 64 <408000000>; |
73 | opp-microvolt = <1040000>; | |
74 | clock-latency-ns = <244144>; /* 8 32k periods */ | |
75 | }; | |
76 | ||
84f1738a | 77 | opp-480000000 { |
e6bd3762 QS |
78 | opp-hz = /bits/ 64 <480000000>; |
79 | opp-microvolt = <1040000>; | |
80 | clock-latency-ns = <244144>; /* 8 32k periods */ | |
81 | }; | |
82 | ||
84f1738a | 83 | opp-504000000 { |
e6bd3762 QS |
84 | opp-hz = /bits/ 64 <504000000>; |
85 | opp-microvolt = <1040000>; | |
86 | clock-latency-ns = <244144>; /* 8 32k periods */ | |
87 | }; | |
88 | ||
84f1738a | 89 | opp-600000000 { |
e6bd3762 QS |
90 | opp-hz = /bits/ 64 <600000000>; |
91 | opp-microvolt = <1040000>; | |
92 | clock-latency-ns = <244144>; /* 8 32k periods */ | |
93 | }; | |
94 | ||
84f1738a | 95 | opp-648000000 { |
03749eb8 IZ |
96 | opp-hz = /bits/ 64 <648000000>; |
97 | opp-microvolt = <1040000>; | |
98 | clock-latency-ns = <244144>; /* 8 32k periods */ | |
99 | }; | |
100 | ||
84f1738a | 101 | opp-720000000 { |
e6bd3762 QS |
102 | opp-hz = /bits/ 64 <720000000>; |
103 | opp-microvolt = <1100000>; | |
104 | clock-latency-ns = <244144>; /* 8 32k periods */ | |
105 | }; | |
106 | ||
84f1738a | 107 | opp-816000000 { |
03749eb8 IZ |
108 | opp-hz = /bits/ 64 <816000000>; |
109 | opp-microvolt = <1100000>; | |
110 | clock-latency-ns = <244144>; /* 8 32k periods */ | |
111 | }; | |
112 | ||
84f1738a | 113 | opp-912000000 { |
e6bd3762 QS |
114 | opp-hz = /bits/ 64 <912000000>; |
115 | opp-microvolt = <1200000>; | |
116 | clock-latency-ns = <244144>; /* 8 32k periods */ | |
117 | }; | |
118 | ||
84f1738a | 119 | opp-1008000000 { |
03749eb8 IZ |
120 | opp-hz = /bits/ 64 <1008000000>; |
121 | opp-microvolt = <1200000>; | |
122 | clock-latency-ns = <244144>; /* 8 32k periods */ | |
123 | }; | |
03749eb8 IZ |
124 | }; |
125 | ||
35af8e4b | 126 | cpus { |
03749eb8 IZ |
127 | cpu@0 { |
128 | clocks = <&ccu CLK_CPUX>; | |
129 | clock-names = "cpu"; | |
130 | operating-points-v2 = <&cpu0_opp_table>; | |
a5ce7a3d | 131 | #cooling-cells = <2>; |
03749eb8 IZ |
132 | }; |
133 | ||
ea33c2c2 QS |
134 | cpu@1 { |
135 | operating-points-v2 = <&cpu0_opp_table>; | |
136 | }; | |
137 | ||
35af8e4b VP |
138 | cpu@2 { |
139 | compatible = "arm,cortex-a7"; | |
140 | device_type = "cpu"; | |
141 | reg = <2>; | |
ea33c2c2 | 142 | operating-points-v2 = <&cpu0_opp_table>; |
35af8e4b VP |
143 | }; |
144 | ||
145 | cpu@3 { | |
146 | compatible = "arm,cortex-a7"; | |
147 | device_type = "cpu"; | |
148 | reg = <3>; | |
ea33c2c2 | 149 | operating-points-v2 = <&cpu0_opp_table>; |
35af8e4b VP |
150 | }; |
151 | }; | |
152 | ||
b12684fe MR |
153 | de: display-engine { |
154 | compatible = "allwinner,sun8i-a33-display-engine"; | |
155 | allwinner,pipelines = <&fe0>; | |
156 | status = "disabled"; | |
157 | }; | |
158 | ||
a424f635 QS |
159 | iio-hwmon { |
160 | compatible = "iio-hwmon"; | |
161 | io-channels = <&ths>; | |
162 | }; | |
163 | ||
66c37322 MR |
164 | mali_opp_table: gpu-opp-table { |
165 | compatible = "operating-points-v2"; | |
166 | ||
84f1738a | 167 | opp-144000000 { |
66c37322 MR |
168 | opp-hz = /bits/ 64 <144000000>; |
169 | }; | |
170 | ||
84f1738a | 171 | opp-240000000 { |
66c37322 MR |
172 | opp-hz = /bits/ 64 <240000000>; |
173 | }; | |
174 | ||
84f1738a | 175 | opp-384000000 { |
66c37322 MR |
176 | opp-hz = /bits/ 64 <384000000>; |
177 | }; | |
178 | }; | |
179 | ||
35af8e4b VP |
180 | memory { |
181 | reg = <0x40000000 0x80000000>; | |
182 | }; | |
183 | ||
870f1bd1 MJ |
184 | sound: sound { |
185 | compatible = "simple-audio-card"; | |
186 | simple-audio-card,name = "sun8i-a33-audio"; | |
187 | simple-audio-card,format = "i2s"; | |
188 | simple-audio-card,frame-master = <&link_codec>; | |
189 | simple-audio-card,bitclock-master = <&link_codec>; | |
190 | simple-audio-card,mclk-fs = <512>; | |
191 | simple-audio-card,aux-devs = <&codec_analog>; | |
192 | simple-audio-card,routing = | |
eb3abaea MJ |
193 | "Left DAC", "AIF1 Slot 0 Left", |
194 | "Right DAC", "AIF1 Slot 0 Right"; | |
870f1bd1 MJ |
195 | status = "disabled"; |
196 | ||
197 | simple-audio-card,cpu { | |
198 | sound-dai = <&dai>; | |
199 | }; | |
200 | ||
201 | link_codec: simple-audio-card,codec { | |
202 | sound-dai = <&codec>; | |
203 | }; | |
204 | }; | |
205 | ||
4f8449b1 | 206 | soc@01c00000 { |
b12684fe MR |
207 | tcon0: lcd-controller@01c0c000 { |
208 | compatible = "allwinner,sun8i-a33-tcon"; | |
209 | reg = <0x01c0c000 0x1000>; | |
210 | interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>; | |
211 | clocks = <&ccu CLK_BUS_LCD>, | |
212 | <&ccu CLK_LCD_CH0>; | |
213 | clock-names = "ahb", | |
214 | "tcon-ch0"; | |
215 | clock-output-names = "tcon-pixel-clock"; | |
216 | resets = <&ccu RST_BUS_LCD>; | |
217 | reset-names = "lcd"; | |
218 | status = "disabled"; | |
219 | ||
220 | ports { | |
221 | #address-cells = <1>; | |
222 | #size-cells = <0>; | |
223 | ||
224 | tcon0_in: port@0 { | |
225 | #address-cells = <1>; | |
226 | #size-cells = <0>; | |
227 | reg = <0>; | |
228 | ||
229 | tcon0_in_drc0: endpoint@0 { | |
230 | reg = <0>; | |
231 | remote-endpoint = <&drc0_out_tcon0>; | |
232 | }; | |
233 | }; | |
234 | ||
235 | tcon0_out: port@1 { | |
236 | #address-cells = <1>; | |
237 | #size-cells = <0>; | |
238 | reg = <1>; | |
239 | }; | |
240 | }; | |
241 | }; | |
242 | ||
f7ad082c CYT |
243 | crypto: crypto-engine@01c15000 { |
244 | compatible = "allwinner,sun4i-a10-crypto"; | |
245 | reg = <0x01c15000 0x1000>; | |
246 | interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>; | |
2c89ce4f | 247 | clocks = <&ccu CLK_BUS_SS>, <&ccu CLK_SS>; |
f7ad082c | 248 | clock-names = "ahb", "mod"; |
2c89ce4f | 249 | resets = <&ccu RST_BUS_SS>; |
f7ad082c CYT |
250 | reset-names = "ahb"; |
251 | }; | |
252 | ||
870f1bd1 MJ |
253 | dai: dai@01c22c00 { |
254 | #sound-dai-cells = <0>; | |
255 | compatible = "allwinner,sun6i-a31-i2s"; | |
256 | reg = <0x01c22c00 0x200>; | |
257 | interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>; | |
258 | clocks = <&ccu CLK_BUS_CODEC>, <&ccu CLK_AC_DIG>; | |
259 | clock-names = "apb", "mod"; | |
260 | resets = <&ccu RST_BUS_CODEC>; | |
261 | dmas = <&dma 15>, <&dma 15>; | |
262 | dma-names = "rx", "tx"; | |
263 | status = "disabled"; | |
264 | }; | |
265 | ||
266 | codec: codec@01c22e00 { | |
267 | #sound-dai-cells = <0>; | |
268 | compatible = "allwinner,sun8i-a33-codec"; | |
269 | reg = <0x01c22e00 0x400>; | |
270 | interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>; | |
271 | clocks = <&ccu CLK_BUS_CODEC>, <&ccu CLK_AC_DIG>; | |
272 | clock-names = "bus", "mod"; | |
273 | status = "disabled"; | |
274 | }; | |
275 | ||
a424f635 QS |
276 | ths: ths@01c25000 { |
277 | compatible = "allwinner,sun8i-a33-ths"; | |
278 | reg = <0x01c25000 0x100>; | |
279 | #thermal-sensor-cells = <0>; | |
280 | #io-channel-cells = <0>; | |
281 | }; | |
282 | ||
b12684fe MR |
283 | fe0: display-frontend@01e00000 { |
284 | compatible = "allwinner,sun8i-a33-display-frontend"; | |
285 | reg = <0x01e00000 0x20000>; | |
286 | interrupts = <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>; | |
287 | clocks = <&ccu CLK_BUS_DE_FE>, <&ccu CLK_DE_FE>, | |
288 | <&ccu CLK_DRAM_DE_FE>; | |
289 | clock-names = "ahb", "mod", | |
290 | "ram"; | |
291 | resets = <&ccu RST_BUS_DE_FE>; | |
292 | status = "disabled"; | |
293 | ||
294 | ports { | |
295 | #address-cells = <1>; | |
296 | #size-cells = <0>; | |
297 | ||
298 | fe0_out: port@1 { | |
299 | #address-cells = <1>; | |
300 | #size-cells = <0>; | |
301 | reg = <1>; | |
302 | ||
303 | fe0_out_be0: endpoint@0 { | |
304 | reg = <0>; | |
305 | remote-endpoint = <&be0_in_fe0>; | |
306 | }; | |
307 | }; | |
308 | }; | |
309 | }; | |
310 | ||
311 | be0: display-backend@01e60000 { | |
312 | compatible = "allwinner,sun8i-a33-display-backend"; | |
313 | reg = <0x01e60000 0x10000>, <0x01e80000 0x1000>; | |
314 | reg-names = "be", "sat"; | |
315 | interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>; | |
316 | clocks = <&ccu CLK_BUS_DE_BE>, <&ccu CLK_DE_BE>, | |
317 | <&ccu CLK_DRAM_DE_BE>, <&ccu CLK_BUS_SAT>; | |
318 | clock-names = "ahb", "mod", | |
319 | "ram", "sat"; | |
320 | resets = <&ccu RST_BUS_DE_BE>, <&ccu RST_BUS_SAT>; | |
321 | reset-names = "be", "sat"; | |
322 | assigned-clocks = <&ccu CLK_DE_BE>; | |
323 | assigned-clock-rates = <300000000>; | |
324 | ||
325 | ports { | |
326 | #address-cells = <1>; | |
327 | #size-cells = <0>; | |
328 | ||
329 | be0_in: port@0 { | |
330 | #address-cells = <1>; | |
331 | #size-cells = <0>; | |
332 | reg = <0>; | |
333 | ||
334 | be0_in_fe0: endpoint@0 { | |
335 | reg = <0>; | |
336 | remote-endpoint = <&fe0_out_be0>; | |
337 | }; | |
338 | }; | |
339 | ||
340 | be0_out: port@1 { | |
341 | #address-cells = <1>; | |
342 | #size-cells = <0>; | |
343 | reg = <1>; | |
344 | ||
345 | be0_out_drc0: endpoint@0 { | |
346 | reg = <0>; | |
347 | remote-endpoint = <&drc0_in_be0>; | |
348 | }; | |
349 | }; | |
350 | }; | |
351 | }; | |
352 | ||
353 | drc0: drc@01e70000 { | |
354 | compatible = "allwinner,sun8i-a33-drc"; | |
355 | reg = <0x01e70000 0x10000>; | |
356 | interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>; | |
357 | clocks = <&ccu CLK_BUS_DRC>, <&ccu CLK_DRC>, | |
358 | <&ccu CLK_DRAM_DRC>; | |
359 | clock-names = "ahb", "mod", "ram"; | |
360 | resets = <&ccu RST_BUS_DRC>; | |
361 | ||
362 | assigned-clocks = <&ccu CLK_DRC>; | |
363 | assigned-clock-rates = <300000000>; | |
364 | ||
365 | ports { | |
366 | #address-cells = <1>; | |
367 | #size-cells = <0>; | |
368 | ||
369 | drc0_in: port@0 { | |
370 | #address-cells = <1>; | |
371 | #size-cells = <0>; | |
372 | reg = <0>; | |
373 | ||
374 | drc0_in_be0: endpoint@0 { | |
375 | reg = <0>; | |
376 | remote-endpoint = <&be0_out_drc0>; | |
377 | }; | |
378 | }; | |
379 | ||
380 | drc0_out: port@1 { | |
381 | #address-cells = <1>; | |
382 | #size-cells = <0>; | |
383 | reg = <1>; | |
384 | ||
385 | drc0_out_tcon0: endpoint@0 { | |
386 | reg = <0>; | |
387 | remote-endpoint = <&tcon0_in_drc0>; | |
388 | }; | |
389 | }; | |
390 | }; | |
391 | }; | |
4f8449b1 | 392 | }; |
a5ce7a3d QS |
393 | |
394 | thermal-zones { | |
395 | cpu_thermal { | |
396 | /* milliseconds */ | |
397 | polling-delay-passive = <250>; | |
398 | polling-delay = <1000>; | |
399 | thermal-sensors = <&ths>; | |
400 | ||
401 | cooling-maps { | |
402 | map0 { | |
403 | trip = <&cpu_alert0>; | |
404 | cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; | |
405 | }; | |
406 | map1 { | |
407 | trip = <&cpu_alert1>; | |
408 | cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; | |
409 | }; | |
e846011e MR |
410 | |
411 | map2 { | |
412 | trip = <&gpu_alert0>; | |
413 | cooling-device = <&mali 1 THERMAL_NO_LIMIT>; | |
414 | }; | |
415 | ||
416 | map3 { | |
417 | trip = <&gpu_alert1>; | |
418 | cooling-device = <&mali 2 THERMAL_NO_LIMIT>; | |
419 | }; | |
a5ce7a3d QS |
420 | }; |
421 | ||
422 | trips { | |
423 | cpu_alert0: cpu_alert0 { | |
424 | /* milliCelsius */ | |
425 | temperature = <75000>; | |
426 | hysteresis = <2000>; | |
427 | type = "passive"; | |
428 | }; | |
429 | ||
e846011e MR |
430 | gpu_alert0: gpu_alert0 { |
431 | /* milliCelsius */ | |
432 | temperature = <85000>; | |
433 | hysteresis = <2000>; | |
434 | type = "passive"; | |
435 | }; | |
436 | ||
a5ce7a3d QS |
437 | cpu_alert1: cpu_alert1 { |
438 | /* milliCelsius */ | |
439 | temperature = <90000>; | |
440 | hysteresis = <2000>; | |
441 | type = "hot"; | |
442 | }; | |
443 | ||
e846011e MR |
444 | gpu_alert1: gpu_alert1 { |
445 | /* milliCelsius */ | |
446 | temperature = <95000>; | |
447 | hysteresis = <2000>; | |
448 | type = "hot"; | |
449 | }; | |
450 | ||
a5ce7a3d QS |
451 | cpu_crit: cpu_crit { |
452 | /* milliCelsius */ | |
453 | temperature = <110000>; | |
454 | hysteresis = <2000>; | |
455 | type = "critical"; | |
456 | }; | |
457 | }; | |
458 | }; | |
459 | }; | |
35af8e4b VP |
460 | }; |
461 | ||
2c89ce4f MR |
462 | &ccu { |
463 | compatible = "allwinner,sun8i-a33-ccu"; | |
464 | }; | |
465 | ||
66c37322 MR |
466 | &mali { |
467 | operating-points-v2 = <&mali_opp_table>; | |
468 | }; | |
469 | ||
35af8e4b VP |
470 | &pio { |
471 | compatible = "allwinner,sun8i-a33-pinctrl"; | |
472 | interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>, | |
473 | <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>; | |
63c6509b CYT |
474 | |
475 | uart0_pins_b: uart0@1 { | |
1edcd36f MR |
476 | pins = "PB0", "PB1"; |
477 | function = "uart0"; | |
63c6509b CYT |
478 | }; |
479 | ||
35af8e4b | 480 | }; |
bd33544e CYT |
481 | |
482 | &usb_otg { | |
483 | compatible = "allwinner,sun8i-a33-musb"; | |
484 | }; | |
485 | ||
486 | &usbphy { | |
487 | compatible = "allwinner,sun8i-a33-usb-phy"; | |
488 | reg = <0x01c19400 0x14>, <0x01c1a800 0x4>; | |
489 | reg-names = "phy_ctrl", "pmu1"; | |
490 | }; |