[linux-2.6-block.git] / arch / arm / boot / dts / sun7i-a20.dtsi

/*
 * Copyright 2013 Maxime Ripard
 *
 * Maxime Ripard <maxime.ripard@free-electrons.com>
 *
 * The code contained herein is licensed under the GNU General Public
 * License. You may obtain a copy of the GNU General Public License
 * Version 2 or later at the following locations:
 *
 * http://www.opensource.org/licenses/gpl-license.html
 * http://www.gnu.org/copyleft/gpl.html
 */

/include/ "skeleton.dtsi"

/ {
	interrupt-parent = <&gic>;

	cpus {
		#address-cells = <1>;
		#size-cells = <0>;

		cpu@0 {
			compatible = "arm,cortex-a7";
			device_type = "cpu";
			reg = <0>;
		};

		cpu@1 {
			compatible = "arm,cortex-a7";
			device_type = "cpu";
			reg = <1>;
		};
	};

	memory {
		reg = <0x40000000 0x80000000>;
	};

	clocks {
		#address-cells = <1>;
		#size-cells = <1>;
		ranges;

		osc24M: osc24M@01c20050 {
			#clock-cells = <0>;
			compatible = "allwinner,sun4i-osc-clk";
			reg = <0x01c20050 0x4>;
			clock-frequency = <24000000>;
		};

		osc32k: osc32k {
			#clock-cells = <0>;
			compatible = "fixed-clock";
			clock-frequency = <32768>;
		};

		pll1: pll1@01c20000 {
			#clock-cells = <0>;
			compatible = "allwinner,sun4i-pll1-clk";
			reg = <0x01c20000 0x4>;
			clocks = <&osc24M>;
		};

		pll4: pll4@01c20018 {
			#clock-cells = <0>;
			compatible = "allwinner,sun4i-pll1-clk";
			reg = <0x01c20018 0x4>;
			clocks = <&osc24M>;
		};

		/*
		 * This is a dummy clock, to be used as placeholder on
		 * other mux clocks when a specific parent clock is not
		 * yet implemented. It should be dropped when the driver
		 * is complete.
		 */
		pll6: pll6 {
			#clock-cells = <0>;
			compatible = "fixed-clock";
			clock-frequency = <0>;
		};

		cpu: cpu@01c20054 {
			#clock-cells = <0>;
			compatible = "allwinner,sun4i-cpu-clk";
			reg = <0x01c20054 0x4>;
			clocks = <&osc32k>, <&osc24M>, <&pll1>, <&pll6>;
		};

		axi: axi@01c20054 {
			#clock-cells = <0>;
			compatible = "allwinner,sun4i-axi-clk";
			reg = <0x01c20054 0x4>;
			clocks = <&cpu>;
		};

		ahb: ahb@01c20054 {
			#clock-cells = <0>;
			compatible = "allwinner,sun4i-ahb-clk";
			reg = <0x01c20054 0x4>;
			clocks = <&axi>;
		};

		ahb_gates: ahb_gates@01c20060 {
			#clock-cells = <1>;
			compatible = "allwinner,sun7i-a20-ahb-gates-clk";
			reg = <0x01c20060 0x8>;
			clocks = <&ahb>;
			clock-output-names = "ahb_usb0", "ahb_ehci0",
				"ahb_ohci0", "ahb_ehci1", "ahb_ohci1",
				"ahb_ss", "ahb_dma", "ahb_bist", "ahb_mmc0",
				"ahb_mmc1", "ahb_mmc2", "ahb_mmc3", "ahb_ms",
				"ahb_nand", "ahb_sdram", "ahb_ace",
				"ahb_emac", "ahb_ts", "ahb_spi0", "ahb_spi1",
				"ahb_spi2", "ahb_spi3", "ahb_sata",
				"ahb_hstimer", "ahb_ve", "ahb_tvd", "ahb_tve0",
				"ahb_tve1", "ahb_lcd0", "ahb_lcd1", "ahb_csi0",
				"ahb_csi1", "ahb_hdmi1", "ahb_hdmi0",
				"ahb_de_be0", "ahb_de_be1", "ahb_de_fe0",
				"ahb_de_fe1", "ahb_gmac", "ahb_mp",
				"ahb_mali";
		};

		apb0: apb0@01c20054 {
			#clock-cells = <0>;
			compatible = "allwinner,sun4i-apb0-clk";
			reg = <0x01c20054 0x4>;
			clocks = <&ahb>;
		};

		apb0_gates: apb0_gates@01c20068 {
			#clock-cells = <1>;
			compatible = "allwinner,sun7i-a20-apb0-gates-clk";
			reg = <0x01c20068 0x4>;
			clocks = <&apb0>;
			clock-output-names = "apb0_codec", "apb0_spdif",
				"apb0_ac97", "apb0_iis0", "apb0_iis1",
				"apb0_pio", "apb0_ir0", "apb0_ir1",
				"apb0_iis2", "apb0_keypad";
		};

		apb1_mux: apb1_mux@01c20058 {
			#clock-cells = <0>;
			compatible = "allwinner,sun4i-apb1-mux-clk";
			reg = <0x01c20058 0x4>;
			clocks = <&osc24M>, <&pll6>, <&osc32k>;
		};

		apb1: apb1@01c20058 {
			#clock-cells = <0>;
			compatible = "allwinner,sun4i-apb1-clk";
			reg = <0x01c20058 0x4>;
			clocks = <&apb1_mux>;
		};

		apb1_gates: apb1_gates@01c2006c {
			#clock-cells = <1>;
			compatible = "allwinner,sun7i-a20-apb1-gates-clk";
			reg = <0x01c2006c 0x4>;
			clocks = <&apb1>;
			clock-output-names = "apb1_i2c0", "apb1_i2c1",
				"apb1_i2c2", "apb1_i2c3", "apb1_can",
				"apb1_scr", "apb1_ps20", "apb1_ps21",
				"apb1_i2c4", "apb1_uart0", "apb1_uart1",
				"apb1_uart2", "apb1_uart3", "apb1_uart4",
				"apb1_uart5", "apb1_uart6", "apb1_uart7";
		};
	};

	soc@01c00000 {
		compatible = "simple-bus";
		#address-cells = <1>;
		#size-cells = <1>;
		ranges;

		emac: ethernet@01c0b000 {
			compatible = "allwinner,sun4i-emac";
			reg = <0x01c0b000 0x1000>;
			interrupts = <0 55 1>;
			clocks = <&ahb_gates 17>;
			status = "disabled";
		};

		mdio@01c0b080 {
			compatible = "allwinner,sun4i-mdio";
			reg = <0x01c0b080 0x14>;
			status = "disabled";
			#address-cells = <1>;
			#size-cells = <0>;
		};

		pio: pinctrl@01c20800 {
			compatible = "allwinner,sun7i-a20-pinctrl";
			reg = <0x01c20800 0x400>;
			interrupts = <0 28 1>;
			clocks = <&apb0_gates 5>;
			gpio-controller;
			interrupt-controller;
			#address-cells = <1>;
			#size-cells = <0>;
			#gpio-cells = <3>;

			uart0_pins_a: uart0@0 {
				allwinner,pins = "PB22", "PB23";
				allwinner,function = "uart0";
				allwinner,drive = <0>;
				allwinner,pull = <0>;
			};

			uart6_pins_a: uart6@0 {
				allwinner,pins = "PI12", "PI13";
				allwinner,function = "uart6";
				allwinner,drive = <0>;
				allwinner,pull = <0>;
			};

			uart7_pins_a: uart7@0 {
				allwinner,pins = "PI20", "PI21";
				allwinner,function = "uart7";
				allwinner,drive = <0>;
				allwinner,pull = <0>;
			};

			i2c0_pins_a: i2c0@0 {
				allwinner,pins = "PB0", "PB1";
				allwinner,function = "i2c0";
				allwinner,drive = <0>;
				allwinner,pull = <0>;
			};

			i2c1_pins_a: i2c1@0 {
				allwinner,pins = "PB18", "PB19";
				allwinner,function = "i2c1";
				allwinner,drive = <0>;
				allwinner,pull = <0>;
			};

			i2c2_pins_a: i2c2@0 {
				allwinner,pins = "PB20", "PB21";
				allwinner,function = "i2c2";
				allwinner,drive = <0>;
				allwinner,pull = <0>;
			};

			emac_pins_a: emac0@0 {
				allwinner,pins = "PA0", "PA1", "PA2",
						"PA3", "PA4", "PA5", "PA6",
						"PA7", "PA8", "PA9", "PA10",
						"PA11", "PA12", "PA13", "PA14",
						"PA15", "PA16";
				allwinner,function = "emac";
				allwinner,drive = <0>;
				allwinner,pull = <0>;
			};
		};

		timer@01c20c00 {
			compatible = "allwinner,sun4i-timer";
			reg = <0x01c20c00 0x90>;
			interrupts = <0 22 1>,
				     <0 23 1>,
				     <0 24 1>,
				     <0 25 1>,
				     <0 67 1>,
				     <0 68 1>;
			clocks = <&osc24M>;
		};

		wdt: watchdog@01c20c90 {
			compatible = "allwinner,sun4i-wdt";
			reg = <0x01c20c90 0x10>;
		};

		sid: eeprom@01c23800 {
			compatible = "allwinner,sun7i-a20-sid";
			reg = <0x01c23800 0x200>;
		};

		uart0: serial@01c28000 {
			compatible = "snps,dw-apb-uart";
			reg = <0x01c28000 0x400>;
			interrupts = <0 1 1>;
			reg-shift = <2>;
			reg-io-width = <4>;
			clocks = <&apb1_gates 16>;
			status = "disabled";
		};

		uart1: serial@01c28400 {
			compatible = "snps,dw-apb-uart";
			reg = <0x01c28400 0x400>;
			interrupts = <0 2 1>;
			reg-shift = <2>;
			reg-io-width = <4>;
			clocks = <&apb1_gates 17>;
			status = "disabled";
		};

		uart2: serial@01c28800 {
			compatible = "snps,dw-apb-uart";
			reg = <0x01c28800 0x400>;
			interrupts = <0 3 1>;
			reg-shift = <2>;
			reg-io-width = <4>;
			clocks = <&apb1_gates 18>;
			status = "disabled";
		};

		uart3: serial@01c28c00 {
			compatible = "snps,dw-apb-uart";
			reg = <0x01c28c00 0x400>;
			interrupts = <0 4 1>;
			reg-shift = <2>;
			reg-io-width = <4>;
			clocks = <&apb1_gates 19>;
			status = "disabled";
		};

		uart4: serial@01c29000 {
			compatible = "snps,dw-apb-uart";
			reg = <0x01c29000 0x400>;
			interrupts = <0 17 1>;
			reg-shift = <2>;
			reg-io-width = <4>;
			clocks = <&apb1_gates 20>;
			status = "disabled";
		};

		uart5: serial@01c29400 {
			compatible = "snps,dw-apb-uart";
			reg = <0x01c29400 0x400>;
			interrupts = <0 18 1>;
			reg-shift = <2>;
			reg-io-width = <4>;
			clocks = <&apb1_gates 21>;
			status = "disabled";
		};

		uart6: serial@01c29800 {
			compatible = "snps,dw-apb-uart";
			reg = <0x01c29800 0x400>;
			interrupts = <0 19 1>;
			reg-shift = <2>;
			reg-io-width = <4>;
			clocks = <&apb1_gates 22>;
			status = "disabled";
		};

		uart7: serial@01c29c00 {
			compatible = "snps,dw-apb-uart";
			reg = <0x01c29c00 0x400>;
			interrupts = <0 20 1>;
			reg-shift = <2>;
			reg-io-width = <4>;
			clocks = <&apb1_gates 23>;
			status = "disabled";
		};

		i2c0: i2c@01c2ac00 {
			compatible = "allwinner,sun4i-i2c";
			reg = <0x01c2ac00 0x400>;
			interrupts = <0 7 1>;
			clocks = <&apb1_gates 0>;
			clock-frequency = <100000>;
			status = "disabled";
		};

		i2c1: i2c@01c2b000 {
			compatible = "allwinner,sun4i-i2c";
			reg = <0x01c2b000 0x400>;
			interrupts = <0 8 1>;
			clocks = <&apb1_gates 1>;
			clock-frequency = <100000>;
			status = "disabled";
		};

		i2c2: i2c@01c2b400 {
			compatible = "allwinner,sun4i-i2c";
			reg = <0x01c2b400 0x400>;
			interrupts = <0 9 1>;
			clocks = <&apb1_gates 2>;
			clock-frequency = <100000>;
			status = "disabled";
		};

		i2c3: i2c@01c2b800 {
			compatible = "allwinner,sun4i-i2c";
			reg = <0x01c2b800 0x400>;
			interrupts = <0 88 1>;
			clocks = <&apb1_gates 3>;
			clock-frequency = <100000>;
			status = "disabled";
		};

		i2c4: i2c@01c2bc00 {
			compatible = "allwinner,sun4i-i2c";
			reg = <0x01c2bc00 0x400>;
			interrupts = <0 89 1>;
			clocks = <&apb1_gates 15>;
			clock-frequency = <100000>;
			status = "disabled";
		};

		gic: interrupt-controller@01c81000 {
			compatible = "arm,cortex-a7-gic", "arm,cortex-a15-gic";
			reg = <0x01c81000 0x1000>,
			      <0x01c82000 0x1000>,
			      <0x01c84000 0x2000>,
			      <0x01c86000 0x2000>;
			interrupt-controller;
			#interrupt-cells = <3>;
			interrupts = <1 9 0xf04>;
		};
	};
};
Commit	Line	Data
4790ecfa MR	1	/*
	2	* Copyright 2013 Maxime Ripard
	3	*
	4	* Maxime Ripard <maxime.ripard@free-electrons.com>
	5	*
	6	* The code contained herein is licensed under the GNU General Public
	7	* License. You may obtain a copy of the GNU General Public License
	8	* Version 2 or later at the following locations:
	9	*
	10	* http://www.opensource.org/licenses/gpl-license.html
	11	* http://www.gnu.org/copyleft/gpl.html
	12	*/
	13
	14	/include/ "skeleton.dtsi"
	15
	16	/ {
	17	interrupt-parent = <&gic>;
	18
	19	cpus {
	20	#address-cells = <1>;
	21	#size-cells = <0>;
	22
	23	cpu@0 {
	24	compatible = "arm,cortex-a7";
	25	device_type = "cpu";
	26	reg = <0>;
	27	};
	28
	29	cpu@1 {
	30	compatible = "arm,cortex-a7";
	31	device_type = "cpu";
	32	reg = <1>;
	33	};
	34	};
	35
	36	memory {
	37	reg = <0x40000000 0x80000000>;
	38	};
	39
	40	clocks {
	41	#address-cells = <1>;
	42	#size-cells = <1>;
	43	ranges;
	44
	45	osc24M: osc24M@01c20050 {
	46	#clock-cells = <0>;
de7dc935 MR	47	compatible = "allwinner,sun4i-osc-clk";
de7dc935 MR	48	reg = <0x01c20050 0x4>;
4790ecfa MR	49	clock-frequency = <24000000>;
	50	};
	51
	52	osc32k: osc32k {
	53	#clock-cells = <0>;
	54	compatible = "fixed-clock";
	55	clock-frequency = <32768>;
	56	};
de7dc935 MR	57
	58	pll1: pll1@01c20000 {
	59	#clock-cells = <0>;
	60	compatible = "allwinner,sun4i-pll1-clk";
	61	reg = <0x01c20000 0x4>;
	62	clocks = <&osc24M>;
	63	};
	64
ec5589f7 EL	65	pll4: pll4@01c20018 {
	66	#clock-cells = <0>;
	67	compatible = "allwinner,sun4i-pll1-clk";
	68	reg = <0x01c20018 0x4>;
	69	clocks = <&osc24M>;
	70	};
	71
de7dc935 MR	72	/*
	73	* This is a dummy clock, to be used as placeholder on
	74	* other mux clocks when a specific parent clock is not
	75	* yet implemented. It should be dropped when the driver
	76	* is complete.
	77	*/
	78	pll6: pll6 {
	79	#clock-cells = <0>;
	80	compatible = "fixed-clock";
	81	clock-frequency = <0>;
	82	};
	83
	84	cpu: cpu@01c20054 {
	85	#clock-cells = <0>;
	86	compatible = "allwinner,sun4i-cpu-clk";
	87	reg = <0x01c20054 0x4>;
	88	clocks = <&osc32k>, <&osc24M>, <&pll1>, <&pll6>;
	89	};
	90
	91	axi: axi@01c20054 {
	92	#clock-cells = <0>;
	93	compatible = "allwinner,sun4i-axi-clk";
	94	reg = <0x01c20054 0x4>;
	95	clocks = <&cpu>;
	96	};
	97
	98	ahb: ahb@01c20054 {
	99	#clock-cells = <0>;
	100	compatible = "allwinner,sun4i-ahb-clk";
	101	reg = <0x01c20054 0x4>;
	102	clocks = <&axi>;
	103	};
	104
	105	ahb_gates: ahb_gates@01c20060 {
	106	#clock-cells = <1>;
	107	compatible = "allwinner,sun7i-a20-ahb-gates-clk";
	108	reg = <0x01c20060 0x8>;
	109	clocks = <&ahb>;
	110	clock-output-names = "ahb_usb0", "ahb_ehci0",
	111	"ahb_ohci0", "ahb_ehci1", "ahb_ohci1",
	112	"ahb_ss", "ahb_dma", "ahb_bist", "ahb_mmc0",
	113	"ahb_mmc1", "ahb_mmc2", "ahb_mmc3", "ahb_ms",
	114	"ahb_nand", "ahb_sdram", "ahb_ace",
	115	"ahb_emac", "ahb_ts", "ahb_spi0", "ahb_spi1",
	116	"ahb_spi2", "ahb_spi3", "ahb_sata",
	117	"ahb_hstimer", "ahb_ve", "ahb_tvd", "ahb_tve0",
	118	"ahb_tve1", "ahb_lcd0", "ahb_lcd1", "ahb_csi0",
	119	"ahb_csi1", "ahb_hdmi1", "ahb_hdmi0",
	120	"ahb_de_be0", "ahb_de_be1", "ahb_de_fe0",
	121	"ahb_de_fe1", "ahb_gmac", "ahb_mp",
	122	"ahb_mali";
	123	};
	124
	125	apb0: apb0@01c20054 {
	126	#clock-cells = <0>;
	127	compatible = "allwinner,sun4i-apb0-clk";
	128	reg = <0x01c20054 0x4>;
	129	clocks = <&ahb>;
	130	};
	131
	132	apb0_gates: apb0_gates@01c20068 {
	133	#clock-cells = <1>;
	134	compatible = "allwinner,sun7i-a20-apb0-gates-clk";
	135	reg = <0x01c20068 0x4>;
136	clocks = <&apb0>;
137	clock-output-names = "apb0_codec", "apb0_spdif",
138	"apb0_ac97", "apb0_iis0", "apb0_iis1",
139	"apb0_pio", "apb0_ir0", "apb0_ir1",
140	"apb0_iis2", "apb0_keypad";
141	};
142
143	apb1_mux: apb1_mux@01c20058 {
144	#clock-cells = <0>;
145	compatible = "allwinner,sun4i-apb1-mux-clk";
146	reg = <0x01c20058 0x4>;
147	clocks = <&osc24M>, <&pll6>, <&osc32k>;
148	};
149
150	apb1: apb1@01c20058 {
151	#clock-cells = <0>;
152	compatible = "allwinner,sun4i-apb1-clk";
153	reg = <0x01c20058 0x4>;
154	clocks = <&apb1_mux>;
155	};
156
157	apb1_gates: apb1_gates@01c2006c {
158	#clock-cells = <1>;
159	compatible = "allwinner,sun7i-a20-apb1-gates-clk";
160	reg = <0x01c2006c 0x4>;
161	clocks = <&apb1>;
162	clock-output-names = "apb1_i2c0", "apb1_i2c1",
163	"apb1_i2c2", "apb1_i2c3", "apb1_can",
164	"apb1_scr", "apb1_ps20", "apb1_ps21",
165	"apb1_i2c4", "apb1_uart0", "apb1_uart1",
166	"apb1_uart2", "apb1_uart3", "apb1_uart4",
167	"apb1_uart5", "apb1_uart6", "apb1_uart7";
168	};
4790ecfa MR	169	};
	170
	171	soc@01c00000 {
	172	compatible = "simple-bus";
	173	#address-cells = <1>;
	174	#size-cells = <1>;
	175	ranges;
	176
2e804d03 MR	177	emac: ethernet@01c0b000 {
	178	compatible = "allwinner,sun4i-emac";
	179	reg = <0x01c0b000 0x1000>;
	180	interrupts = <0 55 1>;
	181	clocks = <&ahb_gates 17>;
	182	status = "disabled";
	183	};
	184
	185	mdio@01c0b080 {
	186	compatible = "allwinner,sun4i-mdio";
	187	reg = <0x01c0b080 0x14>;
	188	status = "disabled";
	189	#address-cells = <1>;
	190	#size-cells = <0>;
	191	};
	192
17eac031 MR	193	pio: pinctrl@01c20800 {
	194	compatible = "allwinner,sun7i-a20-pinctrl";
	195	reg = <0x01c20800 0x400>;
	196	interrupts = <0 28 1>;
de7dc935	197	clocks = <&apb0_gates 5>;
17eac031 MR	198	gpio-controller;
	199	interrupt-controller;
	200	#address-cells = <1>;
	201	#size-cells = <0>;
	202	#gpio-cells = <3>;
9f229ba9 MR	203
	204	uart0_pins_a: uart0@0 {
	205	allwinner,pins = "PB22", "PB23";
	206	allwinner,function = "uart0";
	207	allwinner,drive = <0>;
	208	allwinner,pull = <0>;
	209	};
	210
	211	uart6_pins_a: uart6@0 {
	212	allwinner,pins = "PI12", "PI13";
	213	allwinner,function = "uart6";
	214	allwinner,drive = <0>;
	215	allwinner,pull = <0>;
	216	};
	217
	218	uart7_pins_a: uart7@0 {
	219	allwinner,pins = "PI20", "PI21";
	220	allwinner,function = "uart7";
	221	allwinner,drive = <0>;
	222	allwinner,pull = <0>;
	223	};
756084c5	224
e5496a31 MR	225	i2c0_pins_a: i2c0@0 {
	226	allwinner,pins = "PB0", "PB1";
	227	allwinner,function = "i2c0";
	228	allwinner,drive = <0>;
	229	allwinner,pull = <0>;
	230	};
	231
	232	i2c1_pins_a: i2c1@0 {
	233	allwinner,pins = "PB18", "PB19";
	234	allwinner,function = "i2c1";
	235	allwinner,drive = <0>;
	236	allwinner,pull = <0>;
	237	};
	238
	239	i2c2_pins_a: i2c2@0 {
	240	allwinner,pins = "PB20", "PB21";
	241	allwinner,function = "i2c2";
	242	allwinner,drive = <0>;
	243	allwinner,pull = <0>;
	244	};
	245
756084c5 MR	246	emac_pins_a: emac0@0 {
	247	allwinner,pins = "PA0", "PA1", "PA2",
	248	"PA3", "PA4", "PA5", "PA6",
	249	"PA7", "PA8", "PA9", "PA10",
	250	"PA11", "PA12", "PA13", "PA14",
	251	"PA15", "PA16";
	252	allwinner,function = "emac";
	253	allwinner,drive = <0>;
	254	allwinner,pull = <0>;
	255	};
17eac031 MR	256	};
17eac031 MR	257
4790ecfa MR	258	timer@01c20c00 {
	259	compatible = "allwinner,sun4i-timer";
	260	reg = <0x01c20c00 0x90>;
	261	interrupts = <0 22 1>,
	262	<0 23 1>,
	263	<0 24 1>,
	264	<0 25 1>,
	265	<0 67 1>,
	266	<0 68 1>;
	267	clocks = <&osc24M>;
	268	};
	269
	270	wdt: watchdog@01c20c90 {
	271	compatible = "allwinner,sun4i-wdt";
	272	reg = <0x01c20c90 0x10>;
	273	};
	274
2bad969f OS	275	sid: eeprom@01c23800 {
	276	compatible = "allwinner,sun7i-a20-sid";
	277	reg = <0x01c23800 0x200>;
	278	};
	279
4790ecfa MR	280	uart0: serial@01c28000 {
	281	compatible = "snps,dw-apb-uart";
	282	reg = <0x01c28000 0x400>;
	283	interrupts = <0 1 1>;
	284	reg-shift = <2>;
	285	reg-io-width = <4>;
de7dc935	286	clocks = <&apb1_gates 16>;
4790ecfa MR	287	status = "disabled";
	288	};
	289
	290	uart1: serial@01c28400 {
	291	compatible = "snps,dw-apb-uart";
	292	reg = <0x01c28400 0x400>;
	293	interrupts = <0 2 1>;
	294	reg-shift = <2>;
	295	reg-io-width = <4>;
de7dc935	296	clocks = <&apb1_gates 17>;
4790ecfa MR	297	status = "disabled";
	298	};
	299
	300	uart2: serial@01c28800 {
	301	compatible = "snps,dw-apb-uart";
	302	reg = <0x01c28800 0x400>;
	303	interrupts = <0 3 1>;
	304	reg-shift = <2>;
	305	reg-io-width = <4>;
de7dc935	306	clocks = <&apb1_gates 18>;
4790ecfa MR	307	status = "disabled";
	308	};
	309
	310	uart3: serial@01c28c00 {
	311	compatible = "snps,dw-apb-uart";
	312	reg = <0x01c28c00 0x400>;
	313	interrupts = <0 4 1>;
	314	reg-shift = <2>;
	315	reg-io-width = <4>;
de7dc935	316	clocks = <&apb1_gates 19>;
4790ecfa MR	317	status = "disabled";
	318	};
	319
	320	uart4: serial@01c29000 {
	321	compatible = "snps,dw-apb-uart";
	322	reg = <0x01c29000 0x400>;
	323	interrupts = <0 17 1>;
	324	reg-shift = <2>;
	325	reg-io-width = <4>;
de7dc935	326	clocks = <&apb1_gates 20>;
4790ecfa MR	327	status = "disabled";
	328	};
	329
	330	uart5: serial@01c29400 {
	331	compatible = "snps,dw-apb-uart";
	332	reg = <0x01c29400 0x400>;
	333	interrupts = <0 18 1>;
	334	reg-shift = <2>;
	335	reg-io-width = <4>;
de7dc935	336	clocks = <&apb1_gates 21>;
4790ecfa MR	337	status = "disabled";
	338	};
	339
	340	uart6: serial@01c29800 {
	341	compatible = "snps,dw-apb-uart";
	342	reg = <0x01c29800 0x400>;
	343	interrupts = <0 19 1>;
	344	reg-shift = <2>;
	345	reg-io-width = <4>;
de7dc935	346	clocks = <&apb1_gates 22>;
4790ecfa MR	347	status = "disabled";
	348	};
	349
	350	uart7: serial@01c29c00 {
	351	compatible = "snps,dw-apb-uart";
	352	reg = <0x01c29c00 0x400>;
	353	interrupts = <0 20 1>;
	354	reg-shift = <2>;
	355	reg-io-width = <4>;
de7dc935	356	clocks = <&apb1_gates 23>;
4790ecfa MR	357	status = "disabled";
	358	};
	359
428abbb8 MR	360	i2c0: i2c@01c2ac00 {
	361	compatible = "allwinner,sun4i-i2c";
	362	reg = <0x01c2ac00 0x400>;
	363	interrupts = <0 7 1>;
	364	clocks = <&apb1_gates 0>;
	365	clock-frequency = <100000>;
	366	status = "disabled";
	367	};
	368
	369	i2c1: i2c@01c2b000 {
	370	compatible = "allwinner,sun4i-i2c";
	371	reg = <0x01c2b000 0x400>;
	372	interrupts = <0 8 1>;
	373	clocks = <&apb1_gates 1>;
	374	clock-frequency = <100000>;
	375	status = "disabled";
	376	};
	377
	378	i2c2: i2c@01c2b400 {
	379	compatible = "allwinner,sun4i-i2c";
	380	reg = <0x01c2b400 0x400>;
	381	interrupts = <0 9 1>;
	382	clocks = <&apb1_gates 2>;
	383	clock-frequency = <100000>;
	384	status = "disabled";
	385	};
	386
	387	i2c3: i2c@01c2b800 {
	388	compatible = "allwinner,sun4i-i2c";
	389	reg = <0x01c2b800 0x400>;
	390	interrupts = <0 88 1>;
	391	clocks = <&apb1_gates 3>;
	392	clock-frequency = <100000>;
	393	status = "disabled";
	394	};
	395
	396	i2c4: i2c@01c2bc00 {
	397	compatible = "allwinner,sun4i-i2c";
	398	reg = <0x01c2bc00 0x400>;
	399	interrupts = <0 89 1>;
	400	clocks = <&apb1_gates 15>;
	401	clock-frequency = <100000>;
	402	status = "disabled";
	403	};
	404
4790ecfa MR	405	gic: interrupt-controller@01c81000 {
	406	compatible = "arm,cortex-a7-gic", "arm,cortex-a15-gic";
	407	reg = <0x01c81000 0x1000>,
	408	<0x01c82000 0x1000>,
	409	<0x01c84000 0x2000>,
	410	<0x01c86000 0x2000>;
	411	interrupt-controller;
	412	#interrupt-cells = <3>;
	413	interrupts = <1 9 0xf04>;
	414	};
	415	};
	416	};