projects / linux-2.6-block.git / blame
| Commit | Line | Data |
|---|---|---|
| 4790ecfa MR |
1 | /* |
| 2 | * Copyright 2013 Maxime Ripard | |
| 3 | * | |
| 4 | * Maxime Ripard <maxime.ripard@free-electrons.com> | |
| 5 | * | |
| 394c56ce MR |
6 | * This file is dual-licensed: you can use it either under the terms |
| 7 | * of the GPL or the X11 license, at your option. Note that this dual | |
| 8 | * licensing only applies to this file, and not this project as a | |
| 9 | * whole. | |
| 4790ecfa | 10 | * |
| 5186d83a | 11 | * a) This file is free software; you can redistribute it and/or |
| 394c56ce MR |
12 | * modify it under the terms of the GNU General Public License as |
| 13 | * published by the Free Software Foundation; either version 2 of the | |
| 14 | * License, or (at your option) any later version. | |
| 15 | * | |
| 5186d83a | 16 | * This file is distributed in the hope that it will be useful, |
| 394c56ce MR |
17 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 18 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
| 19 | * GNU General Public License for more details. | |
| 20 | * | |
| 394c56ce MR |
21 | * Or, alternatively, |
| 22 | * | |
| 23 | * b) Permission is hereby granted, free of charge, to any person | |
| 24 | * obtaining a copy of this software and associated documentation | |
| 25 | * files (the "Software"), to deal in the Software without | |
| 26 | * restriction, including without limitation the rights to use, | |
| 27 | * copy, modify, merge, publish, distribute, sublicense, and/or | |
| 28 | * sell copies of the Software, and to permit persons to whom the | |
| 29 | * Software is furnished to do so, subject to the following | |
| 30 | * conditions: | |
| 31 | * | |
| 32 | * The above copyright notice and this permission notice shall be | |
| 33 | * included in all copies or substantial portions of the Software. | |
| 34 | * | |
| 35 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, | |
| 36 | * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES | |
| 37 | * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND | |
| 38 | * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT | |
| 39 | * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, | |
| 40 | * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING | |
| 41 | * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR | |
| 42 | * OTHER DEALINGS IN THE SOFTWARE. | |
| 4790ecfa MR |
43 | */ |
| 44 | ||
| 71455701 | 45 | #include "skeleton.dtsi" |
| 4790ecfa | 46 | |
| 19882b84 | 47 | #include <dt-bindings/interrupt-controller/arm-gic.h> |
| b6d34248 | 48 | #include <dt-bindings/thermal/thermal.h> |
| 19882b84 | 49 | |
| dbe4dd1e | 50 | #include <dt-bindings/clock/sun4i-a10-pll2.h> |
| 1f9f6a78 | 51 | #include <dt-bindings/dma/sun4i-a10.h> |
| 092a0c3b | 52 | #include <dt-bindings/pinctrl/sun4i-a10.h> |
| 4790ecfa MR |
53 | |
| 54 | / { | |
| 55 | interrupt-parent = <&gic>; | |
| 56 | ||
| e751cce9 | 57 | aliases { |
| 18428f77 | 58 | ethernet0 = &gmac; |
| e751cce9 EL |
59 | }; |
| 60 | ||
| 8efc5c2b HG |
61 | chosen { |
| 62 | #address-cells = <1>; | |
| 63 | #size-cells = <1>; | |
| 64 | ranges; | |
| 65 | ||
| a9f8cda3 | 66 | framebuffer@0 { |
| d8cacaa3 MR |
67 | compatible = "allwinner,simple-framebuffer", |
| 68 | "simple-framebuffer"; | |
| a9f8cda3 | 69 | allwinner,pipeline = "de_be0-lcd0-hdmi"; |
| 01621170 HG |
70 | clocks = <&ahb_gates 36>, <&ahb_gates 43>, |
| 71 | <&ahb_gates 44>, <&de_be0_clk>, | |
| 72 | <&tcon0_ch1_clk>, <&dram_gates 26>; | |
| 8efc5c2b HG |
73 | status = "disabled"; |
| 74 | }; | |
| fd18c7ea HG |
75 | |
| 76 | framebuffer@1 { | |
| 77 | compatible = "allwinner,simple-framebuffer", | |
| 78 | "simple-framebuffer"; | |
| 79 | allwinner,pipeline = "de_be0-lcd0"; | |
| f1afc137 PL |
80 | clocks = <&ahb_gates 36>, <&ahb_gates 44>, |
| 81 | <&de_be0_clk>, <&tcon0_ch0_clk>, | |
| 82 | <&dram_gates 26>; | |
| fd18c7ea HG |
83 | status = "disabled"; |
| 84 | }; | |
| 85 | ||
| 86 | framebuffer@2 { | |
| 87 | compatible = "allwinner,simple-framebuffer", | |
| 88 | "simple-framebuffer"; | |
| 89 | allwinner,pipeline = "de_be0-lcd0-tve0"; | |
| 01621170 HG |
90 | clocks = <&ahb_gates 34>, <&ahb_gates 36>, |
| 91 | <&ahb_gates 44>, | |
| 92 | <&de_be0_clk>, <&tcon0_ch1_clk>, | |
| 4b8ccef2 | 93 | <&dram_gates 5>, <&dram_gates 26>; |
| fd18c7ea HG |
94 | status = "disabled"; |
| 95 | }; | |
| 8efc5c2b HG |
96 | }; |
| 97 | ||
| 4790ecfa MR |
98 | cpus { |
| 99 | #address-cells = <1>; | |
| 100 | #size-cells = <0>; | |
| 101 | ||
| d96b7161 | 102 | cpu0: cpu@0 { |
| 4790ecfa MR |
103 | compatible = "arm,cortex-a7"; |
| 104 | device_type = "cpu"; | |
| 105 | reg = <0>; | |
| d96b7161 CYT |
106 | clocks = <&cpu>; |
| 107 | clock-latency = <244144>; /* 8 32k periods */ | |
| 108 | operating-points = < | |
| 8358aada MR |
109 | /* kHz uV */ |
| 110 | 960000 1400000 | |
| 111 | 912000 1400000 | |
| 112 | 864000 1300000 | |
| 113 | 720000 1200000 | |
| 114 | 528000 1100000 | |
| 115 | 312000 1000000 | |
| eaeef1ad | 116 | 144000 1000000 |
| d96b7161 CYT |
117 | >; |
| 118 | #cooling-cells = <2>; | |
| 119 | cooling-min-level = <0>; | |
| 370a9b5f | 120 | cooling-max-level = <6>; |
| 4790ecfa MR |
121 | }; |
| 122 | ||
| 123 | cpu@1 { | |
| 124 | compatible = "arm,cortex-a7"; | |
| 125 | device_type = "cpu"; | |
| 126 | reg = <1>; | |
| 127 | }; | |
| 128 | }; | |
| 129 | ||
| b6d34248 CYT |
130 | thermal-zones { |
| 131 | cpu_thermal { | |
| 132 | /* milliseconds */ | |
| 133 | polling-delay-passive = <250>; | |
| 134 | polling-delay = <1000>; | |
| 135 | thermal-sensors = <&rtp>; | |
| 136 | ||
| 137 | cooling-maps { | |
| 138 | map0 { | |
| 139 | trip = <&cpu_alert0>; | |
| 140 | cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; | |
| 141 | }; | |
| 142 | }; | |
| 143 | ||
| 144 | trips { | |
| 145 | cpu_alert0: cpu_alert0 { | |
| 146 | /* milliCelsius */ | |
| 147 | temperature = <75000>; | |
| 148 | hysteresis = <2000>; | |
| 149 | type = "passive"; | |
| 150 | }; | |
| 151 | ||
| 152 | cpu_crit: cpu_crit { | |
| 153 | /* milliCelsius */ | |
| 154 | temperature = <100000>; | |
| 155 | hysteresis = <2000>; | |
| 156 | type = "critical"; | |
| 157 | }; | |
| 158 | }; | |
| 159 | }; | |
| 160 | }; | |
| 161 | ||
| 4790ecfa MR |
162 | memory { |
| 163 | reg = <0x40000000 0x80000000>; | |
| 164 | }; | |
| 165 | ||
| 7902763e MZ |
166 | timer { |
| 167 | compatible = "arm,armv7-timer"; | |
| 19882b84 MR |
168 | interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, |
| 169 | <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, | |
| 170 | <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, | |
| 171 | <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>; | |
| 7902763e MZ |
172 | }; |
| 173 | ||
| e29ea4d3 MR |
174 | pmu { |
| 175 | compatible = "arm,cortex-a7-pmu", "arm,cortex-a15-pmu"; | |
| 19882b84 MR |
176 | interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>, |
| 177 | <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>; | |
| e29ea4d3 MR |
178 | }; |
| 179 | ||
| 4790ecfa MR |
180 | clocks { |
| 181 | #address-cells = <1>; | |
| 182 | #size-cells = <1>; | |
| 183 | ranges; | |
| 184 | ||
| 06067a2f | 185 | osc24M: clk@01c20050 { |
| 4790ecfa | 186 | #clock-cells = <0>; |
| bf6534a1 | 187 | compatible = "allwinner,sun4i-a10-osc-clk"; |
| de7dc935 | 188 | reg = <0x01c20050 0x4>; |
| 4790ecfa | 189 | clock-frequency = <24000000>; |
| 06067a2f | 190 | clock-output-names = "osc24M"; |
| 4790ecfa MR |
191 | }; |
| 192 | ||
| 068655dc PL |
193 | osc3M: osc3M_clk { |
| 194 | #clock-cells = <0>; | |
| 195 | compatible = "fixed-factor-clock"; | |
| 196 | clock-div = <8>; | |
| 197 | clock-mult = <1>; | |
| 198 | clocks = <&osc24M>; | |
| 199 | clock-output-names = "osc3M"; | |
| 200 | }; | |
| 201 | ||
| 673fac74 | 202 | osc32k: clk@0 { |
| 4790ecfa MR |
203 | #clock-cells = <0>; |
| 204 | compatible = "fixed-clock"; | |
| 205 | clock-frequency = <32768>; | |
| 673fac74 | 206 | clock-output-names = "osc32k"; |
| 4790ecfa | 207 | }; |
| de7dc935 | 208 | |
| 06067a2f | 209 | pll1: clk@01c20000 { |
| de7dc935 | 210 | #clock-cells = <0>; |
| bf6534a1 | 211 | compatible = "allwinner,sun4i-a10-pll1-clk"; |
| de7dc935 MR |
212 | reg = <0x01c20000 0x4>; |
| 213 | clocks = <&osc24M>; | |
| 06067a2f | 214 | clock-output-names = "pll1"; |
| de7dc935 MR |
215 | }; |
| 216 | ||
| 88a86aaa MR |
217 | pll2: clk@01c20008 { |
| 218 | #clock-cells = <1>; | |
| 219 | compatible = "allwinner,sun4i-a10-pll2-clk"; | |
| 220 | reg = <0x01c20008 0x8>; | |
| 221 | clocks = <&osc24M>; | |
| 222 | clock-output-names = "pll2-1x", "pll2-2x", | |
| 223 | "pll2-4x", "pll2-8x"; | |
| 224 | }; | |
| 225 | ||
| 068655dc PL |
226 | pll3: clk@01c20010 { |
| 227 | #clock-cells = <0>; | |
| 228 | compatible = "allwinner,sun4i-a10-pll3-clk"; | |
| 229 | reg = <0x01c20010 0x4>; | |
| 230 | clocks = <&osc3M>; | |
| 231 | clock-output-names = "pll3"; | |
| 232 | }; | |
| 233 | ||
| 234 | pll3x2: pll3x2_clk { | |
| 235 | #clock-cells = <0>; | |
| 236 | compatible = "fixed-factor-clock"; | |
| eee25ab1 | 237 | clocks = <&pll3>; |
| 068655dc PL |
238 | clock-div = <1>; |
| 239 | clock-mult = <2>; | |
| 240 | clock-output-names = "pll3-2x"; | |
| 241 | }; | |
| 242 | ||
| 06067a2f | 243 | pll4: clk@01c20018 { |
| de7dc935 | 244 | #clock-cells = <0>; |
| 04ebcb54 | 245 | compatible = "allwinner,sun7i-a20-pll4-clk"; |
| ec5589f7 EL |
246 | reg = <0x01c20018 0x4>; |
| 247 | clocks = <&osc24M>; | |
| 06067a2f | 248 | clock-output-names = "pll4"; |
| ec5589f7 EL |
249 | }; |
| 250 | ||
| 06067a2f | 251 | pll5: clk@01c20020 { |
| c3e5e66b | 252 | #clock-cells = <1>; |
| bf6534a1 | 253 | compatible = "allwinner,sun4i-a10-pll5-clk"; |
| c3e5e66b EL |
254 | reg = <0x01c20020 0x4>; |
| 255 | clocks = <&osc24M>; | |
| 256 | clock-output-names = "pll5_ddr", "pll5_other"; | |
| 257 | }; | |
| 258 | ||
| 06067a2f | 259 | pll6: clk@01c20028 { |
| c3e5e66b | 260 | #clock-cells = <1>; |
| bf6534a1 | 261 | compatible = "allwinner,sun4i-a10-pll6-clk"; |
| c3e5e66b EL |
262 | reg = <0x01c20028 0x4>; |
| 263 | clocks = <&osc24M>; | |
| 2186df37 CYT |
264 | clock-output-names = "pll6_sata", "pll6_other", "pll6", |
| 265 | "pll6_div_4"; | |
| de7dc935 MR |
266 | }; |
| 267 | ||
| 068655dc PL |
268 | pll7: clk@01c20030 { |
| 269 | #clock-cells = <0>; | |
| 270 | compatible = "allwinner,sun4i-a10-pll3-clk"; | |
| 271 | reg = <0x01c20030 0x4>; | |
| 272 | clocks = <&osc3M>; | |
| 273 | clock-output-names = "pll7"; | |
| 274 | }; | |
| 275 | ||
| 276 | pll7x2: pll7x2_clk { | |
| 277 | #clock-cells = <0>; | |
| 278 | compatible = "fixed-factor-clock"; | |
| eee25ab1 | 279 | clocks = <&pll7>; |
| 068655dc PL |
280 | clock-div = <1>; |
| 281 | clock-mult = <2>; | |
| 282 | clock-output-names = "pll7-2x"; | |
| 283 | }; | |
| 284 | ||
| 04ebcb54 EL |
285 | pll8: clk@01c20040 { |
| 286 | #clock-cells = <0>; | |
| 287 | compatible = "allwinner,sun7i-a20-pll4-clk"; | |
| 288 | reg = <0x01c20040 0x4>; | |
| 289 | clocks = <&osc24M>; | |
| 290 | clock-output-names = "pll8"; | |
| 291 | }; | |
| 292 | ||
| de7dc935 MR |
293 | cpu: cpu@01c20054 { |
| 294 | #clock-cells = <0>; | |
| bf6534a1 | 295 | compatible = "allwinner,sun4i-a10-cpu-clk"; |
| de7dc935 | 296 | reg = <0x01c20054 0x4>; |
| c3e5e66b | 297 | clocks = <&osc32k>, <&osc24M>, <&pll1>, <&pll6 1>; |
| 06067a2f | 298 | clock-output-names = "cpu"; |
| de7dc935 MR |
299 | }; |
| 300 | ||
| 301 | axi: axi@01c20054 { | |
| 302 | #clock-cells = <0>; | |
| bf6534a1 | 303 | compatible = "allwinner,sun4i-a10-axi-clk"; |
| de7dc935 MR |
304 | reg = <0x01c20054 0x4>; |
| 305 | clocks = <&cpu>; | |
| 06067a2f | 306 | clock-output-names = "axi"; |
| de7dc935 MR |
307 | }; |
| 308 | ||
| 309 | ahb: ahb@01c20054 { | |
| 310 | #clock-cells = <0>; | |
| 2186df37 | 311 | compatible = "allwinner,sun5i-a13-ahb-clk"; |
| de7dc935 | 312 | reg = <0x01c20054 0x4>; |
| 2186df37 | 313 | clocks = <&axi>, <&pll6 3>, <&pll6 1>; |
| 06067a2f | 314 | clock-output-names = "ahb"; |
| 2186df37 CYT |
315 | /* |
| 316 | * Use PLL6 as parent, instead of CPU/AXI | |
| 317 | * which has rate changes due to cpufreq | |
| 318 | */ | |
| 319 | assigned-clocks = <&ahb>; | |
| 320 | assigned-clock-parents = <&pll6 3>; | |
| de7dc935 MR |
321 | }; |
| 322 | ||
| 06067a2f | 323 | ahb_gates: clk@01c20060 { |
| de7dc935 MR |
324 | #clock-cells = <1>; |
| 325 | compatible = "allwinner,sun7i-a20-ahb-gates-clk"; | |
| 326 | reg = <0x01c20060 0x8>; | |
| 327 | clocks = <&ahb>; | |
| 6bfe30b2 MR |
328 | clock-indices = <0>, <1>, |
| 329 | <2>, <3>, <4>, | |
| 330 | <5>, <6>, <7>, <8>, | |
| 331 | <9>, <10>, <11>, <12>, | |
| 332 | <13>, <14>, <16>, | |
| 333 | <17>, <18>, <20>, <21>, | |
| 334 | <22>, <23>, <25>, | |
| 335 | <28>, <32>, <33>, <34>, | |
| 336 | <35>, <36>, <37>, <40>, | |
| 337 | <41>, <42>, <43>, | |
| 338 | <44>, <45>, <46>, | |
| 339 | <47>, <49>, <50>, | |
| 340 | <52>; | |
| de7dc935 MR |
341 | clock-output-names = "ahb_usb0", "ahb_ehci0", |
| 342 | "ahb_ohci0", "ahb_ehci1", "ahb_ohci1", | |
| 343 | "ahb_ss", "ahb_dma", "ahb_bist", "ahb_mmc0", | |
| 344 | "ahb_mmc1", "ahb_mmc2", "ahb_mmc3", "ahb_ms", | |
| 345 | "ahb_nand", "ahb_sdram", "ahb_ace", | |
| 346 | "ahb_emac", "ahb_ts", "ahb_spi0", "ahb_spi1", | |
| 347 | "ahb_spi2", "ahb_spi3", "ahb_sata", | |
| 348 | "ahb_hstimer", "ahb_ve", "ahb_tvd", "ahb_tve0", | |
| 349 | "ahb_tve1", "ahb_lcd0", "ahb_lcd1", "ahb_csi0", | |
| 350 | "ahb_csi1", "ahb_hdmi1", "ahb_hdmi0", | |
| 351 | "ahb_de_be0", "ahb_de_be1", "ahb_de_fe0", | |
| 352 | "ahb_de_fe1", "ahb_gmac", "ahb_mp", | |
| 353 | "ahb_mali"; | |
| 354 | }; | |
| 355 | ||
| 356 | apb0: apb0@01c20054 { | |
| 357 | #clock-cells = <0>; | |
| bf6534a1 | 358 | compatible = "allwinner,sun4i-a10-apb0-clk"; |
| de7dc935 MR |
359 | reg = <0x01c20054 0x4>; |
| 360 | clocks = <&ahb>; | |
| 06067a2f | 361 | clock-output-names = "apb0"; |
| de7dc935 MR |
362 | }; |
| 363 | ||
| 06067a2f | 364 | apb0_gates: clk@01c20068 { |
| de7dc935 MR |
365 | #clock-cells = <1>; |
| 366 | compatible = "allwinner,sun7i-a20-apb0-gates-clk"; | |
| 367 | reg = <0x01c20068 0x4>; | |
| 368 | clocks = <&apb0>; | |
| 6bfe30b2 MR |
369 | clock-indices = <0>, <1>, |
| 370 | <2>, <3>, <4>, | |
| 371 | <5>, <6>, <7>, | |
| 372 | <8>, <10>; | |
| de7dc935 | 373 | clock-output-names = "apb0_codec", "apb0_spdif", |
| 60ecb1ef | 374 | "apb0_ac97", "apb0_i2s0", "apb0_i2s1", |
| de7dc935 | 375 | "apb0_pio", "apb0_ir0", "apb0_ir1", |
| 60ecb1ef | 376 | "apb0_i2s2", "apb0_keypad"; |
| de7dc935 MR |
377 | }; |
| 378 | ||
| acbcc0f0 | 379 | apb1: clk@01c20058 { |
| de7dc935 | 380 | #clock-cells = <0>; |
| bf6534a1 | 381 | compatible = "allwinner,sun4i-a10-apb1-clk"; |
| de7dc935 | 382 | reg = <0x01c20058 0x4>; |
| acbcc0f0 | 383 | clocks = <&osc24M>, <&pll6 1>, <&osc32k>; |
| 06067a2f | 384 | clock-output-names = "apb1"; |
| de7dc935 MR |
385 | }; |
| 386 | ||
| 06067a2f | 387 | apb1_gates: clk@01c2006c { |
| de7dc935 MR |
388 | #clock-cells = <1>; |
| 389 | compatible = "allwinner,sun7i-a20-apb1-gates-clk"; | |
| 390 | reg = <0x01c2006c 0x4>; | |
| 391 | clocks = <&apb1>; | |
| 6bfe30b2 MR |
392 | clock-indices = <0>, <1>, |
| 393 | <2>, <3>, <4>, | |
| 394 | <5>, <6>, <7>, | |
| 395 | <15>, <16>, <17>, | |
| 396 | <18>, <19>, <20>, | |
| 397 | <21>, <22>, <23>; | |
| de7dc935 MR |
398 | clock-output-names = "apb1_i2c0", "apb1_i2c1", |
| 399 | "apb1_i2c2", "apb1_i2c3", "apb1_can", | |
| 400 | "apb1_scr", "apb1_ps20", "apb1_ps21", | |
| 401 | "apb1_i2c4", "apb1_uart0", "apb1_uart1", | |
| 402 | "apb1_uart2", "apb1_uart3", "apb1_uart4", | |
| 403 | "apb1_uart5", "apb1_uart6", "apb1_uart7"; | |
| 404 | }; | |
| 1c92b95b EL |
405 | |
| 406 | nand_clk: clk@01c20080 { | |
| 407 | #clock-cells = <0>; | |
| bf6534a1 | 408 | compatible = "allwinner,sun4i-a10-mod0-clk"; |
| 1c92b95b EL |
409 | reg = <0x01c20080 0x4>; |
| 410 | clocks = <&osc24M>, <&pll6 1>, <&pll5 1>; | |
| 411 | clock-output-names = "nand"; | |
| 412 | }; | |
| 413 | ||
| 414 | ms_clk: clk@01c20084 { | |
| 415 | #clock-cells = <0>; | |
| bf6534a1 | 416 | compatible = "allwinner,sun4i-a10-mod0-clk"; |
| 1c92b95b EL |
417 | reg = <0x01c20084 0x4>; |
| 418 | clocks = <&osc24M>, <&pll6 1>, <&pll5 1>; | |
| 419 | clock-output-names = "ms"; | |
| 420 | }; | |
| 421 | ||
| 422 | mmc0_clk: clk@01c20088 { | |
| d8c3a392 MR |
423 | #clock-cells = <1>; |
| 424 | compatible = "allwinner,sun4i-a10-mmc-clk"; | |
| 1c92b95b EL |
425 | reg = <0x01c20088 0x4>; |
| 426 | clocks = <&osc24M>, <&pll6 1>, <&pll5 1>; | |
| d8c3a392 MR |
427 | clock-output-names = "mmc0", |
| 428 | "mmc0_output", | |
| 429 | "mmc0_sample"; | |
| 1c92b95b EL |
430 | }; |
| 431 | ||
| 432 | mmc1_clk: clk@01c2008c { | |
| d8c3a392 MR |
433 | #clock-cells = <1>; |
| 434 | compatible = "allwinner,sun4i-a10-mmc-clk"; | |
| 1c92b95b EL |
435 | reg = <0x01c2008c 0x4>; |
| 436 | clocks = <&osc24M>, <&pll6 1>, <&pll5 1>; | |
| d8c3a392 MR |
437 | clock-output-names = "mmc1", |
| 438 | "mmc1_output", | |
| 439 | "mmc1_sample"; | |
| 1c92b95b EL |
440 | }; |
| 441 | ||
| 442 | mmc2_clk: clk@01c20090 { | |
| d8c3a392 MR |
443 | #clock-cells = <1>; |
| 444 | compatible = "allwinner,sun4i-a10-mmc-clk"; | |
| 1c92b95b EL |
445 | reg = <0x01c20090 0x4>; |
| 446 | clocks = <&osc24M>, <&pll6 1>, <&pll5 1>; | |
| d8c3a392 MR |
447 | clock-output-names = "mmc2", |
| 448 | "mmc2_output", | |
| 449 | "mmc2_sample"; | |
| 1c92b95b EL |
450 | }; |
| 451 | ||
| 452 | mmc3_clk: clk@01c20094 { | |
| d8c3a392 MR |
453 | #clock-cells = <1>; |
| 454 | compatible = "allwinner,sun4i-a10-mmc-clk"; | |
| 1c92b95b EL |
455 | reg = <0x01c20094 0x4>; |
| 456 | clocks = <&osc24M>, <&pll6 1>, <&pll5 1>; | |
| d8c3a392 MR |
457 | clock-output-names = "mmc3", |
| 458 | "mmc3_output", | |
| 459 | "mmc3_sample"; | |
| 1c92b95b EL |
460 | }; |
| 461 | ||
| 462 | ts_clk: clk@01c20098 { | |
| 463 | #clock-cells = <0>; | |
| bf6534a1 | 464 | compatible = "allwinner,sun4i-a10-mod0-clk"; |
| 1c92b95b EL |
465 | reg = <0x01c20098 0x4>; |
| 466 | clocks = <&osc24M>, <&pll6 1>, <&pll5 1>; | |
| 467 | clock-output-names = "ts"; | |
| 468 | }; | |
| 469 | ||
| 470 | ss_clk: clk@01c2009c { | |
| 471 | #clock-cells = <0>; | |
| bf6534a1 | 472 | compatible = "allwinner,sun4i-a10-mod0-clk"; |
| 1c92b95b EL |
473 | reg = <0x01c2009c 0x4>; |
| 474 | clocks = <&osc24M>, <&pll6 1>, <&pll5 1>; | |
| 475 | clock-output-names = "ss"; | |
| 476 | }; | |
| 477 | ||
| 478 | spi0_clk: clk@01c200a0 { | |
| 479 | #clock-cells = <0>; | |
| bf6534a1 | 480 | compatible = "allwinner,sun4i-a10-mod0-clk"; |
| 1c92b95b EL |
481 | reg = <0x01c200a0 0x4>; |
| 482 | clocks = <&osc24M>, <&pll6 1>, <&pll5 1>; | |
| 483 | clock-output-names = "spi0"; | |
| 484 | }; | |
| 485 | ||
| 486 | spi1_clk: clk@01c200a4 { | |
| 487 | #clock-cells = <0>; | |
| bf6534a1 | 488 | compatible = "allwinner,sun4i-a10-mod0-clk"; |
| 1c92b95b EL |
489 | reg = <0x01c200a4 0x4>; |
| 490 | clocks = <&osc24M>, <&pll6 1>, <&pll5 1>; | |
| 491 | clock-output-names = "spi1"; | |
| 492 | }; | |
| 493 | ||
| 494 | spi2_clk: clk@01c200a8 { | |
| 495 | #clock-cells = <0>; | |
| bf6534a1 | 496 | compatible = "allwinner,sun4i-a10-mod0-clk"; |
| 1c92b95b EL |
497 | reg = <0x01c200a8 0x4>; |
| 498 | clocks = <&osc24M>, <&pll6 1>, <&pll5 1>; | |
| 499 | clock-output-names = "spi2"; | |
| 500 | }; | |
| 501 | ||
| 502 | pata_clk: clk@01c200ac { | |
| 503 | #clock-cells = <0>; | |
| bf6534a1 | 504 | compatible = "allwinner,sun4i-a10-mod0-clk"; |
| 1c92b95b EL |
505 | reg = <0x01c200ac 0x4>; |
| 506 | clocks = <&osc24M>, <&pll6 1>, <&pll5 1>; | |
| 507 | clock-output-names = "pata"; | |
| 508 | }; | |
| 509 | ||
| 510 | ir0_clk: clk@01c200b0 { | |
| 511 | #clock-cells = <0>; | |
| bf6534a1 | 512 | compatible = "allwinner,sun4i-a10-mod0-clk"; |
| 1c92b95b EL |
513 | reg = <0x01c200b0 0x4>; |
| 514 | clocks = <&osc24M>, <&pll6 1>, <&pll5 1>; | |
| 515 | clock-output-names = "ir0"; | |
| 516 | }; | |
| 517 | ||
| 518 | ir1_clk: clk@01c200b4 { | |
| 519 | #clock-cells = <0>; | |
| bf6534a1 | 520 | compatible = "allwinner,sun4i-a10-mod0-clk"; |
| 1c92b95b EL |
521 | reg = <0x01c200b4 0x4>; |
| 522 | clocks = <&osc24M>, <&pll6 1>, <&pll5 1>; | |
| 523 | clock-output-names = "ir1"; | |
| 524 | }; | |
| 525 | ||
| 60ecb1ef EL |
526 | i2s0_clk: clk@01c200b8 { |
| 527 | #clock-cells = <0>; | |
| 528 | compatible = "allwinner,sun4i-a10-mod1-clk"; | |
| 529 | reg = <0x01c200b8 0x4>; | |
| 530 | clocks = <&pll2 SUN4I_A10_PLL2_8X>, | |
| 531 | <&pll2 SUN4I_A10_PLL2_4X>, | |
| 532 | <&pll2 SUN4I_A10_PLL2_2X>, | |
| 533 | <&pll2 SUN4I_A10_PLL2_1X>; | |
| 534 | clock-output-names = "i2s0"; | |
| 535 | }; | |
| 536 | ||
| 537 | ac97_clk: clk@01c200bc { | |
| 538 | #clock-cells = <0>; | |
| 539 | compatible = "allwinner,sun4i-a10-mod1-clk"; | |
| 540 | reg = <0x01c200bc 0x4>; | |
| 541 | clocks = <&pll2 SUN4I_A10_PLL2_8X>, | |
| 542 | <&pll2 SUN4I_A10_PLL2_4X>, | |
| 543 | <&pll2 SUN4I_A10_PLL2_2X>, | |
| 544 | <&pll2 SUN4I_A10_PLL2_1X>; | |
| 545 | clock-output-names = "ac97"; | |
| 546 | }; | |
| 547 | ||
| 90b7a489 MC |
548 | spdif_clk: clk@01c200c0 { |
| 549 | #clock-cells = <0>; | |
| 550 | compatible = "allwinner,sun4i-a10-mod1-clk"; | |
| 551 | reg = <0x01c200c0 0x4>; | |
| 552 | clocks = <&pll2 SUN4I_A10_PLL2_8X>, | |
| 553 | <&pll2 SUN4I_A10_PLL2_4X>, | |
| 554 | <&pll2 SUN4I_A10_PLL2_2X>, | |
| 555 | <&pll2 SUN4I_A10_PLL2_1X>; | |
| 556 | clock-output-names = "spdif"; | |
| 557 | }; | |
| 558 | ||
| 6f1606bf YJ |
559 | keypad_clk: clk@01c200c4 { |
| 560 | #clock-cells = <0>; | |
| 561 | compatible = "allwinner,sun4i-a10-mod0-clk"; | |
| 562 | reg = <0x01c200c4 0x4>; | |
| 563 | clocks = <&osc24M>; | |
| 564 | clock-output-names = "keypad"; | |
| 565 | }; | |
| 566 | ||
| 434e41b3 RB |
567 | usb_clk: clk@01c200cc { |
| 568 | #clock-cells = <1>; | |
| 8358aada | 569 | #reset-cells = <1>; |
| 434e41b3 RB |
570 | compatible = "allwinner,sun4i-a10-usb-clk"; |
| 571 | reg = <0x01c200cc 0x4>; | |
| 572 | clocks = <&pll6 1>; | |
| d8cacaa3 MR |
573 | clock-output-names = "usb_ohci0", "usb_ohci1", |
| 574 | "usb_phy"; | |
| 434e41b3 RB |
575 | }; |
| 576 | ||
| 1c92b95b EL |
577 | spi3_clk: clk@01c200d4 { |
| 578 | #clock-cells = <0>; | |
| bf6534a1 | 579 | compatible = "allwinner,sun4i-a10-mod0-clk"; |
| 1c92b95b EL |
580 | reg = <0x01c200d4 0x4>; |
| 581 | clocks = <&osc24M>, <&pll6 1>, <&pll5 1>; | |
| 582 | clock-output-names = "spi3"; | |
| 583 | }; | |
| 118c07ae | 584 | |
| 60ecb1ef EL |
585 | i2s1_clk: clk@01c200d8 { |
| 586 | #clock-cells = <0>; | |
| 587 | compatible = "allwinner,sun4i-a10-mod1-clk"; | |
| 588 | reg = <0x01c200d8 0x4>; | |
| 589 | clocks = <&pll2 SUN4I_A10_PLL2_8X>, | |
| 590 | <&pll2 SUN4I_A10_PLL2_4X>, | |
| 591 | <&pll2 SUN4I_A10_PLL2_2X>, | |
| 592 | <&pll2 SUN4I_A10_PLL2_1X>; | |
| 593 | clock-output-names = "i2s1"; | |
| 594 | }; | |
| 595 | ||
| 596 | i2s2_clk: clk@01c200dc { | |
| 597 | #clock-cells = <0>; | |
| 598 | compatible = "allwinner,sun4i-a10-mod1-clk"; | |
| 599 | reg = <0x01c200dc 0x4>; | |
| 600 | clocks = <&pll2 SUN4I_A10_PLL2_8X>, | |
| 601 | <&pll2 SUN4I_A10_PLL2_4X>, | |
| 602 | <&pll2 SUN4I_A10_PLL2_2X>, | |
| 603 | <&pll2 SUN4I_A10_PLL2_1X>; | |
| 604 | clock-output-names = "i2s2"; | |
| 605 | }; | |
| 606 | ||
| 0b4bf5a5 CYT |
607 | dram_gates: clk@01c20100 { |
| 608 | #clock-cells = <1>; | |
| 609 | compatible = "allwinner,sun4i-a10-dram-gates-clk"; | |
| 610 | reg = <0x01c20100 0x4>; | |
| 611 | clocks = <&pll5 0>; | |
| 612 | clock-indices = <0>, | |
| 613 | <1>, <2>, | |
| 614 | <3>, | |
| 615 | <4>, | |
| 616 | <5>, <6>, | |
| 617 | <15>, | |
| 618 | <24>, <25>, | |
| 619 | <26>, <27>, | |
| 620 | <28>, <29>; | |
| 621 | clock-output-names = "dram_ve", | |
| 622 | "dram_csi0", "dram_csi1", | |
| 623 | "dram_ts", | |
| 624 | "dram_tvd", | |
| 625 | "dram_tve0", "dram_tve1", | |
| 626 | "dram_output", | |
| 627 | "dram_de_fe1", "dram_de_fe0", | |
| 628 | "dram_de_be0", "dram_de_be1", | |
| 629 | "dram_de_mp", "dram_ace"; | |
| 630 | }; | |
| 631 | ||
| f1afc137 PL |
632 | de_be0_clk: clk@01c20104 { |
| 633 | #clock-cells = <0>; | |
| 634 | #reset-cells = <0>; | |
| 635 | compatible = "allwinner,sun4i-a10-display-clk"; | |
| 636 | reg = <0x01c20104 0x4>; | |
| 637 | clocks = <&pll3>, <&pll7>, <&pll5 1>; | |
| 638 | clock-output-names = "de-be0"; | |
| 639 | }; | |
| 640 | ||
| 641 | de_be1_clk: clk@01c20108 { | |
| 642 | #clock-cells = <0>; | |
| 643 | #reset-cells = <0>; | |
| 644 | compatible = "allwinner,sun4i-a10-display-clk"; | |
| 645 | reg = <0x01c20108 0x4>; | |
| 646 | clocks = <&pll3>, <&pll7>, <&pll5 1>; | |
| 647 | clock-output-names = "de-be1"; | |
| 648 | }; | |
| 649 | ||
| 650 | de_fe0_clk: clk@01c2010c { | |
| 651 | #clock-cells = <0>; | |
| 652 | #reset-cells = <0>; | |
| 653 | compatible = "allwinner,sun4i-a10-display-clk"; | |
| 654 | reg = <0x01c2010c 0x4>; | |
| 655 | clocks = <&pll3>, <&pll7>, <&pll5 1>; | |
| 656 | clock-output-names = "de-fe0"; | |
| 657 | }; | |
| 658 | ||
| 659 | de_fe1_clk: clk@01c20110 { | |
| 660 | #clock-cells = <0>; | |
| 661 | #reset-cells = <0>; | |
| 662 | compatible = "allwinner,sun4i-a10-display-clk"; | |
| 663 | reg = <0x01c20110 0x4>; | |
| 664 | clocks = <&pll3>, <&pll7>, <&pll5 1>; | |
| 665 | clock-output-names = "de-fe1"; | |
| 666 | }; | |
| 667 | ||
| 668 | tcon0_ch0_clk: clk@01c20118 { | |
| 669 | #clock-cells = <0>; | |
| 670 | #reset-cells = <1>; | |
| 671 | compatible = "allwinner,sun4i-a10-tcon-ch0-clk"; | |
| 672 | reg = <0x01c20118 0x4>; | |
| 673 | clocks = <&pll3>, <&pll7>, <&pll3x2>, <&pll7x2>; | |
| 674 | clock-output-names = "tcon0-ch0-sclk"; | |
| 675 | ||
| 676 | }; | |
| 677 | ||
| 678 | tcon1_ch0_clk: clk@01c2011c { | |
| 679 | #clock-cells = <0>; | |
| 680 | #reset-cells = <1>; | |
| 681 | compatible = "allwinner,sun4i-a10-tcon-ch1-clk"; | |
| 682 | reg = <0x01c2011c 0x4>; | |
| 683 | clocks = <&pll3>, <&pll7>, <&pll3x2>, <&pll7x2>; | |
| 684 | clock-output-names = "tcon1-ch0-sclk"; | |
| 685 | ||
| 686 | }; | |
| 687 | ||
| 688 | tcon0_ch1_clk: clk@01c2012c { | |
| 689 | #clock-cells = <0>; | |
| 690 | compatible = "allwinner,sun4i-a10-tcon-ch0-clk"; | |
| 691 | reg = <0x01c2012c 0x4>; | |
| 692 | clocks = <&pll3>, <&pll7>, <&pll3x2>, <&pll7x2>; | |
| 693 | clock-output-names = "tcon0-ch1-sclk"; | |
| 694 | ||
| 695 | }; | |
| 696 | ||
| 697 | tcon1_ch1_clk: clk@01c20130 { | |
| 698 | #clock-cells = <0>; | |
| 699 | compatible = "allwinner,sun4i-a10-tcon-ch1-clk"; | |
| 700 | reg = <0x01c20130 0x4>; | |
| 701 | clocks = <&pll3>, <&pll7>, <&pll3x2>, <&pll7x2>; | |
| 702 | clock-output-names = "tcon1-ch1-sclk"; | |
| 703 | ||
| 704 | }; | |
| 705 | ||
| f0571ab1 CYT |
706 | ve_clk: clk@01c2013c { |
| 707 | #clock-cells = <0>; | |
| 708 | #reset-cells = <0>; | |
| 709 | compatible = "allwinner,sun4i-a10-ve-clk"; | |
| 710 | reg = <0x01c2013c 0x4>; | |
| 711 | clocks = <&pll4>; | |
| 712 | clock-output-names = "ve"; | |
| 713 | }; | |
| 714 | ||
| dbe4dd1e MR |
715 | codec_clk: clk@01c20140 { |
| 716 | #clock-cells = <0>; | |
| 717 | compatible = "allwinner,sun4i-a10-codec-clk"; | |
| 718 | reg = <0x01c20140 0x4>; | |
| 719 | clocks = <&pll2 SUN4I_A10_PLL2_1X>; | |
| 720 | clock-output-names = "codec"; | |
| 721 | }; | |
| 722 | ||
| 118c07ae EL |
723 | mbus_clk: clk@01c2015c { |
| 724 | #clock-cells = <0>; | |
| 7868c5eb | 725 | compatible = "allwinner,sun5i-a13-mbus-clk"; |
| 118c07ae EL |
726 | reg = <0x01c2015c 0x4>; |
| 727 | clocks = <&osc24M>, <&pll6 2>, <&pll5 1>; | |
| 728 | clock-output-names = "mbus"; | |
| 729 | }; | |
| 0aff0370 | 730 | |
| daed5a81 | 731 | /* |
| d8cacaa3 MR |
732 | * The following two are dummy clocks, placeholders |
| 733 | * used in the gmac_tx clock. The gmac driver will | |
| 734 | * choose one parent depending on the PHY interface | |
| 735 | * mode, using clk_set_rate auto-reparenting. | |
| 736 | * | |
| 737 | * The actual TX clock rate is not controlled by the | |
| 738 | * gmac_tx clock. | |
| daed5a81 CYT |
739 | */ |
| 740 | mii_phy_tx_clk: clk@2 { | |
| 741 | #clock-cells = <0>; | |
| 742 | compatible = "fixed-clock"; | |
| 743 | clock-frequency = <25000000>; | |
| 744 | clock-output-names = "mii_phy_tx"; | |
| 745 | }; | |
| 746 | ||
| 747 | gmac_int_tx_clk: clk@3 { | |
| 748 | #clock-cells = <0>; | |
| 749 | compatible = "fixed-clock"; | |
| 750 | clock-frequency = <125000000>; | |
| 751 | clock-output-names = "gmac_int_tx"; | |
| 752 | }; | |
| 753 | ||
| 754 | gmac_tx_clk: clk@01c20164 { | |
| 755 | #clock-cells = <0>; | |
| 756 | compatible = "allwinner,sun7i-a20-gmac-clk"; | |
| 757 | reg = <0x01c20164 0x4>; | |
| 758 | clocks = <&mii_phy_tx_clk>, <&gmac_int_tx_clk>; | |
| 759 | clock-output-names = "gmac_tx"; | |
| 760 | }; | |
| 761 | ||
| 0aff0370 CYT |
762 | /* |
| 763 | * Dummy clock used by output clocks | |
| 764 | */ | |
| 765 | osc24M_32k: clk@1 { | |
| 766 | #clock-cells = <0>; | |
| 767 | compatible = "fixed-factor-clock"; | |
| 768 | clock-div = <750>; | |
| 769 | clock-mult = <1>; | |
| 770 | clocks = <&osc24M>; | |
| 771 | clock-output-names = "osc24M_32k"; | |
| 772 | }; | |
| 773 | ||
| 774 | clk_out_a: clk@01c201f0 { | |
| 775 | #clock-cells = <0>; | |
| 776 | compatible = "allwinner,sun7i-a20-out-clk"; | |
| 777 | reg = <0x01c201f0 0x4>; | |
| 778 | clocks = <&osc24M_32k>, <&osc32k>, <&osc24M>; | |
| 779 | clock-output-names = "clk_out_a"; | |
| 780 | }; | |
| 781 | ||
| 782 | clk_out_b: clk@01c201f4 { | |
| 783 | #clock-cells = <0>; | |
| 784 | compatible = "allwinner,sun7i-a20-out-clk"; | |
| 785 | reg = <0x01c201f4 0x4>; | |
| 786 | clocks = <&osc24M_32k>, <&osc32k>, <&osc24M>; | |
| 787 | clock-output-names = "clk_out_b"; | |
| 788 | }; | |
| 4790ecfa MR |
789 | }; |
| 790 | ||
| 791 | soc@01c00000 { | |
| 792 | compatible = "simple-bus"; | |
| 793 | #address-cells = <1>; | |
| 794 | #size-cells = <1>; | |
| 795 | ranges; | |
| 796 | ||
| 0eb14a8d MR |
797 | sram-controller@01c00000 { |
| 798 | compatible = "allwinner,sun4i-a10-sram-controller"; | |
| 799 | reg = <0x01c00000 0x30>; | |
| 800 | #address-cells = <1>; | |
| 801 | #size-cells = <1>; | |
| 802 | ranges; | |
| 803 | ||
| 804 | sram_a: sram@00000000 { | |
| 805 | compatible = "mmio-sram"; | |
| 806 | reg = <0x00000000 0xc000>; | |
| 807 | #address-cells = <1>; | |
| 808 | #size-cells = <1>; | |
| 809 | ranges = <0 0x00000000 0xc000>; | |
| 810 | ||
| 811 | emac_sram: sram-section@8000 { | |
| 812 | compatible = "allwinner,sun4i-a10-sram-a3-a4"; | |
| 813 | reg = <0x8000 0x4000>; | |
| 814 | status = "disabled"; | |
| 815 | }; | |
| 816 | }; | |
| 817 | ||
| 818 | sram_d: sram@00010000 { | |
| 819 | compatible = "mmio-sram"; | |
| 820 | reg = <0x00010000 0x1000>; | |
| 821 | #address-cells = <1>; | |
| 822 | #size-cells = <1>; | |
| 823 | ranges = <0 0x00010000 0x1000>; | |
| 824 | ||
| 825 | otg_sram: sram-section@0000 { | |
| 826 | compatible = "allwinner,sun4i-a10-sram-d"; | |
| 827 | reg = <0x0000 0x1000>; | |
| 828 | status = "disabled"; | |
| 829 | }; | |
| 830 | }; | |
| 831 | }; | |
| 832 | ||
| 8ff973a2 CC |
833 | nmi_intc: interrupt-controller@01c00030 { |
| 834 | compatible = "allwinner,sun7i-a20-sc-nmi"; | |
| 835 | interrupt-controller; | |
| 836 | #interrupt-cells = <2>; | |
| 837 | reg = <0x01c00030 0x0c>; | |
| 19882b84 | 838 | interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>; |
| 8ff973a2 CC |
839 | }; |
| 840 | ||
| 316e0b0e EL |
841 | dma: dma-controller@01c02000 { |
| 842 | compatible = "allwinner,sun4i-a10-dma"; | |
| 843 | reg = <0x01c02000 0x1000>; | |
| 19882b84 | 844 | interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>; |
| 316e0b0e EL |
845 | clocks = <&ahb_gates 6>; |
| 846 | #dma-cells = <2>; | |
| 847 | }; | |
| 848 | ||
| b2a83ad2 BB |
849 | nfc: nand@01c03000 { |
| 850 | compatible = "allwinner,sun4i-a10-nand"; | |
| 851 | reg = <0x01c03000 0x1000>; | |
| 852 | interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>; | |
| 853 | clocks = <&ahb_gates 13>, <&nand_clk>; | |
| 854 | clock-names = "ahb", "mod"; | |
| 855 | dmas = <&dma SUN4I_DMA_DEDICATED 3>; | |
| 856 | dma-names = "rxtx"; | |
| 857 | status = "disabled"; | |
| 858 | #address-cells = <1>; | |
| 859 | #size-cells = <0>; | |
| 860 | }; | |
| 861 | ||
| 36ab3e73 MR |
862 | spi0: spi@01c05000 { |
| 863 | compatible = "allwinner,sun4i-a10-spi"; | |
| 864 | reg = <0x01c05000 0x1000>; | |
| 19882b84 | 865 | interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>; |
| 36ab3e73 MR |
866 | clocks = <&ahb_gates 20>, <&spi0_clk>; |
| 867 | clock-names = "ahb", "mod"; | |
| 1f9f6a78 MR |
868 | dmas = <&dma SUN4I_DMA_DEDICATED 27>, |
| 869 | <&dma SUN4I_DMA_DEDICATED 26>; | |
| ffec7210 | 870 | dma-names = "rx", "tx"; |
| 36ab3e73 MR |
871 | status = "disabled"; |
| 872 | #address-cells = <1>; | |
| 873 | #size-cells = <0>; | |
| 874 | }; | |
| 875 | ||
| 876 | spi1: spi@01c06000 { | |
| 877 | compatible = "allwinner,sun4i-a10-spi"; | |
| 878 | reg = <0x01c06000 0x1000>; | |
| 19882b84 | 879 | interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>; |
| 36ab3e73 MR |
880 | clocks = <&ahb_gates 21>, <&spi1_clk>; |
| 881 | clock-names = "ahb", "mod"; | |
| 1f9f6a78 MR |
882 | dmas = <&dma SUN4I_DMA_DEDICATED 9>, |
| 883 | <&dma SUN4I_DMA_DEDICATED 8>; | |
| ffec7210 | 884 | dma-names = "rx", "tx"; |
| 36ab3e73 MR |
885 | status = "disabled"; |
| 886 | #address-cells = <1>; | |
| 887 | #size-cells = <0>; | |
| 888 | }; | |
| 889 | ||
| 2e804d03 | 890 | emac: ethernet@01c0b000 { |
| 1c70e099 | 891 | compatible = "allwinner,sun4i-a10-emac"; |
| 2e804d03 | 892 | reg = <0x01c0b000 0x1000>; |
| 19882b84 | 893 | interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>; |
| 2e804d03 | 894 | clocks = <&ahb_gates 17>; |
| 0eb14a8d | 895 | allwinner,sram = <&emac_sram 1>; |
| 2e804d03 MR |
896 | status = "disabled"; |
| 897 | }; | |
| 898 | ||
| 92395f56 | 899 | mdio: mdio@01c0b080 { |
| 1c70e099 | 900 | compatible = "allwinner,sun4i-a10-mdio"; |
| 2e804d03 MR |
901 | reg = <0x01c0b080 0x14>; |
| 902 | status = "disabled"; | |
| 903 | #address-cells = <1>; | |
| 904 | #size-cells = <0>; | |
| 905 | }; | |
| 906 | ||
| dd29ce53 | 907 | mmc0: mmc@01c0f000 { |
| 57af711d | 908 | compatible = "allwinner,sun7i-a20-mmc"; |
| dd29ce53 | 909 | reg = <0x01c0f000 0x1000>; |
| d8c3a392 MR |
910 | clocks = <&ahb_gates 8>, |
| 911 | <&mmc0_clk 0>, | |
| 912 | <&mmc0_clk 1>, | |
| 913 | <&mmc0_clk 2>; | |
| 914 | clock-names = "ahb", | |
| 915 | "mmc", | |
| 916 | "output", | |
| 917 | "sample"; | |
| 19882b84 | 918 | interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>; |
| dd29ce53 | 919 | status = "disabled"; |
| 4c1bb9c3 HG |
920 | #address-cells = <1>; |
| 921 | #size-cells = <0>; | |
| dd29ce53 HG |
922 | }; |
| 923 | ||
| 924 | mmc1: mmc@01c10000 { | |
| 57af711d | 925 | compatible = "allwinner,sun7i-a20-mmc"; |
| dd29ce53 | 926 | reg = <0x01c10000 0x1000>; |
| d8c3a392 MR |
927 | clocks = <&ahb_gates 9>, |
| 928 | <&mmc1_clk 0>, | |
| 929 | <&mmc1_clk 1>, | |
| 930 | <&mmc1_clk 2>; | |
| 931 | clock-names = "ahb", | |
| 932 | "mmc", | |
| 933 | "output", | |
| 934 | "sample"; | |
| 19882b84 | 935 | interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>; |
| dd29ce53 | 936 | status = "disabled"; |
| 4c1bb9c3 HG |
937 | #address-cells = <1>; |
| 938 | #size-cells = <0>; | |
| dd29ce53 HG |
939 | }; |
| 940 | ||
| 941 | mmc2: mmc@01c11000 { | |
| 57af711d | 942 | compatible = "allwinner,sun7i-a20-mmc"; |
| dd29ce53 | 943 | reg = <0x01c11000 0x1000>; |
| d8c3a392 MR |
944 | clocks = <&ahb_gates 10>, |
| 945 | <&mmc2_clk 0>, | |
| 946 | <&mmc2_clk 1>, | |
| 947 | <&mmc2_clk 2>; | |
| 948 | clock-names = "ahb", | |
| 949 | "mmc", | |
| 950 | "output", | |
| 951 | "sample"; | |
| 19882b84 | 952 | interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>; |
| dd29ce53 | 953 | status = "disabled"; |
| 4c1bb9c3 HG |
954 | #address-cells = <1>; |
| 955 | #size-cells = <0>; | |
| dd29ce53 HG |
956 | }; |
| 957 | ||
| 958 | mmc3: mmc@01c12000 { | |
| 57af711d | 959 | compatible = "allwinner,sun7i-a20-mmc"; |
| dd29ce53 | 960 | reg = <0x01c12000 0x1000>; |
| d8c3a392 MR |
961 | clocks = <&ahb_gates 11>, |
| 962 | <&mmc3_clk 0>, | |
| 963 | <&mmc3_clk 1>, | |
| 964 | <&mmc3_clk 2>; | |
| 965 | clock-names = "ahb", | |
| 966 | "mmc", | |
| 967 | "output", | |
| 968 | "sample"; | |
| 19882b84 | 969 | interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>; |
| dd29ce53 | 970 | status = "disabled"; |
| 4c1bb9c3 HG |
971 | #address-cells = <1>; |
| 972 | #size-cells = <0>; | |
| dd29ce53 HG |
973 | }; |
| 974 | ||
| cbb3ff1d RB |
975 | usb_otg: usb@01c13000 { |
| 976 | compatible = "allwinner,sun4i-a10-musb"; | |
| 977 | reg = <0x01c13000 0x0400>; | |
| 978 | clocks = <&ahb_gates 0>; | |
| 979 | interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>; | |
| 980 | interrupt-names = "mc"; | |
| 981 | phys = <&usbphy 0>; | |
| 982 | phy-names = "usb"; | |
| 983 | extcon = <&usbphy 0>; | |
| 984 | allwinner,sram = <&otg_sram 1>; | |
| 985 | status = "disabled"; | |
| 986 | }; | |
| 987 | ||
| 9debd0a2 RB |
988 | usbphy: phy@01c13400 { |
| 989 | #phy-cells = <1>; | |
| 990 | compatible = "allwinner,sun7i-a20-usb-phy"; | |
| 991 | reg = <0x01c13400 0x10 0x01c14800 0x4 0x01c1c800 0x4>; | |
| 992 | reg-names = "phy_ctrl", "pmu1", "pmu2"; | |
| 993 | clocks = <&usb_clk 8>; | |
| 994 | clock-names = "usb_phy"; | |
| 134c60ad RB |
995 | resets = <&usb_clk 0>, <&usb_clk 1>, <&usb_clk 2>; |
| 996 | reset-names = "usb0_reset", "usb1_reset", "usb2_reset"; | |
| 9debd0a2 RB |
997 | status = "disabled"; |
| 998 | }; | |
| 999 | ||
| 1000 | ehci0: usb@01c14000 { | |
| 1001 | compatible = "allwinner,sun7i-a20-ehci", "generic-ehci"; | |
| 1002 | reg = <0x01c14000 0x100>; | |
| 19882b84 | 1003 | interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>; |
| 9debd0a2 RB |
1004 | clocks = <&ahb_gates 1>; |
| 1005 | phys = <&usbphy 1>; | |
| 1006 | phy-names = "usb"; | |
| 1007 | status = "disabled"; | |
| 1008 | }; | |
| 1009 | ||
| 1010 | ohci0: usb@01c14400 { | |
| 1011 | compatible = "allwinner,sun7i-a20-ohci", "generic-ohci"; | |
| 1012 | reg = <0x01c14400 0x100>; | |
| 19882b84 | 1013 | interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>; |
| 9debd0a2 RB |
1014 | clocks = <&usb_clk 6>, <&ahb_gates 2>; |
| 1015 | phys = <&usbphy 1>; | |
| 1016 | phy-names = "usb"; | |
| 1017 | status = "disabled"; | |
| 1018 | }; | |
| 1019 | ||
| 110d4e25 LC |
1020 | crypto: crypto-engine@01c15000 { |
| 1021 | compatible = "allwinner,sun4i-a10-crypto"; | |
| 1022 | reg = <0x01c15000 0x1000>; | |
| 1023 | interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>; | |
| 1024 | clocks = <&ahb_gates 5>, <&ss_clk>; | |
| 1025 | clock-names = "ahb", "mod"; | |
| 1026 | }; | |
| 1027 | ||
| 36ab3e73 MR |
1028 | spi2: spi@01c17000 { |
| 1029 | compatible = "allwinner,sun4i-a10-spi"; | |
| 1030 | reg = <0x01c17000 0x1000>; | |
| 19882b84 | 1031 | interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>; |
| 36ab3e73 MR |
1032 | clocks = <&ahb_gates 22>, <&spi2_clk>; |
| 1033 | clock-names = "ahb", "mod"; | |
| 1f9f6a78 MR |
1034 | dmas = <&dma SUN4I_DMA_DEDICATED 29>, |
| 1035 | <&dma SUN4I_DMA_DEDICATED 28>; | |
| ffec7210 | 1036 | dma-names = "rx", "tx"; |
| 36ab3e73 MR |
1037 | status = "disabled"; |
| 1038 | #address-cells = <1>; | |
| 1039 | #size-cells = <0>; | |
| 1040 | }; | |
| 1041 | ||
| 902febf9 HG |
1042 | ahci: sata@01c18000 { |
| 1043 | compatible = "allwinner,sun4i-a10-ahci"; | |
| 1044 | reg = <0x01c18000 0x1000>; | |
| 19882b84 | 1045 | interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>; |
| 902febf9 HG |
1046 | clocks = <&pll6 0>, <&ahb_gates 25>; |
| 1047 | status = "disabled"; | |
| 1048 | }; | |
| 1049 | ||
| 9debd0a2 RB |
1050 | ehci1: usb@01c1c000 { |
| 1051 | compatible = "allwinner,sun7i-a20-ehci", "generic-ehci"; | |
| 1052 | reg = <0x01c1c000 0x100>; | |
| 19882b84 | 1053 | interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>; |
| 9debd0a2 RB |
1054 | clocks = <&ahb_gates 3>; |
| 1055 | phys = <&usbphy 2>; | |
| 1056 | phy-names = "usb"; | |
| 1057 | status = "disabled"; | |
| 1058 | }; | |
| 1059 | ||
| 1060 | ohci1: usb@01c1c400 { | |
| 1061 | compatible = "allwinner,sun7i-a20-ohci", "generic-ohci"; | |
| 1062 | reg = <0x01c1c400 0x100>; | |
| 19882b84 | 1063 | interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>; |
| 9debd0a2 RB |
1064 | clocks = <&usb_clk 7>, <&ahb_gates 4>; |
| 1065 | phys = <&usbphy 2>; | |
| 1066 | phy-names = "usb"; | |
| 1067 | status = "disabled"; | |
| 1068 | }; | |
| 1069 | ||
| 36ab3e73 MR |
1070 | spi3: spi@01c1f000 { |
| 1071 | compatible = "allwinner,sun4i-a10-spi"; | |
| 1072 | reg = <0x01c1f000 0x1000>; | |
| 19882b84 | 1073 | interrupts = <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>; |
| 36ab3e73 MR |
1074 | clocks = <&ahb_gates 23>, <&spi3_clk>; |
| 1075 | clock-names = "ahb", "mod"; | |
| 1f9f6a78 MR |
1076 | dmas = <&dma SUN4I_DMA_DEDICATED 31>, |
| 1077 | <&dma SUN4I_DMA_DEDICATED 30>; | |
| ffec7210 | 1078 | dma-names = "rx", "tx"; |
| 36ab3e73 | 1079 | status = "disabled"; |
| 2e804d03 MR |
1080 | #address-cells = <1>; |
| 1081 | #size-cells = <0>; | |
| 1082 | }; | |
| 1083 | ||
| 17eac031 MR |
1084 | pio: pinctrl@01c20800 { |
| 1085 | compatible = "allwinner,sun7i-a20-pinctrl"; | |
| 1086 | reg = <0x01c20800 0x400>; | |
| 19882b84 | 1087 | interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>; |
| de7dc935 | 1088 | clocks = <&apb0_gates 5>; |
| 17eac031 MR |
1089 | gpio-controller; |
| 1090 | interrupt-controller; | |
| b03e0816 | 1091 | #interrupt-cells = <3>; |
| 17eac031 | 1092 | #gpio-cells = <3>; |
| 9f229ba9 | 1093 | |
| d130f2e7 AM |
1094 | clk_out_a_pins_a: clk_out_a@0 { |
| 1095 | allwinner,pins = "PI12"; | |
| 1096 | allwinner,function = "clk_out_a"; | |
| 092a0c3b MR |
1097 | allwinner,drive = <SUN4I_PINCTRL_10_MA>; |
| 1098 | allwinner,pull = <SUN4I_PINCTRL_NO_PULL>; | |
| fd7898a2 AB |
1099 | }; |
| 1100 | ||
| d130f2e7 AM |
1101 | clk_out_b_pins_a: clk_out_b@0 { |
| 1102 | allwinner,pins = "PI13"; | |
| 1103 | allwinner,function = "clk_out_b"; | |
| 092a0c3b MR |
1104 | allwinner,drive = <SUN4I_PINCTRL_10_MA>; |
| 1105 | allwinner,pull = <SUN4I_PINCTRL_NO_PULL>; | |
| fd7898a2 AB |
1106 | }; |
| 1107 | ||
| d130f2e7 AM |
1108 | emac_pins_a: emac0@0 { |
| 1109 | allwinner,pins = "PA0", "PA1", "PA2", | |
| 1110 | "PA3", "PA4", "PA5", "PA6", | |
| 1111 | "PA7", "PA8", "PA9", "PA10", | |
| 1112 | "PA11", "PA12", "PA13", "PA14", | |
| 1113 | "PA15", "PA16"; | |
| 1114 | allwinner,function = "emac"; | |
| 092a0c3b MR |
1115 | allwinner,drive = <SUN4I_PINCTRL_10_MA>; |
| 1116 | allwinner,pull = <SUN4I_PINCTRL_NO_PULL>; | |
| 9f229ba9 MR |
1117 | }; |
| 1118 | ||
| d130f2e7 AM |
1119 | gmac_pins_mii_a: gmac_mii@0 { |
| 1120 | allwinner,pins = "PA0", "PA1", "PA2", | |
| 1121 | "PA3", "PA4", "PA5", "PA6", | |
| 1122 | "PA7", "PA8", "PA9", "PA10", | |
| 1123 | "PA11", "PA12", "PA13", "PA14", | |
| 1124 | "PA15", "PA16"; | |
| 1125 | allwinner,function = "gmac"; | |
| 092a0c3b MR |
1126 | allwinner,drive = <SUN4I_PINCTRL_10_MA>; |
| 1127 | allwinner,pull = <SUN4I_PINCTRL_NO_PULL>; | |
| 4261ec43 CYT |
1128 | }; |
| 1129 | ||
| d130f2e7 AM |
1130 | gmac_pins_rgmii_a: gmac_rgmii@0 { |
| 1131 | allwinner,pins = "PA0", "PA1", "PA2", | |
| 1132 | "PA3", "PA4", "PA5", "PA6", | |
| 1133 | "PA7", "PA8", "PA10", | |
| 1134 | "PA11", "PA12", "PA13", | |
| 1135 | "PA15", "PA16"; | |
| 1136 | allwinner,function = "gmac"; | |
| 1137 | /* | |
| 1138 | * data lines in RGMII mode use DDR mode | |
| 1139 | * and need a higher signal drive strength | |
| 1140 | */ | |
| 1141 | allwinner,drive = <SUN4I_PINCTRL_40_MA>; | |
| 092a0c3b | 1142 | allwinner,pull = <SUN4I_PINCTRL_NO_PULL>; |
| 7b5bace3 WW |
1143 | }; |
| 1144 | ||
| d130f2e7 AM |
1145 | i2c0_pins_a: i2c0@0 { |
| 1146 | allwinner,pins = "PB0", "PB1"; | |
| 1147 | allwinner,function = "i2c0"; | |
| 092a0c3b MR |
1148 | allwinner,drive = <SUN4I_PINCTRL_10_MA>; |
| 1149 | allwinner,pull = <SUN4I_PINCTRL_NO_PULL>; | |
| 0510e4b5 HG |
1150 | }; |
| 1151 | ||
| d130f2e7 AM |
1152 | i2c1_pins_a: i2c1@0 { |
| 1153 | allwinner,pins = "PB18", "PB19"; | |
| 1154 | allwinner,function = "i2c1"; | |
| 092a0c3b MR |
1155 | allwinner,drive = <SUN4I_PINCTRL_10_MA>; |
| 1156 | allwinner,pull = <SUN4I_PINCTRL_NO_PULL>; | |
| 7b5bace3 WW |
1157 | }; |
| 1158 | ||
| d130f2e7 AM |
1159 | i2c2_pins_a: i2c2@0 { |
| 1160 | allwinner,pins = "PB20", "PB21"; | |
| 1161 | allwinner,function = "i2c2"; | |
| 869afa7f MR |
1162 | allwinner,drive = <SUN4I_PINCTRL_10_MA>; |
| 1163 | allwinner,pull = <SUN4I_PINCTRL_NO_PULL>; | |
| 1164 | }; | |
| 1165 | ||
| d130f2e7 AM |
1166 | i2c3_pins_a: i2c3@0 { |
| 1167 | allwinner,pins = "PI0", "PI1"; | |
| 1168 | allwinner,function = "i2c3"; | |
| 092a0c3b MR |
1169 | allwinner,drive = <SUN4I_PINCTRL_10_MA>; |
| 1170 | allwinner,pull = <SUN4I_PINCTRL_NO_PULL>; | |
| 7b5bace3 WW |
1171 | }; |
| 1172 | ||
| d130f2e7 AM |
1173 | ir0_rx_pins_a: ir0@0 { |
| 1174 | allwinner,pins = "PB4"; | |
| 1175 | allwinner,function = "ir0"; | |
| 1176 | allwinner,drive = <SUN4I_PINCTRL_10_MA>; | |
| 1177 | allwinner,pull = <SUN4I_PINCTRL_NO_PULL>; | |
| 9f229ba9 MR |
1178 | }; |
| 1179 | ||
| d130f2e7 AM |
1180 | ir0_tx_pins_a: ir0@1 { |
| 1181 | allwinner,pins = "PB3"; | |
| 1182 | allwinner,function = "ir0"; | |
| 1183 | allwinner,drive = <SUN4I_PINCTRL_10_MA>; | |
| 1184 | allwinner,pull = <SUN4I_PINCTRL_NO_PULL>; | |
| 9f229ba9 | 1185 | }; |
| 756084c5 | 1186 | |
| d130f2e7 AM |
1187 | ir1_rx_pins_a: ir1@0 { |
| 1188 | allwinner,pins = "PB23"; | |
| 1189 | allwinner,function = "ir1"; | |
| 1190 | allwinner,drive = <SUN4I_PINCTRL_10_MA>; | |
| 1191 | allwinner,pull = <SUN4I_PINCTRL_NO_PULL>; | |
| e5496a31 MR |
1192 | }; |
| 1193 | ||
| d130f2e7 AM |
1194 | ir1_tx_pins_a: ir1@1 { |
| 1195 | allwinner,pins = "PB22"; | |
| 1196 | allwinner,function = "ir1"; | |
| 1197 | allwinner,drive = <SUN4I_PINCTRL_10_MA>; | |
| 1198 | allwinner,pull = <SUN4I_PINCTRL_NO_PULL>; | |
| e5496a31 MR |
1199 | }; |
| 1200 | ||
| d130f2e7 AM |
1201 | mmc0_pins_a: mmc0@0 { |
| 1202 | allwinner,pins = "PF0", "PF1", "PF2", | |
| 1203 | "PF3", "PF4", "PF5"; | |
| 1204 | allwinner,function = "mmc0"; | |
| 1205 | allwinner,drive = <SUN4I_PINCTRL_30_MA>; | |
| 092a0c3b | 1206 | allwinner,pull = <SUN4I_PINCTRL_NO_PULL>; |
| e5496a31 MR |
1207 | }; |
| 1208 | ||
| d130f2e7 AM |
1209 | mmc0_cd_pin_reference_design: mmc0_cd_pin@0 { |
| 1210 | allwinner,pins = "PH1"; | |
| 1211 | allwinner,function = "gpio_in"; | |
| 092a0c3b | 1212 | allwinner,drive = <SUN4I_PINCTRL_10_MA>; |
| d130f2e7 AM |
1213 | allwinner,pull = <SUN4I_PINCTRL_PULL_UP>; |
| 1214 | }; | |
| 1215 | ||
| 1216 | mmc2_pins_a: mmc2@0 { | |
| 1217 | allwinner,pins = "PC6", "PC7", "PC8", | |
| 1218 | "PC9", "PC10", "PC11"; | |
| 1219 | allwinner,function = "mmc2"; | |
| 1220 | allwinner,drive = <SUN4I_PINCTRL_30_MA>; | |
| 1221 | allwinner,pull = <SUN4I_PINCTRL_PULL_UP>; | |
| 1222 | }; | |
| 1223 | ||
| 1224 | mmc3_pins_a: mmc3@0 { | |
| 1225 | allwinner,pins = "PI4", "PI5", "PI6", | |
| 1226 | "PI7", "PI8", "PI9"; | |
| 1227 | allwinner,function = "mmc3"; | |
| 1228 | allwinner,drive = <SUN4I_PINCTRL_30_MA>; | |
| 092a0c3b | 1229 | allwinner,pull = <SUN4I_PINCTRL_NO_PULL>; |
| 7b5bace3 WW |
1230 | }; |
| 1231 | ||
| d130f2e7 AM |
1232 | ps20_pins_a: ps20@0 { |
| 1233 | allwinner,pins = "PI20", "PI21"; | |
| 1234 | allwinner,function = "ps2"; | |
| 092a0c3b MR |
1235 | allwinner,drive = <SUN4I_PINCTRL_10_MA>; |
| 1236 | allwinner,pull = <SUN4I_PINCTRL_NO_PULL>; | |
| 756084c5 | 1237 | }; |
| f2e0759e | 1238 | |
| d130f2e7 AM |
1239 | ps21_pins_a: ps21@0 { |
| 1240 | allwinner,pins = "PH12", "PH13"; | |
| 1241 | allwinner,function = "ps2"; | |
| 092a0c3b MR |
1242 | allwinner,drive = <SUN4I_PINCTRL_10_MA>; |
| 1243 | allwinner,pull = <SUN4I_PINCTRL_NO_PULL>; | |
| f2e0759e CYT |
1244 | }; |
| 1245 | ||
| d130f2e7 AM |
1246 | pwm0_pins_a: pwm0@0 { |
| 1247 | allwinner,pins = "PB2"; | |
| 1248 | allwinner,function = "pwm"; | |
| 092a0c3b MR |
1249 | allwinner,drive = <SUN4I_PINCTRL_10_MA>; |
| 1250 | allwinner,pull = <SUN4I_PINCTRL_NO_PULL>; | |
| f2e0759e | 1251 | }; |
| 129ccbcd | 1252 | |
| d130f2e7 AM |
1253 | pwm1_pins_a: pwm1@0 { |
| 1254 | allwinner,pins = "PI3"; | |
| 1255 | allwinner,function = "pwm"; | |
| 092a0c3b MR |
1256 | allwinner,drive = <SUN4I_PINCTRL_10_MA>; |
| 1257 | allwinner,pull = <SUN4I_PINCTRL_NO_PULL>; | |
| 129ccbcd CYT |
1258 | }; |
| 1259 | ||
| d130f2e7 AM |
1260 | spdif_tx_pins_a: spdif@0 { |
| 1261 | allwinner,pins = "PB13"; | |
| 1262 | allwinner,function = "spdif"; | |
| 1263 | allwinner,drive = <SUN4I_PINCTRL_10_MA>; | |
| 1264 | allwinner,pull = <SUN4I_PINCTRL_PULL_UP>; | |
| 129ccbcd | 1265 | }; |
| 412f2c6f | 1266 | |
| 2dad53b5 | 1267 | spi0_pins_a: spi0@0 { |
| f3022c6c MR |
1268 | allwinner,pins = "PI11", "PI12", "PI13"; |
| 1269 | allwinner,function = "spi0"; | |
| 1270 | allwinner,drive = <SUN4I_PINCTRL_10_MA>; | |
| 1271 | allwinner,pull = <SUN4I_PINCTRL_NO_PULL>; | |
| 1272 | }; | |
| 1273 | ||
| 1274 | spi0_cs0_pins_a: spi0_cs0@0 { | |
| 1275 | allwinner,pins = "PI10"; | |
| 1276 | allwinner,function = "spi0"; | |
| 1277 | allwinner,drive = <SUN4I_PINCTRL_10_MA>; | |
| 1278 | allwinner,pull = <SUN4I_PINCTRL_NO_PULL>; | |
| 1279 | }; | |
| 1280 | ||
| 1281 | spi0_cs1_pins_a: spi0_cs1@0 { | |
| 1282 | allwinner,pins = "PI14"; | |
| 2dad53b5 | 1283 | allwinner,function = "spi0"; |
| 092a0c3b MR |
1284 | allwinner,drive = <SUN4I_PINCTRL_10_MA>; |
| 1285 | allwinner,pull = <SUN4I_PINCTRL_NO_PULL>; | |
| 2dad53b5 HG |
1286 | }; |
| 1287 | ||
| 412f2c6f | 1288 | spi1_pins_a: spi1@0 { |
| f3022c6c MR |
1289 | allwinner,pins = "PI17", "PI18", "PI19"; |
| 1290 | allwinner,function = "spi1"; | |
| 1291 | allwinner,drive = <SUN4I_PINCTRL_10_MA>; | |
| 1292 | allwinner,pull = <SUN4I_PINCTRL_NO_PULL>; | |
| 1293 | }; | |
| 1294 | ||
| 1295 | spi1_cs0_pins_a: spi1_cs0@0 { | |
| 1296 | allwinner,pins = "PI16"; | |
| 412f2c6f | 1297 | allwinner,function = "spi1"; |
| 092a0c3b MR |
1298 | allwinner,drive = <SUN4I_PINCTRL_10_MA>; |
| 1299 | allwinner,pull = <SUN4I_PINCTRL_NO_PULL>; | |
| 412f2c6f MR |
1300 | }; |
| 1301 | ||
| 1302 | spi2_pins_a: spi2@0 { | |
| f3022c6c | 1303 | allwinner,pins = "PC20", "PC21", "PC22"; |
| 412f2c6f | 1304 | allwinner,function = "spi2"; |
| 092a0c3b MR |
1305 | allwinner,drive = <SUN4I_PINCTRL_10_MA>; |
| 1306 | allwinner,pull = <SUN4I_PINCTRL_NO_PULL>; | |
| 7b5bace3 WW |
1307 | }; |
| 1308 | ||
| 1309 | spi2_pins_b: spi2@1 { | |
| f3022c6c MR |
1310 | allwinner,pins = "PB15", "PB16", "PB17"; |
| 1311 | allwinner,function = "spi2"; | |
| 1312 | allwinner,drive = <SUN4I_PINCTRL_10_MA>; | |
| 1313 | allwinner,pull = <SUN4I_PINCTRL_NO_PULL>; | |
| 1314 | }; | |
| 1315 | ||
| 1316 | spi2_cs0_pins_a: spi2_cs0@0 { | |
| 1317 | allwinner,pins = "PC19"; | |
| 1318 | allwinner,function = "spi2"; | |
| 1319 | allwinner,drive = <SUN4I_PINCTRL_10_MA>; | |
| 1320 | allwinner,pull = <SUN4I_PINCTRL_NO_PULL>; | |
| 1321 | }; | |
| 1322 | ||
| 1323 | spi2_cs0_pins_b: spi2_cs0@1 { | |
| 1324 | allwinner,pins = "PB14"; | |
| 7b5bace3 | 1325 | allwinner,function = "spi2"; |
| 092a0c3b MR |
1326 | allwinner,drive = <SUN4I_PINCTRL_10_MA>; |
| 1327 | allwinner,pull = <SUN4I_PINCTRL_NO_PULL>; | |
| 412f2c6f | 1328 | }; |
| 11fbedf4 | 1329 | |
| d130f2e7 AM |
1330 | uart0_pins_a: uart0@0 { |
| 1331 | allwinner,pins = "PB22", "PB23"; | |
| 1332 | allwinner,function = "uart0"; | |
| 1333 | allwinner,drive = <SUN4I_PINCTRL_10_MA>; | |
| 092a0c3b | 1334 | allwinner,pull = <SUN4I_PINCTRL_NO_PULL>; |
| 11fbedf4 HG |
1335 | }; |
| 1336 | ||
| d130f2e7 AM |
1337 | uart2_pins_a: uart2@0 { |
| 1338 | allwinner,pins = "PI16", "PI17", "PI18", "PI19"; | |
| 1339 | allwinner,function = "uart2"; | |
| 092a0c3b | 1340 | allwinner,drive = <SUN4I_PINCTRL_10_MA>; |
| 092a0c3b | 1341 | allwinner,pull = <SUN4I_PINCTRL_NO_PULL>; |
| 11fbedf4 | 1342 | }; |
| 0fc2b7af | 1343 | |
| d130f2e7 AM |
1344 | uart3_pins_a: uart3@0 { |
| 1345 | allwinner,pins = "PG6", "PG7", "PG8", "PG9"; | |
| 1346 | allwinner,function = "uart3"; | |
| 1347 | allwinner,drive = <SUN4I_PINCTRL_10_MA>; | |
| 1348 | allwinner,pull = <SUN4I_PINCTRL_NO_PULL>; | |
| 0fc2b7af AB |
1349 | }; |
| 1350 | ||
| d130f2e7 AM |
1351 | uart3_pins_b: uart3@1 { |
| 1352 | allwinner,pins = "PH0", "PH1"; | |
| 1353 | allwinner,function = "uart3"; | |
| 1354 | allwinner,drive = <SUN4I_PINCTRL_10_MA>; | |
| 1355 | allwinner,pull = <SUN4I_PINCTRL_NO_PULL>; | |
| 469a22e6 MC |
1356 | }; |
| 1357 | ||
| d130f2e7 AM |
1358 | uart4_pins_a: uart4@0 { |
| 1359 | allwinner,pins = "PG10", "PG11"; | |
| 1360 | allwinner,function = "uart4"; | |
| 1361 | allwinner,drive = <SUN4I_PINCTRL_10_MA>; | |
| 1362 | allwinner,pull = <SUN4I_PINCTRL_NO_PULL>; | |
| 469a22e6 MC |
1363 | }; |
| 1364 | ||
| d130f2e7 AM |
1365 | uart4_pins_b: uart4@1 { |
| 1366 | allwinner,pins = "PH4", "PH5"; | |
| 1367 | allwinner,function = "uart4"; | |
| 1368 | allwinner,drive = <SUN4I_PINCTRL_10_MA>; | |
| 1369 | allwinner,pull = <SUN4I_PINCTRL_NO_PULL>; | |
| 0fc2b7af | 1370 | }; |
| 1e8d1567 | 1371 | |
| d130f2e7 AM |
1372 | uart5_pins_a: uart5@0 { |
| 1373 | allwinner,pins = "PI10", "PI11"; | |
| 1374 | allwinner,function = "uart5"; | |
| 1e8d1567 VP |
1375 | allwinner,drive = <SUN4I_PINCTRL_10_MA>; |
| 1376 | allwinner,pull = <SUN4I_PINCTRL_NO_PULL>; | |
| 1377 | }; | |
| 1378 | ||
| d130f2e7 AM |
1379 | uart6_pins_a: uart6@0 { |
| 1380 | allwinner,pins = "PI12", "PI13"; | |
| 1381 | allwinner,function = "uart6"; | |
| 1e8d1567 VP |
1382 | allwinner,drive = <SUN4I_PINCTRL_10_MA>; |
| 1383 | allwinner,pull = <SUN4I_PINCTRL_NO_PULL>; | |
| 0fc2b7af | 1384 | }; |
| bdd08a84 | 1385 | |
| d130f2e7 AM |
1386 | uart7_pins_a: uart7@0 { |
| 1387 | allwinner,pins = "PI20", "PI21"; | |
| 1388 | allwinner,function = "uart7"; | |
| bdd08a84 | 1389 | allwinner,drive = <SUN4I_PINCTRL_10_MA>; |
| d130f2e7 | 1390 | allwinner,pull = <SUN4I_PINCTRL_NO_PULL>; |
| bdd08a84 | 1391 | }; |
| 17eac031 MR |
1392 | }; |
| 1393 | ||
| 4790ecfa | 1394 | timer@01c20c00 { |
| b4f26440 | 1395 | compatible = "allwinner,sun4i-a10-timer"; |
| 4790ecfa | 1396 | reg = <0x01c20c00 0x90>; |
| 19882b84 MR |
1397 | interrupts = <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>, |
| 1398 | <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>, | |
| 1399 | <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>, | |
| 1400 | <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>, | |
| 1401 | <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>, | |
| 1402 | <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>; | |
| 4790ecfa MR |
1403 | clocks = <&osc24M>; |
| 1404 | }; | |
| 1405 | ||
| 1406 | wdt: watchdog@01c20c90 { | |
| ca5d04d9 | 1407 | compatible = "allwinner,sun4i-a10-wdt"; |
| 4790ecfa MR |
1408 | reg = <0x01c20c90 0x10>; |
| 1409 | }; | |
| 1410 | ||
| b5d905c7 CC |
1411 | rtc: rtc@01c20d00 { |
| 1412 | compatible = "allwinner,sun7i-a20-rtc"; | |
| 1413 | reg = <0x01c20d00 0x20>; | |
| 19882b84 | 1414 | interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>; |
| b5d905c7 CC |
1415 | }; |
| 1416 | ||
| 8ec40c25 AB |
1417 | pwm: pwm@01c20e00 { |
| 1418 | compatible = "allwinner,sun7i-a20-pwm"; | |
| 1419 | reg = <0x01c20e00 0xc>; | |
| 1420 | clocks = <&osc24M>; | |
| 1421 | #pwm-cells = <3>; | |
| 1422 | status = "disabled"; | |
| 1423 | }; | |
| 1424 | ||
| a34d6ce5 MC |
1425 | spdif: spdif@01c21000 { |
| 1426 | #sound-dai-cells = <0>; | |
| 1427 | compatible = "allwinner,sun4i-a10-spdif"; | |
| 1428 | reg = <0x01c21000 0x400>; | |
| 1429 | interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>; | |
| 1430 | clocks = <&apb0_gates 1>, <&spdif_clk>; | |
| 1431 | clock-names = "apb", "spdif"; | |
| 1432 | dmas = <&dma SUN4I_DMA_NORMAL 2>, | |
| 1433 | <&dma SUN4I_DMA_NORMAL 2>; | |
| 1434 | dma-names = "rx", "tx"; | |
| 1435 | status = "disabled"; | |
| 1436 | }; | |
| 1437 | ||
| c1a0ee3d | 1438 | ir0: ir@01c21800 { |
| 1715a389 | 1439 | compatible = "allwinner,sun4i-a10-ir"; |
| c1a0ee3d AB |
1440 | clocks = <&apb0_gates 6>, <&ir0_clk>; |
| 1441 | clock-names = "apb", "ir"; | |
| 19882b84 | 1442 | interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>; |
| c1a0ee3d AB |
1443 | reg = <0x01c21800 0x40>; |
| 1444 | status = "disabled"; | |
| 1445 | }; | |
| 1446 | ||
| 1447 | ir1: ir@01c21c00 { | |
| 1715a389 | 1448 | compatible = "allwinner,sun4i-a10-ir"; |
| c1a0ee3d AB |
1449 | clocks = <&apb0_gates 7>, <&ir1_clk>; |
| 1450 | clock-names = "apb", "ir"; | |
| 19882b84 | 1451 | interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>; |
| c1a0ee3d AB |
1452 | reg = <0x01c21c00 0x40>; |
| 1453 | status = "disabled"; | |
| 1454 | }; | |
| 1455 | ||
| 6a706356 MR |
1456 | i2s1: i2s@01c22000 { |
| 1457 | #sound-dai-cells = <0>; | |
| 1458 | compatible = "allwinner,sun4i-a10-i2s"; | |
| 1459 | reg = <0x01c22000 0x400>; | |
| 1460 | interrupts = <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>; | |
| 1461 | clocks = <&apb0_gates 4>, <&i2s1_clk>; | |
| 1462 | clock-names = "apb", "mod"; | |
| 1463 | dmas = <&dma SUN4I_DMA_NORMAL 4>, | |
| 1464 | <&dma SUN4I_DMA_NORMAL 4>; | |
| 1465 | dma-names = "rx", "tx"; | |
| 1466 | status = "disabled"; | |
| 1467 | }; | |
| 1468 | ||
| 1469 | i2s0: i2s@01c22400 { | |
| 1470 | #sound-dai-cells = <0>; | |
| 1471 | compatible = "allwinner,sun4i-a10-i2s"; | |
| 1472 | reg = <0x01c22400 0x400>; | |
| 1473 | interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>; | |
| 1474 | clocks = <&apb0_gates 3>, <&i2s0_clk>; | |
| 1475 | clock-names = "apb", "mod"; | |
| 1476 | dmas = <&dma SUN4I_DMA_NORMAL 3>, | |
| 1477 | <&dma SUN4I_DMA_NORMAL 3>; | |
| 1478 | dma-names = "rx", "tx"; | |
| 1479 | status = "disabled"; | |
| 1480 | }; | |
| 1481 | ||
| a6a2d644 HG |
1482 | lradc: lradc@01c22800 { |
| 1483 | compatible = "allwinner,sun4i-a10-lradc-keys"; | |
| 1484 | reg = <0x01c22800 0x100>; | |
| 19882b84 | 1485 | interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>; |
| a6a2d644 HG |
1486 | status = "disabled"; |
| 1487 | }; | |
| 1488 | ||
| d5ce107a EL |
1489 | codec: codec@01c22c00 { |
| 1490 | #sound-dai-cells = <0>; | |
| 1491 | compatible = "allwinner,sun7i-a20-codec"; | |
| 1492 | reg = <0x01c22c00 0x40>; | |
| 1493 | interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>; | |
| 1494 | clocks = <&apb0_gates 0>, <&codec_clk>; | |
| 1495 | clock-names = "apb", "codec"; | |
| 1496 | dmas = <&dma SUN4I_DMA_NORMAL 19>, | |
| 1497 | <&dma SUN4I_DMA_NORMAL 19>; | |
| 1498 | dma-names = "rx", "tx"; | |
| 1499 | status = "disabled"; | |
| 1500 | }; | |
| 1501 | ||
| 2bad969f OS |
1502 | sid: eeprom@01c23800 { |
| 1503 | compatible = "allwinner,sun7i-a20-sid"; | |
| 1504 | reg = <0x01c23800 0x200>; | |
| 1505 | }; | |
| 1506 | ||
| 6a706356 MR |
1507 | i2s2: i2s@01c24400 { |
| 1508 | #sound-dai-cells = <0>; | |
| 1509 | compatible = "allwinner,sun4i-a10-i2s"; | |
| 1510 | reg = <0x01c24400 0x400>; | |
| 1511 | interrupts = <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>; | |
| 1512 | clocks = <&apb0_gates 8>, <&i2s2_clk>; | |
| 1513 | clock-names = "apb", "mod"; | |
| 1514 | dmas = <&dma SUN4I_DMA_NORMAL 6>, | |
| 1515 | <&dma SUN4I_DMA_NORMAL 6>; | |
| 1516 | dma-names = "rx", "tx"; | |
| 1517 | status = "disabled"; | |
| 1518 | }; | |
| 1519 | ||
| 00f7ed8d | 1520 | rtp: rtp@01c25000 { |
| 8bf1b9b3 | 1521 | compatible = "allwinner,sun5i-a13-ts"; |
| 00f7ed8d | 1522 | reg = <0x01c25000 0x100>; |
| 19882b84 | 1523 | interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>; |
| 41e7afb1 | 1524 | #thermal-sensor-cells = <0>; |
| 00f7ed8d HG |
1525 | }; |
| 1526 | ||
| 4790ecfa MR |
1527 | uart0: serial@01c28000 { |
| 1528 | compatible = "snps,dw-apb-uart"; | |
| 1529 | reg = <0x01c28000 0x400>; | |
| 19882b84 | 1530 | interrupts = <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>; |
| 4790ecfa MR |
1531 | reg-shift = <2>; |
| 1532 | reg-io-width = <4>; | |
| de7dc935 | 1533 | clocks = <&apb1_gates 16>; |
| 4790ecfa MR |
1534 | status = "disabled"; |
| 1535 | }; | |
| 1536 | ||
| 1537 | uart1: serial@01c28400 { | |
| 1538 | compatible = "snps,dw-apb-uart"; | |
| 1539 | reg = <0x01c28400 0x400>; | |
| 19882b84 | 1540 | interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>; |
| 4790ecfa MR |
1541 | reg-shift = <2>; |
| 1542 | reg-io-width = <4>; | |
| de7dc935 | 1543 | clocks = <&apb1_gates 17>; |
| 4790ecfa MR |
1544 | status = "disabled"; |
| 1545 | }; | |
| 1546 | ||
| 1547 | uart2: serial@01c28800 { | |
| 1548 | compatible = "snps,dw-apb-uart"; | |
| 1549 | reg = <0x01c28800 0x400>; | |
| 19882b84 | 1550 | interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>; |
| 4790ecfa MR |
1551 | reg-shift = <2>; |
| 1552 | reg-io-width = <4>; | |
| de7dc935 | 1553 | clocks = <&apb1_gates 18>; |
| 4790ecfa MR |
1554 | status = "disabled"; |
| 1555 | }; | |
| 1556 | ||
| 1557 | uart3: serial@01c28c00 { | |
| 1558 | compatible = "snps,dw-apb-uart"; | |
| 1559 | reg = <0x01c28c00 0x400>; | |
| 19882b84 | 1560 | interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>; |
| 4790ecfa MR |
1561 | reg-shift = <2>; |
| 1562 | reg-io-width = <4>; | |
| de7dc935 | 1563 | clocks = <&apb1_gates 19>; |
| 4790ecfa MR |
1564 | status = "disabled"; |
| 1565 | }; | |
| 1566 | ||
| 1567 | uart4: serial@01c29000 { | |
| 1568 | compatible = "snps,dw-apb-uart"; | |
| 1569 | reg = <0x01c29000 0x400>; | |
| 19882b84 | 1570 | interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>; |
| 4790ecfa MR |
1571 | reg-shift = <2>; |
| 1572 | reg-io-width = <4>; | |
| de7dc935 | 1573 | clocks = <&apb1_gates 20>; |
| 4790ecfa MR |
1574 | status = "disabled"; |
| 1575 | }; | |
| 1576 | ||
| 1577 | uart5: serial@01c29400 { | |
| 1578 | compatible = "snps,dw-apb-uart"; | |
| 1579 | reg = <0x01c29400 0x400>; | |
| 19882b84 | 1580 | interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>; |
| 4790ecfa MR |
1581 | reg-shift = <2>; |
| 1582 | reg-io-width = <4>; | |
| de7dc935 | 1583 | clocks = <&apb1_gates 21>; |
| 4790ecfa MR |
1584 | status = "disabled"; |
| 1585 | }; | |
| 1586 | ||
| 1587 | uart6: serial@01c29800 { | |
| 1588 | compatible = "snps,dw-apb-uart"; | |
| 1589 | reg = <0x01c29800 0x400>; | |
| 19882b84 | 1590 | interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>; |
| 4790ecfa MR |
1591 | reg-shift = <2>; |
| 1592 | reg-io-width = <4>; | |
| de7dc935 | 1593 | clocks = <&apb1_gates 22>; |
| 4790ecfa MR |
1594 | status = "disabled"; |
| 1595 | }; | |
| 1596 | ||
| 1597 | uart7: serial@01c29c00 { | |
| 1598 | compatible = "snps,dw-apb-uart"; | |
| 1599 | reg = <0x01c29c00 0x400>; | |
| 19882b84 | 1600 | interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>; |
| 4790ecfa MR |
1601 | reg-shift = <2>; |
| 1602 | reg-io-width = <4>; | |
| de7dc935 | 1603 | clocks = <&apb1_gates 23>; |
| 4790ecfa MR |
1604 | status = "disabled"; |
| 1605 | }; | |
| 1606 | ||
| 428abbb8 | 1607 | i2c0: i2c@01c2ac00 { |
| d8cacaa3 MR |
1608 | compatible = "allwinner,sun7i-a20-i2c", |
| 1609 | "allwinner,sun4i-a10-i2c"; | |
| 428abbb8 | 1610 | reg = <0x01c2ac00 0x400>; |
| 19882b84 | 1611 | interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>; |
| 428abbb8 | 1612 | clocks = <&apb1_gates 0>; |
| 428abbb8 | 1613 | status = "disabled"; |
| d1412aed HG |
1614 | #address-cells = <1>; |
| 1615 | #size-cells = <0>; | |
| 428abbb8 MR |
1616 | }; |
| 1617 | ||
| 1618 | i2c1: i2c@01c2b000 { | |
| d8cacaa3 MR |
1619 | compatible = "allwinner,sun7i-a20-i2c", |
| 1620 | "allwinner,sun4i-a10-i2c"; | |
| 428abbb8 | 1621 | reg = <0x01c2b000 0x400>; |
| 19882b84 | 1622 | interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>; |
| 428abbb8 | 1623 | clocks = <&apb1_gates 1>; |
| 428abbb8 | 1624 | status = "disabled"; |
| d1412aed HG |
1625 | #address-cells = <1>; |
| 1626 | #size-cells = <0>; | |
| 428abbb8 MR |
1627 | }; |
| 1628 | ||
| 1629 | i2c2: i2c@01c2b400 { | |
| d8cacaa3 MR |
1630 | compatible = "allwinner,sun7i-a20-i2c", |
| 1631 | "allwinner,sun4i-a10-i2c"; | |
| 428abbb8 | 1632 | reg = <0x01c2b400 0x400>; |
| 19882b84 | 1633 | interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>; |
| 428abbb8 | 1634 | clocks = <&apb1_gates 2>; |
| 428abbb8 | 1635 | status = "disabled"; |
| d1412aed HG |
1636 | #address-cells = <1>; |
| 1637 | #size-cells = <0>; | |
| 428abbb8 MR |
1638 | }; |
| 1639 | ||
| 1640 | i2c3: i2c@01c2b800 { | |
| d8cacaa3 MR |
1641 | compatible = "allwinner,sun7i-a20-i2c", |
| 1642 | "allwinner,sun4i-a10-i2c"; | |
| 428abbb8 | 1643 | reg = <0x01c2b800 0x400>; |
| 19882b84 | 1644 | interrupts = <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>; |
| 428abbb8 | 1645 | clocks = <&apb1_gates 3>; |
| 428abbb8 | 1646 | status = "disabled"; |
| d1412aed HG |
1647 | #address-cells = <1>; |
| 1648 | #size-cells = <0>; | |
| 428abbb8 MR |
1649 | }; |
| 1650 | ||
| a3867045 | 1651 | i2c4: i2c@01c2c000 { |
| d8cacaa3 MR |
1652 | compatible = "allwinner,sun7i-a20-i2c", |
| 1653 | "allwinner,sun4i-a10-i2c"; | |
| a3867045 | 1654 | reg = <0x01c2c000 0x400>; |
| 19882b84 | 1655 | interrupts = <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>; |
| 428abbb8 | 1656 | clocks = <&apb1_gates 15>; |
| 428abbb8 | 1657 | status = "disabled"; |
| d1412aed HG |
1658 | #address-cells = <1>; |
| 1659 | #size-cells = <0>; | |
| 428abbb8 MR |
1660 | }; |
| 1661 | ||
| c40b8d58 CYT |
1662 | gmac: ethernet@01c50000 { |
| 1663 | compatible = "allwinner,sun7i-a20-gmac"; | |
| 1664 | reg = <0x01c50000 0x10000>; | |
| 19882b84 | 1665 | interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>; |
| c40b8d58 CYT |
1666 | interrupt-names = "macirq"; |
| 1667 | clocks = <&ahb_gates 49>, <&gmac_tx_clk>; | |
| 1668 | clock-names = "stmmaceth", "allwinner_gmac_tx"; | |
| 1669 | snps,pbl = <2>; | |
| 1670 | snps,fixed-burst; | |
| 1671 | snps,force_sf_dma_mode; | |
| 1672 | status = "disabled"; | |
| 1673 | #address-cells = <1>; | |
| 1674 | #size-cells = <0>; | |
| 1675 | }; | |
| 1676 | ||
| 31f8ad38 MR |
1677 | hstimer@01c60000 { |
| 1678 | compatible = "allwinner,sun7i-a20-hstimer"; | |
| 1679 | reg = <0x01c60000 0x1000>; | |
| 19882b84 MR |
1680 | interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>, |
| 1681 | <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>, | |
| 1682 | <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>, | |
| 1683 | <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>; | |
| 31f8ad38 MR |
1684 | clocks = <&ahb_gates 28>; |
| 1685 | }; | |
| 1686 | ||
| 4790ecfa MR |
1687 | gic: interrupt-controller@01c81000 { |
| 1688 | compatible = "arm,cortex-a7-gic", "arm,cortex-a15-gic"; | |
| 1689 | reg = <0x01c81000 0x1000>, | |
| 1690 | <0x01c82000 0x1000>, | |
| 1691 | <0x01c84000 0x2000>, | |
| 1692 | <0x01c86000 0x2000>; | |
| 1693 | interrupt-controller; | |
| 1694 | #interrupt-cells = <3>; | |
| 19882b84 | 1695 | interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>; |
| 4790ecfa | 1696 | }; |
| 196654ae VP |
1697 | |
| 1698 | ps20: ps2@01c2a000 { | |
| 1699 | compatible = "allwinner,sun4i-a10-ps2"; | |
| 1700 | reg = <0x01c2a000 0x400>; | |
| 1701 | interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>; | |
| 1702 | clocks = <&apb1_gates 6>; | |
| 1703 | status = "disabled"; | |
| 1704 | }; | |
| 1705 | ||
| 1706 | ps21: ps2@01c2a400 { | |
| 1707 | compatible = "allwinner,sun4i-a10-ps2"; | |
| 1708 | reg = <0x01c2a400 0x400>; | |
| 1709 | interrupts = <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>; | |
| 1710 | clocks = <&apb1_gates 7>; | |
| 1711 | status = "disabled"; | |
| 4790ecfa MR |
1712 | }; |
| 1713 | }; | |
| 1714 | }; |