projects / linux-2.6-block.git / blame
| Commit | Line | Data |
|---|---|---|
| 4790ecfa MR |
1 | /* |
| 2 | * Copyright 2013 Maxime Ripard | |
| 3 | * | |
| 4 | * Maxime Ripard <maxime.ripard@free-electrons.com> | |
| 5 | * | |
| 6 | * The code contained herein is licensed under the GNU General Public | |
| 7 | * License. You may obtain a copy of the GNU General Public License | |
| 8 | * Version 2 or later at the following locations: | |
| 9 | * | |
| 10 | * http://www.opensource.org/licenses/gpl-license.html | |
| 11 | * http://www.gnu.org/copyleft/gpl.html | |
| 12 | */ | |
| 13 | ||
| 14 | /include/ "skeleton.dtsi" | |
| 15 | ||
| 16 | / { | |
| 17 | interrupt-parent = <&gic>; | |
| 18 | ||
| e751cce9 | 19 | aliases { |
| 18428f77 | 20 | ethernet0 = &gmac; |
| 4566b4be MR |
21 | serial0 = &uart0; |
| 22 | serial1 = &uart1; | |
| 23 | serial2 = &uart2; | |
| 24 | serial3 = &uart3; | |
| 25 | serial4 = &uart4; | |
| 26 | serial5 = &uart5; | |
| 27 | serial6 = &uart6; | |
| 28 | serial7 = &uart7; | |
| e751cce9 EL |
29 | }; |
| 30 | ||
| 4790ecfa MR |
31 | cpus { |
| 32 | #address-cells = <1>; | |
| 33 | #size-cells = <0>; | |
| 34 | ||
| 35 | cpu@0 { | |
| 36 | compatible = "arm,cortex-a7"; | |
| 37 | device_type = "cpu"; | |
| 38 | reg = <0>; | |
| 39 | }; | |
| 40 | ||
| 41 | cpu@1 { | |
| 42 | compatible = "arm,cortex-a7"; | |
| 43 | device_type = "cpu"; | |
| 44 | reg = <1>; | |
| 45 | }; | |
| 46 | }; | |
| 47 | ||
| 48 | memory { | |
| 49 | reg = <0x40000000 0x80000000>; | |
| 50 | }; | |
| 51 | ||
| 7902763e MZ |
52 | timer { |
| 53 | compatible = "arm,armv7-timer"; | |
| 54 | interrupts = <1 13 0xf08>, | |
| 55 | <1 14 0xf08>, | |
| 56 | <1 11 0xf08>, | |
| 57 | <1 10 0xf08>; | |
| 58 | }; | |
| 59 | ||
| 4790ecfa MR |
60 | clocks { |
| 61 | #address-cells = <1>; | |
| 62 | #size-cells = <1>; | |
| 63 | ranges; | |
| 64 | ||
| 06067a2f | 65 | osc24M: clk@01c20050 { |
| 4790ecfa | 66 | #clock-cells = <0>; |
| bf6534a1 | 67 | compatible = "allwinner,sun4i-a10-osc-clk"; |
| de7dc935 | 68 | reg = <0x01c20050 0x4>; |
| 4790ecfa | 69 | clock-frequency = <24000000>; |
| 06067a2f | 70 | clock-output-names = "osc24M"; |
| 4790ecfa MR |
71 | }; |
| 72 | ||
| 673fac74 | 73 | osc32k: clk@0 { |
| 4790ecfa MR |
74 | #clock-cells = <0>; |
| 75 | compatible = "fixed-clock"; | |
| 76 | clock-frequency = <32768>; | |
| 673fac74 | 77 | clock-output-names = "osc32k"; |
| 4790ecfa | 78 | }; |
| de7dc935 | 79 | |
| 06067a2f | 80 | pll1: clk@01c20000 { |
| de7dc935 | 81 | #clock-cells = <0>; |
| bf6534a1 | 82 | compatible = "allwinner,sun4i-a10-pll1-clk"; |
| de7dc935 MR |
83 | reg = <0x01c20000 0x4>; |
| 84 | clocks = <&osc24M>; | |
| 06067a2f | 85 | clock-output-names = "pll1"; |
| de7dc935 MR |
86 | }; |
| 87 | ||
| 06067a2f | 88 | pll4: clk@01c20018 { |
| de7dc935 | 89 | #clock-cells = <0>; |
| bf6534a1 | 90 | compatible = "allwinner,sun4i-a10-pll1-clk"; |
| ec5589f7 EL |
91 | reg = <0x01c20018 0x4>; |
| 92 | clocks = <&osc24M>; | |
| 06067a2f | 93 | clock-output-names = "pll4"; |
| ec5589f7 EL |
94 | }; |
| 95 | ||
| 06067a2f | 96 | pll5: clk@01c20020 { |
| c3e5e66b | 97 | #clock-cells = <1>; |
| bf6534a1 | 98 | compatible = "allwinner,sun4i-a10-pll5-clk"; |
| c3e5e66b EL |
99 | reg = <0x01c20020 0x4>; |
| 100 | clocks = <&osc24M>; | |
| 101 | clock-output-names = "pll5_ddr", "pll5_other"; | |
| 102 | }; | |
| 103 | ||
| 06067a2f | 104 | pll6: clk@01c20028 { |
| c3e5e66b | 105 | #clock-cells = <1>; |
| bf6534a1 | 106 | compatible = "allwinner,sun4i-a10-pll6-clk"; |
| c3e5e66b EL |
107 | reg = <0x01c20028 0x4>; |
| 108 | clocks = <&osc24M>; | |
| 109 | clock-output-names = "pll6_sata", "pll6_other", "pll6"; | |
| de7dc935 MR |
110 | }; |
| 111 | ||
| 112 | cpu: cpu@01c20054 { | |
| 113 | #clock-cells = <0>; | |
| bf6534a1 | 114 | compatible = "allwinner,sun4i-a10-cpu-clk"; |
| de7dc935 | 115 | reg = <0x01c20054 0x4>; |
| c3e5e66b | 116 | clocks = <&osc32k>, <&osc24M>, <&pll1>, <&pll6 1>; |
| 06067a2f | 117 | clock-output-names = "cpu"; |
| de7dc935 MR |
118 | }; |
| 119 | ||
| 120 | axi: axi@01c20054 { | |
| 121 | #clock-cells = <0>; | |
| bf6534a1 | 122 | compatible = "allwinner,sun4i-a10-axi-clk"; |
| de7dc935 MR |
123 | reg = <0x01c20054 0x4>; |
| 124 | clocks = <&cpu>; | |
| 06067a2f | 125 | clock-output-names = "axi"; |
| de7dc935 MR |
126 | }; |
| 127 | ||
| 128 | ahb: ahb@01c20054 { | |
| 129 | #clock-cells = <0>; | |
| bf6534a1 | 130 | compatible = "allwinner,sun4i-a10-ahb-clk"; |
| de7dc935 MR |
131 | reg = <0x01c20054 0x4>; |
| 132 | clocks = <&axi>; | |
| 06067a2f | 133 | clock-output-names = "ahb"; |
| de7dc935 MR |
134 | }; |
| 135 | ||
| 06067a2f | 136 | ahb_gates: clk@01c20060 { |
| de7dc935 MR |
137 | #clock-cells = <1>; |
| 138 | compatible = "allwinner,sun7i-a20-ahb-gates-clk"; | |
| 139 | reg = <0x01c20060 0x8>; | |
| 140 | clocks = <&ahb>; | |
| 141 | clock-output-names = "ahb_usb0", "ahb_ehci0", | |
| 142 | "ahb_ohci0", "ahb_ehci1", "ahb_ohci1", | |
| 143 | "ahb_ss", "ahb_dma", "ahb_bist", "ahb_mmc0", | |
| 144 | "ahb_mmc1", "ahb_mmc2", "ahb_mmc3", "ahb_ms", | |
| 145 | "ahb_nand", "ahb_sdram", "ahb_ace", | |
| 146 | "ahb_emac", "ahb_ts", "ahb_spi0", "ahb_spi1", | |
| 147 | "ahb_spi2", "ahb_spi3", "ahb_sata", | |
| 148 | "ahb_hstimer", "ahb_ve", "ahb_tvd", "ahb_tve0", | |
| 149 | "ahb_tve1", "ahb_lcd0", "ahb_lcd1", "ahb_csi0", | |
| 150 | "ahb_csi1", "ahb_hdmi1", "ahb_hdmi0", | |
| 151 | "ahb_de_be0", "ahb_de_be1", "ahb_de_fe0", | |
| 152 | "ahb_de_fe1", "ahb_gmac", "ahb_mp", | |
| 153 | "ahb_mali"; | |
| 154 | }; | |
| 155 | ||
| 156 | apb0: apb0@01c20054 { | |
| 157 | #clock-cells = <0>; | |
| bf6534a1 | 158 | compatible = "allwinner,sun4i-a10-apb0-clk"; |
| de7dc935 MR |
159 | reg = <0x01c20054 0x4>; |
| 160 | clocks = <&ahb>; | |
| 06067a2f | 161 | clock-output-names = "apb0"; |
| de7dc935 MR |
162 | }; |
| 163 | ||
| 06067a2f | 164 | apb0_gates: clk@01c20068 { |
| de7dc935 MR |
165 | #clock-cells = <1>; |
| 166 | compatible = "allwinner,sun7i-a20-apb0-gates-clk"; | |
| 167 | reg = <0x01c20068 0x4>; | |
| 168 | clocks = <&apb0>; | |
| 169 | clock-output-names = "apb0_codec", "apb0_spdif", | |
| 170 | "apb0_ac97", "apb0_iis0", "apb0_iis1", | |
| 171 | "apb0_pio", "apb0_ir0", "apb0_ir1", | |
| 172 | "apb0_iis2", "apb0_keypad"; | |
| 173 | }; | |
| 174 | ||
| 175 | apb1_mux: apb1_mux@01c20058 { | |
| 176 | #clock-cells = <0>; | |
| bf6534a1 | 177 | compatible = "allwinner,sun4i-a10-apb1-mux-clk"; |
| de7dc935 | 178 | reg = <0x01c20058 0x4>; |
| c3e5e66b | 179 | clocks = <&osc24M>, <&pll6 1>, <&osc32k>; |
| 06067a2f | 180 | clock-output-names = "apb1_mux"; |
| de7dc935 MR |
181 | }; |
| 182 | ||
| 183 | apb1: apb1@01c20058 { | |
| 184 | #clock-cells = <0>; | |
| bf6534a1 | 185 | compatible = "allwinner,sun4i-a10-apb1-clk"; |
| de7dc935 MR |
186 | reg = <0x01c20058 0x4>; |
| 187 | clocks = <&apb1_mux>; | |
| 06067a2f | 188 | clock-output-names = "apb1"; |
| de7dc935 MR |
189 | }; |
| 190 | ||
| 06067a2f | 191 | apb1_gates: clk@01c2006c { |
| de7dc935 MR |
192 | #clock-cells = <1>; |
| 193 | compatible = "allwinner,sun7i-a20-apb1-gates-clk"; | |
| 194 | reg = <0x01c2006c 0x4>; | |
| 195 | clocks = <&apb1>; | |
| 196 | clock-output-names = "apb1_i2c0", "apb1_i2c1", | |
| 197 | "apb1_i2c2", "apb1_i2c3", "apb1_can", | |
| 198 | "apb1_scr", "apb1_ps20", "apb1_ps21", | |
| 199 | "apb1_i2c4", "apb1_uart0", "apb1_uart1", | |
| 200 | "apb1_uart2", "apb1_uart3", "apb1_uart4", | |
| 201 | "apb1_uart5", "apb1_uart6", "apb1_uart7"; | |
| 202 | }; | |
| 1c92b95b EL |
203 | |
| 204 | nand_clk: clk@01c20080 { | |
| 205 | #clock-cells = <0>; | |
| bf6534a1 | 206 | compatible = "allwinner,sun4i-a10-mod0-clk"; |
| 1c92b95b EL |
207 | reg = <0x01c20080 0x4>; |
| 208 | clocks = <&osc24M>, <&pll6 1>, <&pll5 1>; | |
| 209 | clock-output-names = "nand"; | |
| 210 | }; | |
| 211 | ||
| 212 | ms_clk: clk@01c20084 { | |
| 213 | #clock-cells = <0>; | |
| bf6534a1 | 214 | compatible = "allwinner,sun4i-a10-mod0-clk"; |
| 1c92b95b EL |
215 | reg = <0x01c20084 0x4>; |
| 216 | clocks = <&osc24M>, <&pll6 1>, <&pll5 1>; | |
| 217 | clock-output-names = "ms"; | |
| 218 | }; | |
| 219 | ||
| 220 | mmc0_clk: clk@01c20088 { | |
| 221 | #clock-cells = <0>; | |
| bf6534a1 | 222 | compatible = "allwinner,sun4i-a10-mod0-clk"; |
| 1c92b95b EL |
223 | reg = <0x01c20088 0x4>; |
| 224 | clocks = <&osc24M>, <&pll6 1>, <&pll5 1>; | |
| 225 | clock-output-names = "mmc0"; | |
| 226 | }; | |
| 227 | ||
| 228 | mmc1_clk: clk@01c2008c { | |
| 229 | #clock-cells = <0>; | |
| bf6534a1 | 230 | compatible = "allwinner,sun4i-a10-mod0-clk"; |
| 1c92b95b EL |
231 | reg = <0x01c2008c 0x4>; |
| 232 | clocks = <&osc24M>, <&pll6 1>, <&pll5 1>; | |
| 233 | clock-output-names = "mmc1"; | |
| 234 | }; | |
| 235 | ||
| 236 | mmc2_clk: clk@01c20090 { | |
| 237 | #clock-cells = <0>; | |
| bf6534a1 | 238 | compatible = "allwinner,sun4i-a10-mod0-clk"; |
| 1c92b95b EL |
239 | reg = <0x01c20090 0x4>; |
| 240 | clocks = <&osc24M>, <&pll6 1>, <&pll5 1>; | |
| 241 | clock-output-names = "mmc2"; | |
| 242 | }; | |
| 243 | ||
| 244 | mmc3_clk: clk@01c20094 { | |
| 245 | #clock-cells = <0>; | |
| bf6534a1 | 246 | compatible = "allwinner,sun4i-a10-mod0-clk"; |
| 1c92b95b EL |
247 | reg = <0x01c20094 0x4>; |
| 248 | clocks = <&osc24M>, <&pll6 1>, <&pll5 1>; | |
| 249 | clock-output-names = "mmc3"; | |
| 250 | }; | |
| 251 | ||
| 252 | ts_clk: clk@01c20098 { | |
| 253 | #clock-cells = <0>; | |
| bf6534a1 | 254 | compatible = "allwinner,sun4i-a10-mod0-clk"; |
| 1c92b95b EL |
255 | reg = <0x01c20098 0x4>; |
| 256 | clocks = <&osc24M>, <&pll6 1>, <&pll5 1>; | |
| 257 | clock-output-names = "ts"; | |
| 258 | }; | |
| 259 | ||
| 260 | ss_clk: clk@01c2009c { | |
| 261 | #clock-cells = <0>; | |
| bf6534a1 | 262 | compatible = "allwinner,sun4i-a10-mod0-clk"; |
| 1c92b95b EL |
263 | reg = <0x01c2009c 0x4>; |
| 264 | clocks = <&osc24M>, <&pll6 1>, <&pll5 1>; | |
| 265 | clock-output-names = "ss"; | |
| 266 | }; | |
| 267 | ||
| 268 | spi0_clk: clk@01c200a0 { | |
| 269 | #clock-cells = <0>; | |
| bf6534a1 | 270 | compatible = "allwinner,sun4i-a10-mod0-clk"; |
| 1c92b95b EL |
271 | reg = <0x01c200a0 0x4>; |
| 272 | clocks = <&osc24M>, <&pll6 1>, <&pll5 1>; | |
| 273 | clock-output-names = "spi0"; | |
| 274 | }; | |
| 275 | ||
| 276 | spi1_clk: clk@01c200a4 { | |
| 277 | #clock-cells = <0>; | |
| bf6534a1 | 278 | compatible = "allwinner,sun4i-a10-mod0-clk"; |
| 1c92b95b EL |
279 | reg = <0x01c200a4 0x4>; |
| 280 | clocks = <&osc24M>, <&pll6 1>, <&pll5 1>; | |
| 281 | clock-output-names = "spi1"; | |
| 282 | }; | |
| 283 | ||
| 284 | spi2_clk: clk@01c200a8 { | |
| 285 | #clock-cells = <0>; | |
| bf6534a1 | 286 | compatible = "allwinner,sun4i-a10-mod0-clk"; |
| 1c92b95b EL |
287 | reg = <0x01c200a8 0x4>; |
| 288 | clocks = <&osc24M>, <&pll6 1>, <&pll5 1>; | |
| 289 | clock-output-names = "spi2"; | |
| 290 | }; | |
| 291 | ||
| 292 | pata_clk: clk@01c200ac { | |
| 293 | #clock-cells = <0>; | |
| bf6534a1 | 294 | compatible = "allwinner,sun4i-a10-mod0-clk"; |
| 1c92b95b EL |
295 | reg = <0x01c200ac 0x4>; |
| 296 | clocks = <&osc24M>, <&pll6 1>, <&pll5 1>; | |
| 297 | clock-output-names = "pata"; | |
| 298 | }; | |
| 299 | ||
| 300 | ir0_clk: clk@01c200b0 { | |
| 301 | #clock-cells = <0>; | |
| bf6534a1 | 302 | compatible = "allwinner,sun4i-a10-mod0-clk"; |
| 1c92b95b EL |
303 | reg = <0x01c200b0 0x4>; |
| 304 | clocks = <&osc24M>, <&pll6 1>, <&pll5 1>; | |
| 305 | clock-output-names = "ir0"; | |
| 306 | }; | |
| 307 | ||
| 308 | ir1_clk: clk@01c200b4 { | |
| 309 | #clock-cells = <0>; | |
| bf6534a1 | 310 | compatible = "allwinner,sun4i-a10-mod0-clk"; |
| 1c92b95b EL |
311 | reg = <0x01c200b4 0x4>; |
| 312 | clocks = <&osc24M>, <&pll6 1>, <&pll5 1>; | |
| 313 | clock-output-names = "ir1"; | |
| 314 | }; | |
| 315 | ||
| 434e41b3 RB |
316 | usb_clk: clk@01c200cc { |
| 317 | #clock-cells = <1>; | |
| 318 | #reset-cells = <1>; | |
| 319 | compatible = "allwinner,sun4i-a10-usb-clk"; | |
| 320 | reg = <0x01c200cc 0x4>; | |
| 321 | clocks = <&pll6 1>; | |
| 322 | clock-output-names = "usb_ohci0", "usb_ohci1", "usb_phy"; | |
| 323 | }; | |
| 324 | ||
| 1c92b95b EL |
325 | spi3_clk: clk@01c200d4 { |
| 326 | #clock-cells = <0>; | |
| bf6534a1 | 327 | compatible = "allwinner,sun4i-a10-mod0-clk"; |
| 1c92b95b EL |
328 | reg = <0x01c200d4 0x4>; |
| 329 | clocks = <&osc24M>, <&pll6 1>, <&pll5 1>; | |
| 330 | clock-output-names = "spi3"; | |
| 331 | }; | |
| 118c07ae EL |
332 | |
| 333 | mbus_clk: clk@01c2015c { | |
| 334 | #clock-cells = <0>; | |
| bf6534a1 | 335 | compatible = "allwinner,sun4i-a10-mod0-clk"; |
| 118c07ae EL |
336 | reg = <0x01c2015c 0x4>; |
| 337 | clocks = <&osc24M>, <&pll6 2>, <&pll5 1>; | |
| 338 | clock-output-names = "mbus"; | |
| 339 | }; | |
| 0aff0370 | 340 | |
| daed5a81 CYT |
341 | /* |
| 342 | * The following two are dummy clocks, placeholders used in the gmac_tx | |
| 343 | * clock. The gmac driver will choose one parent depending on the PHY | |
| 344 | * interface mode, using clk_set_rate auto-reparenting. | |
| 345 | * The actual TX clock rate is not controlled by the gmac_tx clock. | |
| 346 | */ | |
| 347 | mii_phy_tx_clk: clk@2 { | |
| 348 | #clock-cells = <0>; | |
| 349 | compatible = "fixed-clock"; | |
| 350 | clock-frequency = <25000000>; | |
| 351 | clock-output-names = "mii_phy_tx"; | |
| 352 | }; | |
| 353 | ||
| 354 | gmac_int_tx_clk: clk@3 { | |
| 355 | #clock-cells = <0>; | |
| 356 | compatible = "fixed-clock"; | |
| 357 | clock-frequency = <125000000>; | |
| 358 | clock-output-names = "gmac_int_tx"; | |
| 359 | }; | |
| 360 | ||
| 361 | gmac_tx_clk: clk@01c20164 { | |
| 362 | #clock-cells = <0>; | |
| 363 | compatible = "allwinner,sun7i-a20-gmac-clk"; | |
| 364 | reg = <0x01c20164 0x4>; | |
| 365 | clocks = <&mii_phy_tx_clk>, <&gmac_int_tx_clk>; | |
| 366 | clock-output-names = "gmac_tx"; | |
| 367 | }; | |
| 368 | ||
| 0aff0370 CYT |
369 | /* |
| 370 | * Dummy clock used by output clocks | |
| 371 | */ | |
| 372 | osc24M_32k: clk@1 { | |
| 373 | #clock-cells = <0>; | |
| 374 | compatible = "fixed-factor-clock"; | |
| 375 | clock-div = <750>; | |
| 376 | clock-mult = <1>; | |
| 377 | clocks = <&osc24M>; | |
| 378 | clock-output-names = "osc24M_32k"; | |
| 379 | }; | |
| 380 | ||
| 381 | clk_out_a: clk@01c201f0 { | |
| 382 | #clock-cells = <0>; | |
| 383 | compatible = "allwinner,sun7i-a20-out-clk"; | |
| 384 | reg = <0x01c201f0 0x4>; | |
| 385 | clocks = <&osc24M_32k>, <&osc32k>, <&osc24M>; | |
| 386 | clock-output-names = "clk_out_a"; | |
| 387 | }; | |
| 388 | ||
| 389 | clk_out_b: clk@01c201f4 { | |
| 390 | #clock-cells = <0>; | |
| 391 | compatible = "allwinner,sun7i-a20-out-clk"; | |
| 392 | reg = <0x01c201f4 0x4>; | |
| 393 | clocks = <&osc24M_32k>, <&osc32k>, <&osc24M>; | |
| 394 | clock-output-names = "clk_out_b"; | |
| 395 | }; | |
| 4790ecfa MR |
396 | }; |
| 397 | ||
| 398 | soc@01c00000 { | |
| 399 | compatible = "simple-bus"; | |
| 400 | #address-cells = <1>; | |
| 401 | #size-cells = <1>; | |
| 402 | ranges; | |
| 403 | ||
| 36ab3e73 MR |
404 | spi0: spi@01c05000 { |
| 405 | compatible = "allwinner,sun4i-a10-spi"; | |
| 406 | reg = <0x01c05000 0x1000>; | |
| 407 | interrupts = <0 10 4>; | |
| 408 | clocks = <&ahb_gates 20>, <&spi0_clk>; | |
| 409 | clock-names = "ahb", "mod"; | |
| 410 | status = "disabled"; | |
| 411 | #address-cells = <1>; | |
| 412 | #size-cells = <0>; | |
| 413 | }; | |
| 414 | ||
| 415 | spi1: spi@01c06000 { | |
| 416 | compatible = "allwinner,sun4i-a10-spi"; | |
| 417 | reg = <0x01c06000 0x1000>; | |
| 418 | interrupts = <0 11 4>; | |
| 419 | clocks = <&ahb_gates 21>, <&spi1_clk>; | |
| 420 | clock-names = "ahb", "mod"; | |
| 421 | status = "disabled"; | |
| 422 | #address-cells = <1>; | |
| 423 | #size-cells = <0>; | |
| 424 | }; | |
| 425 | ||
| 2e804d03 MR |
426 | emac: ethernet@01c0b000 { |
| 427 | compatible = "allwinner,sun4i-emac"; | |
| 428 | reg = <0x01c0b000 0x1000>; | |
| 378d0aee | 429 | interrupts = <0 55 4>; |
| 2e804d03 MR |
430 | clocks = <&ahb_gates 17>; |
| 431 | status = "disabled"; | |
| 432 | }; | |
| 433 | ||
| 434 | mdio@01c0b080 { | |
| 435 | compatible = "allwinner,sun4i-mdio"; | |
| 436 | reg = <0x01c0b080 0x14>; | |
| 437 | status = "disabled"; | |
| 36ab3e73 MR |
438 | #address-cells = <1>; |
| 439 | #size-cells = <0>; | |
| 440 | }; | |
| 441 | ||
| 442 | spi2: spi@01c17000 { | |
| 443 | compatible = "allwinner,sun4i-a10-spi"; | |
| 444 | reg = <0x01c17000 0x1000>; | |
| 445 | interrupts = <0 12 4>; | |
| 446 | clocks = <&ahb_gates 22>, <&spi2_clk>; | |
| 447 | clock-names = "ahb", "mod"; | |
| 448 | status = "disabled"; | |
| 449 | #address-cells = <1>; | |
| 450 | #size-cells = <0>; | |
| 451 | }; | |
| 452 | ||
| 453 | spi3: spi@01c1f000 { | |
| 454 | compatible = "allwinner,sun4i-a10-spi"; | |
| 455 | reg = <0x01c1f000 0x1000>; | |
| 456 | interrupts = <0 50 4>; | |
| 457 | clocks = <&ahb_gates 23>, <&spi3_clk>; | |
| 458 | clock-names = "ahb", "mod"; | |
| 459 | status = "disabled"; | |
| 2e804d03 MR |
460 | #address-cells = <1>; |
| 461 | #size-cells = <0>; | |
| 462 | }; | |
| 463 | ||
| 17eac031 MR |
464 | pio: pinctrl@01c20800 { |
| 465 | compatible = "allwinner,sun7i-a20-pinctrl"; | |
| 466 | reg = <0x01c20800 0x400>; | |
| 378d0aee | 467 | interrupts = <0 28 4>; |
| de7dc935 | 468 | clocks = <&apb0_gates 5>; |
| 17eac031 MR |
469 | gpio-controller; |
| 470 | interrupt-controller; | |
| 471 | #address-cells = <1>; | |
| 472 | #size-cells = <0>; | |
| 473 | #gpio-cells = <3>; | |
| 9f229ba9 MR |
474 | |
| 475 | uart0_pins_a: uart0@0 { | |
| 476 | allwinner,pins = "PB22", "PB23"; | |
| 477 | allwinner,function = "uart0"; | |
| 478 | allwinner,drive = <0>; | |
| 479 | allwinner,pull = <0>; | |
| 480 | }; | |
| 481 | ||
| 4261ec43 CYT |
482 | uart2_pins_a: uart2@0 { |
| 483 | allwinner,pins = "PI16", "PI17", "PI18", "PI19"; | |
| 484 | allwinner,function = "uart2"; | |
| 485 | allwinner,drive = <0>; | |
| 486 | allwinner,pull = <0>; | |
| 487 | }; | |
| 488 | ||
| 9f229ba9 MR |
489 | uart6_pins_a: uart6@0 { |
| 490 | allwinner,pins = "PI12", "PI13"; | |
| 491 | allwinner,function = "uart6"; | |
| 492 | allwinner,drive = <0>; | |
| 493 | allwinner,pull = <0>; | |
| 494 | }; | |
| 495 | ||
| 496 | uart7_pins_a: uart7@0 { | |
| 497 | allwinner,pins = "PI20", "PI21"; | |
| 498 | allwinner,function = "uart7"; | |
| 499 | allwinner,drive = <0>; | |
| 500 | allwinner,pull = <0>; | |
| 501 | }; | |
| 756084c5 | 502 | |
| e5496a31 MR |
503 | i2c0_pins_a: i2c0@0 { |
| 504 | allwinner,pins = "PB0", "PB1"; | |
| 505 | allwinner,function = "i2c0"; | |
| 506 | allwinner,drive = <0>; | |
| 507 | allwinner,pull = <0>; | |
| 508 | }; | |
| 509 | ||
| 510 | i2c1_pins_a: i2c1@0 { | |
| 511 | allwinner,pins = "PB18", "PB19"; | |
| 512 | allwinner,function = "i2c1"; | |
| 513 | allwinner,drive = <0>; | |
| 514 | allwinner,pull = <0>; | |
| 515 | }; | |
| 516 | ||
| 517 | i2c2_pins_a: i2c2@0 { | |
| 518 | allwinner,pins = "PB20", "PB21"; | |
| 519 | allwinner,function = "i2c2"; | |
| 520 | allwinner,drive = <0>; | |
| 521 | allwinner,pull = <0>; | |
| 522 | }; | |
| 523 | ||
| 756084c5 MR |
524 | emac_pins_a: emac0@0 { |
| 525 | allwinner,pins = "PA0", "PA1", "PA2", | |
| 526 | "PA3", "PA4", "PA5", "PA6", | |
| 527 | "PA7", "PA8", "PA9", "PA10", | |
| 528 | "PA11", "PA12", "PA13", "PA14", | |
| 529 | "PA15", "PA16"; | |
| 530 | allwinner,function = "emac"; | |
| 531 | allwinner,drive = <0>; | |
| 532 | allwinner,pull = <0>; | |
| 533 | }; | |
| f2e0759e CYT |
534 | |
| 535 | clk_out_a_pins_a: clk_out_a@0 { | |
| 536 | allwinner,pins = "PI12"; | |
| 537 | allwinner,function = "clk_out_a"; | |
| 538 | allwinner,drive = <0>; | |
| 539 | allwinner,pull = <0>; | |
| 540 | }; | |
| 541 | ||
| 542 | clk_out_b_pins_a: clk_out_b@0 { | |
| 543 | allwinner,pins = "PI13"; | |
| 544 | allwinner,function = "clk_out_b"; | |
| 545 | allwinner,drive = <0>; | |
| 546 | allwinner,pull = <0>; | |
| 547 | }; | |
| 129ccbcd CYT |
548 | |
| 549 | gmac_pins_mii_a: gmac_mii@0 { | |
| 550 | allwinner,pins = "PA0", "PA1", "PA2", | |
| 551 | "PA3", "PA4", "PA5", "PA6", | |
| 552 | "PA7", "PA8", "PA9", "PA10", | |
| 553 | "PA11", "PA12", "PA13", "PA14", | |
| 554 | "PA15", "PA16"; | |
| 555 | allwinner,function = "gmac"; | |
| 556 | allwinner,drive = <0>; | |
| 557 | allwinner,pull = <0>; | |
| 558 | }; | |
| 559 | ||
| 560 | gmac_pins_rgmii_a: gmac_rgmii@0 { | |
| 561 | allwinner,pins = "PA0", "PA1", "PA2", | |
| 562 | "PA3", "PA4", "PA5", "PA6", | |
| 563 | "PA7", "PA8", "PA10", | |
| 564 | "PA11", "PA12", "PA13", | |
| 565 | "PA15", "PA16"; | |
| 566 | allwinner,function = "gmac"; | |
| 567 | /* | |
| 568 | * data lines in RGMII mode use DDR mode | |
| 569 | * and need a higher signal drive strength | |
| 570 | */ | |
| 571 | allwinner,drive = <3>; | |
| 572 | allwinner,pull = <0>; | |
| 573 | }; | |
| 17eac031 MR |
574 | }; |
| 575 | ||
| 4790ecfa MR |
576 | timer@01c20c00 { |
| 577 | compatible = "allwinner,sun4i-timer"; | |
| 578 | reg = <0x01c20c00 0x90>; | |
| 378d0aee MR |
579 | interrupts = <0 22 4>, |
| 580 | <0 23 4>, | |
| 581 | <0 24 4>, | |
| 582 | <0 25 4>, | |
| 583 | <0 67 4>, | |
| 584 | <0 68 4>; | |
| 4790ecfa MR |
585 | clocks = <&osc24M>; |
| 586 | }; | |
| 587 | ||
| 588 | wdt: watchdog@01c20c90 { | |
| 589 | compatible = "allwinner,sun4i-wdt"; | |
| 590 | reg = <0x01c20c90 0x10>; | |
| 591 | }; | |
| 592 | ||
| b5d905c7 CC |
593 | rtc: rtc@01c20d00 { |
| 594 | compatible = "allwinner,sun7i-a20-rtc"; | |
| 595 | reg = <0x01c20d00 0x20>; | |
| 596 | interrupts = <0 24 1>; | |
| 597 | }; | |
| 598 | ||
| 2bad969f OS |
599 | sid: eeprom@01c23800 { |
| 600 | compatible = "allwinner,sun7i-a20-sid"; | |
| 601 | reg = <0x01c23800 0x200>; | |
| 602 | }; | |
| 603 | ||
| 00f7ed8d HG |
604 | rtp: rtp@01c25000 { |
| 605 | compatible = "allwinner,sun4i-ts"; | |
| 606 | reg = <0x01c25000 0x100>; | |
| 607 | interrupts = <0 29 4>; | |
| 608 | }; | |
| 609 | ||
| 4790ecfa MR |
610 | uart0: serial@01c28000 { |
| 611 | compatible = "snps,dw-apb-uart"; | |
| 612 | reg = <0x01c28000 0x400>; | |
| 378d0aee | 613 | interrupts = <0 1 4>; |
| 4790ecfa MR |
614 | reg-shift = <2>; |
| 615 | reg-io-width = <4>; | |
| de7dc935 | 616 | clocks = <&apb1_gates 16>; |
| 4790ecfa MR |
617 | status = "disabled"; |
| 618 | }; | |
| 619 | ||
| 620 | uart1: serial@01c28400 { | |
| 621 | compatible = "snps,dw-apb-uart"; | |
| 622 | reg = <0x01c28400 0x400>; | |
| 378d0aee | 623 | interrupts = <0 2 4>; |
| 4790ecfa MR |
624 | reg-shift = <2>; |
| 625 | reg-io-width = <4>; | |
| de7dc935 | 626 | clocks = <&apb1_gates 17>; |
| 4790ecfa MR |
627 | status = "disabled"; |
| 628 | }; | |
| 629 | ||
| 630 | uart2: serial@01c28800 { | |
| 631 | compatible = "snps,dw-apb-uart"; | |
| 632 | reg = <0x01c28800 0x400>; | |
| 378d0aee | 633 | interrupts = <0 3 4>; |
| 4790ecfa MR |
634 | reg-shift = <2>; |
| 635 | reg-io-width = <4>; | |
| de7dc935 | 636 | clocks = <&apb1_gates 18>; |
| 4790ecfa MR |
637 | status = "disabled"; |
| 638 | }; | |
| 639 | ||
| 640 | uart3: serial@01c28c00 { | |
| 641 | compatible = "snps,dw-apb-uart"; | |
| 642 | reg = <0x01c28c00 0x400>; | |
| 378d0aee | 643 | interrupts = <0 4 4>; |
| 4790ecfa MR |
644 | reg-shift = <2>; |
| 645 | reg-io-width = <4>; | |
| de7dc935 | 646 | clocks = <&apb1_gates 19>; |
| 4790ecfa MR |
647 | status = "disabled"; |
| 648 | }; | |
| 649 | ||
| 650 | uart4: serial@01c29000 { | |
| 651 | compatible = "snps,dw-apb-uart"; | |
| 652 | reg = <0x01c29000 0x400>; | |
| 378d0aee | 653 | interrupts = <0 17 4>; |
| 4790ecfa MR |
654 | reg-shift = <2>; |
| 655 | reg-io-width = <4>; | |
| de7dc935 | 656 | clocks = <&apb1_gates 20>; |
| 4790ecfa MR |
657 | status = "disabled"; |
| 658 | }; | |
| 659 | ||
| 660 | uart5: serial@01c29400 { | |
| 661 | compatible = "snps,dw-apb-uart"; | |
| 662 | reg = <0x01c29400 0x400>; | |
| 378d0aee | 663 | interrupts = <0 18 4>; |
| 4790ecfa MR |
664 | reg-shift = <2>; |
| 665 | reg-io-width = <4>; | |
| de7dc935 | 666 | clocks = <&apb1_gates 21>; |
| 4790ecfa MR |
667 | status = "disabled"; |
| 668 | }; | |
| 669 | ||
| 670 | uart6: serial@01c29800 { | |
| 671 | compatible = "snps,dw-apb-uart"; | |
| 672 | reg = <0x01c29800 0x400>; | |
| 378d0aee | 673 | interrupts = <0 19 4>; |
| 4790ecfa MR |
674 | reg-shift = <2>; |
| 675 | reg-io-width = <4>; | |
| de7dc935 | 676 | clocks = <&apb1_gates 22>; |
| 4790ecfa MR |
677 | status = "disabled"; |
| 678 | }; | |
| 679 | ||
| 680 | uart7: serial@01c29c00 { | |
| 681 | compatible = "snps,dw-apb-uart"; | |
| 682 | reg = <0x01c29c00 0x400>; | |
| 378d0aee | 683 | interrupts = <0 20 4>; |
| 4790ecfa MR |
684 | reg-shift = <2>; |
| 685 | reg-io-width = <4>; | |
| de7dc935 | 686 | clocks = <&apb1_gates 23>; |
| 4790ecfa MR |
687 | status = "disabled"; |
| 688 | }; | |
| 689 | ||
| 428abbb8 MR |
690 | i2c0: i2c@01c2ac00 { |
| 691 | compatible = "allwinner,sun4i-i2c"; | |
| 692 | reg = <0x01c2ac00 0x400>; | |
| 378d0aee | 693 | interrupts = <0 7 4>; |
| 428abbb8 MR |
694 | clocks = <&apb1_gates 0>; |
| 695 | clock-frequency = <100000>; | |
| 696 | status = "disabled"; | |
| 697 | }; | |
| 698 | ||
| 699 | i2c1: i2c@01c2b000 { | |
| 700 | compatible = "allwinner,sun4i-i2c"; | |
| 701 | reg = <0x01c2b000 0x400>; | |
| 378d0aee | 702 | interrupts = <0 8 4>; |
| 428abbb8 MR |
703 | clocks = <&apb1_gates 1>; |
| 704 | clock-frequency = <100000>; | |
| 705 | status = "disabled"; | |
| 706 | }; | |
| 707 | ||
| 708 | i2c2: i2c@01c2b400 { | |
| 709 | compatible = "allwinner,sun4i-i2c"; | |
| 710 | reg = <0x01c2b400 0x400>; | |
| 378d0aee | 711 | interrupts = <0 9 4>; |
| 428abbb8 MR |
712 | clocks = <&apb1_gates 2>; |
| 713 | clock-frequency = <100000>; | |
| 714 | status = "disabled"; | |
| 715 | }; | |
| 716 | ||
| 717 | i2c3: i2c@01c2b800 { | |
| 718 | compatible = "allwinner,sun4i-i2c"; | |
| 719 | reg = <0x01c2b800 0x400>; | |
| 378d0aee | 720 | interrupts = <0 88 4>; |
| 428abbb8 MR |
721 | clocks = <&apb1_gates 3>; |
| 722 | clock-frequency = <100000>; | |
| 723 | status = "disabled"; | |
| 724 | }; | |
| 725 | ||
| 726 | i2c4: i2c@01c2bc00 { | |
| 727 | compatible = "allwinner,sun4i-i2c"; | |
| 728 | reg = <0x01c2bc00 0x400>; | |
| 378d0aee | 729 | interrupts = <0 89 4>; |
| 428abbb8 MR |
730 | clocks = <&apb1_gates 15>; |
| 731 | clock-frequency = <100000>; | |
| 732 | status = "disabled"; | |
| 733 | }; | |
| 734 | ||
| c40b8d58 CYT |
735 | gmac: ethernet@01c50000 { |
| 736 | compatible = "allwinner,sun7i-a20-gmac"; | |
| 737 | reg = <0x01c50000 0x10000>; | |
| 738 | interrupts = <0 85 4>; | |
| 739 | interrupt-names = "macirq"; | |
| 740 | clocks = <&ahb_gates 49>, <&gmac_tx_clk>; | |
| 741 | clock-names = "stmmaceth", "allwinner_gmac_tx"; | |
| 742 | snps,pbl = <2>; | |
| 743 | snps,fixed-burst; | |
| 744 | snps,force_sf_dma_mode; | |
| 745 | status = "disabled"; | |
| 746 | #address-cells = <1>; | |
| 747 | #size-cells = <0>; | |
| 748 | }; | |
| 749 | ||
| 31f8ad38 MR |
750 | hstimer@01c60000 { |
| 751 | compatible = "allwinner,sun7i-a20-hstimer"; | |
| 752 | reg = <0x01c60000 0x1000>; | |
| 753 | interrupts = <0 81 1>, | |
| 754 | <0 82 1>, | |
| 755 | <0 83 1>, | |
| 756 | <0 84 1>; | |
| 757 | clocks = <&ahb_gates 28>; | |
| 758 | }; | |
| 759 | ||
| 4790ecfa MR |
760 | gic: interrupt-controller@01c81000 { |
| 761 | compatible = "arm,cortex-a7-gic", "arm,cortex-a15-gic"; | |
| 762 | reg = <0x01c81000 0x1000>, | |
| 763 | <0x01c82000 0x1000>, | |
| 764 | <0x01c84000 0x2000>, | |
| 765 | <0x01c86000 0x2000>; | |
| 766 | interrupt-controller; | |
| 767 | #interrupt-cells = <3>; | |
| 768 | interrupts = <1 9 0xf04>; | |
| 769 | }; | |
| 770 | }; | |
| 771 | }; |