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4790ecfa MR |
1 | /* |
2 | * Copyright 2013 Maxime Ripard | |
3 | * | |
4 | * Maxime Ripard <maxime.ripard@free-electrons.com> | |
5 | * | |
6 | * The code contained herein is licensed under the GNU General Public | |
7 | * License. You may obtain a copy of the GNU General Public License | |
8 | * Version 2 or later at the following locations: | |
9 | * | |
10 | * http://www.opensource.org/licenses/gpl-license.html | |
11 | * http://www.gnu.org/copyleft/gpl.html | |
12 | */ | |
13 | ||
14 | /include/ "skeleton.dtsi" | |
15 | ||
16 | / { | |
17 | interrupt-parent = <&gic>; | |
18 | ||
19 | cpus { | |
20 | #address-cells = <1>; | |
21 | #size-cells = <0>; | |
22 | ||
23 | cpu@0 { | |
24 | compatible = "arm,cortex-a7"; | |
25 | device_type = "cpu"; | |
26 | reg = <0>; | |
27 | }; | |
28 | ||
29 | cpu@1 { | |
30 | compatible = "arm,cortex-a7"; | |
31 | device_type = "cpu"; | |
32 | reg = <1>; | |
33 | }; | |
34 | }; | |
35 | ||
36 | memory { | |
37 | reg = <0x40000000 0x80000000>; | |
38 | }; | |
39 | ||
40 | clocks { | |
41 | #address-cells = <1>; | |
42 | #size-cells = <1>; | |
43 | ranges; | |
44 | ||
45 | osc24M: osc24M@01c20050 { | |
46 | #clock-cells = <0>; | |
de7dc935 MR |
47 | compatible = "allwinner,sun4i-osc-clk"; |
48 | reg = <0x01c20050 0x4>; | |
4790ecfa MR |
49 | clock-frequency = <24000000>; |
50 | }; | |
51 | ||
52 | osc32k: osc32k { | |
53 | #clock-cells = <0>; | |
54 | compatible = "fixed-clock"; | |
55 | clock-frequency = <32768>; | |
56 | }; | |
de7dc935 MR |
57 | |
58 | pll1: pll1@01c20000 { | |
59 | #clock-cells = <0>; | |
60 | compatible = "allwinner,sun4i-pll1-clk"; | |
61 | reg = <0x01c20000 0x4>; | |
62 | clocks = <&osc24M>; | |
63 | }; | |
64 | ||
65 | /* | |
66 | * This is a dummy clock, to be used as placeholder on | |
67 | * other mux clocks when a specific parent clock is not | |
68 | * yet implemented. It should be dropped when the driver | |
69 | * is complete. | |
70 | */ | |
71 | pll6: pll6 { | |
72 | #clock-cells = <0>; | |
73 | compatible = "fixed-clock"; | |
74 | clock-frequency = <0>; | |
75 | }; | |
76 | ||
77 | cpu: cpu@01c20054 { | |
78 | #clock-cells = <0>; | |
79 | compatible = "allwinner,sun4i-cpu-clk"; | |
80 | reg = <0x01c20054 0x4>; | |
81 | clocks = <&osc32k>, <&osc24M>, <&pll1>, <&pll6>; | |
82 | }; | |
83 | ||
84 | axi: axi@01c20054 { | |
85 | #clock-cells = <0>; | |
86 | compatible = "allwinner,sun4i-axi-clk"; | |
87 | reg = <0x01c20054 0x4>; | |
88 | clocks = <&cpu>; | |
89 | }; | |
90 | ||
91 | ahb: ahb@01c20054 { | |
92 | #clock-cells = <0>; | |
93 | compatible = "allwinner,sun4i-ahb-clk"; | |
94 | reg = <0x01c20054 0x4>; | |
95 | clocks = <&axi>; | |
96 | }; | |
97 | ||
98 | ahb_gates: ahb_gates@01c20060 { | |
99 | #clock-cells = <1>; | |
100 | compatible = "allwinner,sun7i-a20-ahb-gates-clk"; | |
101 | reg = <0x01c20060 0x8>; | |
102 | clocks = <&ahb>; | |
103 | clock-output-names = "ahb_usb0", "ahb_ehci0", | |
104 | "ahb_ohci0", "ahb_ehci1", "ahb_ohci1", | |
105 | "ahb_ss", "ahb_dma", "ahb_bist", "ahb_mmc0", | |
106 | "ahb_mmc1", "ahb_mmc2", "ahb_mmc3", "ahb_ms", | |
107 | "ahb_nand", "ahb_sdram", "ahb_ace", | |
108 | "ahb_emac", "ahb_ts", "ahb_spi0", "ahb_spi1", | |
109 | "ahb_spi2", "ahb_spi3", "ahb_sata", | |
110 | "ahb_hstimer", "ahb_ve", "ahb_tvd", "ahb_tve0", | |
111 | "ahb_tve1", "ahb_lcd0", "ahb_lcd1", "ahb_csi0", | |
112 | "ahb_csi1", "ahb_hdmi1", "ahb_hdmi0", | |
113 | "ahb_de_be0", "ahb_de_be1", "ahb_de_fe0", | |
114 | "ahb_de_fe1", "ahb_gmac", "ahb_mp", | |
115 | "ahb_mali"; | |
116 | }; | |
117 | ||
118 | apb0: apb0@01c20054 { | |
119 | #clock-cells = <0>; | |
120 | compatible = "allwinner,sun4i-apb0-clk"; | |
121 | reg = <0x01c20054 0x4>; | |
122 | clocks = <&ahb>; | |
123 | }; | |
124 | ||
125 | apb0_gates: apb0_gates@01c20068 { | |
126 | #clock-cells = <1>; | |
127 | compatible = "allwinner,sun7i-a20-apb0-gates-clk"; | |
128 | reg = <0x01c20068 0x4>; | |
129 | clocks = <&apb0>; | |
130 | clock-output-names = "apb0_codec", "apb0_spdif", | |
131 | "apb0_ac97", "apb0_iis0", "apb0_iis1", | |
132 | "apb0_pio", "apb0_ir0", "apb0_ir1", | |
133 | "apb0_iis2", "apb0_keypad"; | |
134 | }; | |
135 | ||
136 | apb1_mux: apb1_mux@01c20058 { | |
137 | #clock-cells = <0>; | |
138 | compatible = "allwinner,sun4i-apb1-mux-clk"; | |
139 | reg = <0x01c20058 0x4>; | |
140 | clocks = <&osc24M>, <&pll6>, <&osc32k>; | |
141 | }; | |
142 | ||
143 | apb1: apb1@01c20058 { | |
144 | #clock-cells = <0>; | |
145 | compatible = "allwinner,sun4i-apb1-clk"; | |
146 | reg = <0x01c20058 0x4>; | |
147 | clocks = <&apb1_mux>; | |
148 | }; | |
149 | ||
150 | apb1_gates: apb1_gates@01c2006c { | |
151 | #clock-cells = <1>; | |
152 | compatible = "allwinner,sun7i-a20-apb1-gates-clk"; | |
153 | reg = <0x01c2006c 0x4>; | |
154 | clocks = <&apb1>; | |
155 | clock-output-names = "apb1_i2c0", "apb1_i2c1", | |
156 | "apb1_i2c2", "apb1_i2c3", "apb1_can", | |
157 | "apb1_scr", "apb1_ps20", "apb1_ps21", | |
158 | "apb1_i2c4", "apb1_uart0", "apb1_uart1", | |
159 | "apb1_uart2", "apb1_uart3", "apb1_uart4", | |
160 | "apb1_uart5", "apb1_uart6", "apb1_uart7"; | |
161 | }; | |
4790ecfa MR |
162 | }; |
163 | ||
164 | soc@01c00000 { | |
165 | compatible = "simple-bus"; | |
166 | #address-cells = <1>; | |
167 | #size-cells = <1>; | |
168 | ranges; | |
169 | ||
2e804d03 MR |
170 | emac: ethernet@01c0b000 { |
171 | compatible = "allwinner,sun4i-emac"; | |
172 | reg = <0x01c0b000 0x1000>; | |
173 | interrupts = <0 55 1>; | |
174 | clocks = <&ahb_gates 17>; | |
175 | status = "disabled"; | |
176 | }; | |
177 | ||
178 | mdio@01c0b080 { | |
179 | compatible = "allwinner,sun4i-mdio"; | |
180 | reg = <0x01c0b080 0x14>; | |
181 | status = "disabled"; | |
182 | #address-cells = <1>; | |
183 | #size-cells = <0>; | |
184 | }; | |
185 | ||
17eac031 MR |
186 | pio: pinctrl@01c20800 { |
187 | compatible = "allwinner,sun7i-a20-pinctrl"; | |
188 | reg = <0x01c20800 0x400>; | |
189 | interrupts = <0 28 1>; | |
de7dc935 | 190 | clocks = <&apb0_gates 5>; |
17eac031 MR |
191 | gpio-controller; |
192 | interrupt-controller; | |
193 | #address-cells = <1>; | |
194 | #size-cells = <0>; | |
195 | #gpio-cells = <3>; | |
9f229ba9 MR |
196 | |
197 | uart0_pins_a: uart0@0 { | |
198 | allwinner,pins = "PB22", "PB23"; | |
199 | allwinner,function = "uart0"; | |
200 | allwinner,drive = <0>; | |
201 | allwinner,pull = <0>; | |
202 | }; | |
203 | ||
204 | uart6_pins_a: uart6@0 { | |
205 | allwinner,pins = "PI12", "PI13"; | |
206 | allwinner,function = "uart6"; | |
207 | allwinner,drive = <0>; | |
208 | allwinner,pull = <0>; | |
209 | }; | |
210 | ||
211 | uart7_pins_a: uart7@0 { | |
212 | allwinner,pins = "PI20", "PI21"; | |
213 | allwinner,function = "uart7"; | |
214 | allwinner,drive = <0>; | |
215 | allwinner,pull = <0>; | |
216 | }; | |
756084c5 MR |
217 | |
218 | emac_pins_a: emac0@0 { | |
219 | allwinner,pins = "PA0", "PA1", "PA2", | |
220 | "PA3", "PA4", "PA5", "PA6", | |
221 | "PA7", "PA8", "PA9", "PA10", | |
222 | "PA11", "PA12", "PA13", "PA14", | |
223 | "PA15", "PA16"; | |
224 | allwinner,function = "emac"; | |
225 | allwinner,drive = <0>; | |
226 | allwinner,pull = <0>; | |
227 | }; | |
17eac031 MR |
228 | }; |
229 | ||
4790ecfa MR |
230 | timer@01c20c00 { |
231 | compatible = "allwinner,sun4i-timer"; | |
232 | reg = <0x01c20c00 0x90>; | |
233 | interrupts = <0 22 1>, | |
234 | <0 23 1>, | |
235 | <0 24 1>, | |
236 | <0 25 1>, | |
237 | <0 67 1>, | |
238 | <0 68 1>; | |
239 | clocks = <&osc24M>; | |
240 | }; | |
241 | ||
242 | wdt: watchdog@01c20c90 { | |
243 | compatible = "allwinner,sun4i-wdt"; | |
244 | reg = <0x01c20c90 0x10>; | |
245 | }; | |
246 | ||
2bad969f OS |
247 | sid: eeprom@01c23800 { |
248 | compatible = "allwinner,sun7i-a20-sid"; | |
249 | reg = <0x01c23800 0x200>; | |
250 | }; | |
251 | ||
4790ecfa MR |
252 | uart0: serial@01c28000 { |
253 | compatible = "snps,dw-apb-uart"; | |
254 | reg = <0x01c28000 0x400>; | |
255 | interrupts = <0 1 1>; | |
256 | reg-shift = <2>; | |
257 | reg-io-width = <4>; | |
de7dc935 | 258 | clocks = <&apb1_gates 16>; |
4790ecfa MR |
259 | status = "disabled"; |
260 | }; | |
261 | ||
262 | uart1: serial@01c28400 { | |
263 | compatible = "snps,dw-apb-uart"; | |
264 | reg = <0x01c28400 0x400>; | |
265 | interrupts = <0 2 1>; | |
266 | reg-shift = <2>; | |
267 | reg-io-width = <4>; | |
de7dc935 | 268 | clocks = <&apb1_gates 17>; |
4790ecfa MR |
269 | status = "disabled"; |
270 | }; | |
271 | ||
272 | uart2: serial@01c28800 { | |
273 | compatible = "snps,dw-apb-uart"; | |
274 | reg = <0x01c28800 0x400>; | |
275 | interrupts = <0 3 1>; | |
276 | reg-shift = <2>; | |
277 | reg-io-width = <4>; | |
de7dc935 | 278 | clocks = <&apb1_gates 18>; |
4790ecfa MR |
279 | status = "disabled"; |
280 | }; | |
281 | ||
282 | uart3: serial@01c28c00 { | |
283 | compatible = "snps,dw-apb-uart"; | |
284 | reg = <0x01c28c00 0x400>; | |
285 | interrupts = <0 4 1>; | |
286 | reg-shift = <2>; | |
287 | reg-io-width = <4>; | |
de7dc935 | 288 | clocks = <&apb1_gates 19>; |
4790ecfa MR |
289 | status = "disabled"; |
290 | }; | |
291 | ||
292 | uart4: serial@01c29000 { | |
293 | compatible = "snps,dw-apb-uart"; | |
294 | reg = <0x01c29000 0x400>; | |
295 | interrupts = <0 17 1>; | |
296 | reg-shift = <2>; | |
297 | reg-io-width = <4>; | |
de7dc935 | 298 | clocks = <&apb1_gates 20>; |
4790ecfa MR |
299 | status = "disabled"; |
300 | }; | |
301 | ||
302 | uart5: serial@01c29400 { | |
303 | compatible = "snps,dw-apb-uart"; | |
304 | reg = <0x01c29400 0x400>; | |
305 | interrupts = <0 18 1>; | |
306 | reg-shift = <2>; | |
307 | reg-io-width = <4>; | |
de7dc935 | 308 | clocks = <&apb1_gates 21>; |
4790ecfa MR |
309 | status = "disabled"; |
310 | }; | |
311 | ||
312 | uart6: serial@01c29800 { | |
313 | compatible = "snps,dw-apb-uart"; | |
314 | reg = <0x01c29800 0x400>; | |
315 | interrupts = <0 19 1>; | |
316 | reg-shift = <2>; | |
317 | reg-io-width = <4>; | |
de7dc935 | 318 | clocks = <&apb1_gates 22>; |
4790ecfa MR |
319 | status = "disabled"; |
320 | }; | |
321 | ||
322 | uart7: serial@01c29c00 { | |
323 | compatible = "snps,dw-apb-uart"; | |
324 | reg = <0x01c29c00 0x400>; | |
325 | interrupts = <0 20 1>; | |
326 | reg-shift = <2>; | |
327 | reg-io-width = <4>; | |
de7dc935 | 328 | clocks = <&apb1_gates 23>; |
4790ecfa MR |
329 | status = "disabled"; |
330 | }; | |
331 | ||
428abbb8 MR |
332 | i2c0: i2c@01c2ac00 { |
333 | compatible = "allwinner,sun4i-i2c"; | |
334 | reg = <0x01c2ac00 0x400>; | |
335 | interrupts = <0 7 1>; | |
336 | clocks = <&apb1_gates 0>; | |
337 | clock-frequency = <100000>; | |
338 | status = "disabled"; | |
339 | }; | |
340 | ||
341 | i2c1: i2c@01c2b000 { | |
342 | compatible = "allwinner,sun4i-i2c"; | |
343 | reg = <0x01c2b000 0x400>; | |
344 | interrupts = <0 8 1>; | |
345 | clocks = <&apb1_gates 1>; | |
346 | clock-frequency = <100000>; | |
347 | status = "disabled"; | |
348 | }; | |
349 | ||
350 | i2c2: i2c@01c2b400 { | |
351 | compatible = "allwinner,sun4i-i2c"; | |
352 | reg = <0x01c2b400 0x400>; | |
353 | interrupts = <0 9 1>; | |
354 | clocks = <&apb1_gates 2>; | |
355 | clock-frequency = <100000>; | |
356 | status = "disabled"; | |
357 | }; | |
358 | ||
359 | i2c3: i2c@01c2b800 { | |
360 | compatible = "allwinner,sun4i-i2c"; | |
361 | reg = <0x01c2b800 0x400>; | |
362 | interrupts = <0 88 1>; | |
363 | clocks = <&apb1_gates 3>; | |
364 | clock-frequency = <100000>; | |
365 | status = "disabled"; | |
366 | }; | |
367 | ||
368 | i2c4: i2c@01c2bc00 { | |
369 | compatible = "allwinner,sun4i-i2c"; | |
370 | reg = <0x01c2bc00 0x400>; | |
371 | interrupts = <0 89 1>; | |
372 | clocks = <&apb1_gates 15>; | |
373 | clock-frequency = <100000>; | |
374 | status = "disabled"; | |
375 | }; | |
376 | ||
4790ecfa MR |
377 | gic: interrupt-controller@01c81000 { |
378 | compatible = "arm,cortex-a7-gic", "arm,cortex-a15-gic"; | |
379 | reg = <0x01c81000 0x1000>, | |
380 | <0x01c82000 0x1000>, | |
381 | <0x01c84000 0x2000>, | |
382 | <0x01c86000 0x2000>; | |
383 | interrupt-controller; | |
384 | #interrupt-cells = <3>; | |
385 | interrupts = <1 9 0xf04>; | |
386 | }; | |
387 | }; | |
388 | }; |