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Merge tag 'drm-misc-next-2017-01-30' of git://anongit.freedesktop.org/git/drm-misc...
[linux-block.git] / arch / arm / boot / dts / sun6i-a31.dtsi
CommitLineData
8aed3b31
MR		 1/*
2 * Copyright 2013 Maxime Ripard
3 *
4 * Maxime Ripard <maxime.ripard@free-electrons.com>
5 *
6c3ba724
MR		 6 * This file is dual-licensed: you can use it either under the terms
7 * of the GPL or the X11 license, at your option. Note that this dual
8 * licensing only applies to this file, and not this project as a
9 * whole.
8aed3b31 10 *
5186d83a 11 * a) This file is free software; you can redistribute it and/or
6c3ba724
MR		 12 * modify it under the terms of the GNU General Public License as
13 * published by the Free Software Foundation; either version 2 of the
14 * License, or (at your option) any later version.
15 *
5186d83a 16 * This file is distributed in the hope that it will be useful,
6c3ba724
MR		 17 * but WITHOUT ANY WARRANTY; without even the implied warranty of
18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
19 * GNU General Public License for more details.
20 *
6c3ba724
MR		 21 * Or, alternatively,
22 *
23 * b) Permission is hereby granted, free of charge, to any person
24 * obtaining a copy of this software and associated documentation
25 * files (the "Software"), to deal in the Software without
26 * restriction, including without limitation the rights to use,
27 * copy, modify, merge, publish, distribute, sublicense, and/or
28 * sell copies of the Software, and to permit persons to whom the
29 * Software is furnished to do so, subject to the following
30 * conditions:
31 *
32 * The above copyright notice and this permission notice shall be
33 * included in all copies or substantial portions of the Software.
34 *
35 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
36 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
37 * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
38 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
39 * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
40 * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
41 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
42 * OTHER DEALINGS IN THE SOFTWARE.
8aed3b31
MR		 43 */
44
71455701 45#include "skeleton.dtsi"
8aed3b31 46
19882b84 47#include <dt-bindings/interrupt-controller/arm-gic.h>
eb58b40f 48#include <dt-bindings/thermal/thermal.h>
19882b84 49
78a9f0db 50#include <dt-bindings/clock/sun6i-a31-ccu.h>
092a0c3b 51#include <dt-bindings/pinctrl/sun4i-a10.h>
78a9f0db 52#include <dt-bindings/reset/sun6i-a31-ccu.h>
8aed3b31
MR		 53
54/ {
55 interrupt-parent = <&gic>;
56
54428d40 57 aliases {
e5073fde 58 ethernet0 = &gmac;
54428d40
MR		 59 };
60
e53a8b22
HG		 61 chosen {
62 #address-cells = <1>;
63 #size-cells = <1>;
64 ranges;
65
c0949308 66 simplefb_hdmi: framebuffer@0 {
d8cacaa3
MR		 67 compatible = "allwinner,simple-framebuffer",
68 "simple-framebuffer";
a9f8cda3 69 allwinner,pipeline = "de_be0-lcd0-hdmi";
78a9f0db
CYT		 70 clocks = <&ccu CLK_AHB1_BE0>, <&ccu CLK_AHB1_LCD0>,
71 <&ccu CLK_AHB1_HDMI>, <&ccu CLK_DRAM_BE0>,
72 <&ccu CLK_IEP_DRC0>, <&ccu CLK_BE0>,
73 <&ccu CLK_LCD0_CH1>, <&ccu CLK_HDMI>;
e53a8b22
HG		 74 status = "disabled";
75 };
fd18c7ea 76
c0949308 77 simplefb_lcd: framebuffer@1 {
fd18c7ea
HG		 78 compatible = "allwinner,simple-framebuffer",
79 "simple-framebuffer";
80 allwinner,pipeline = "de_be0-lcd0";
78a9f0db
CYT		 81 clocks = <&ccu CLK_AHB1_BE0>, <&ccu CLK_AHB1_LCD0>,
82 <&ccu CLK_DRAM_BE0>, <&ccu CLK_IEP_DRC0>,
83 <&ccu CLK_BE0>, <&ccu CLK_LCD0_CH0>;
fd18c7ea
HG		 84 status = "disabled";
85 };
e53a8b22 86 };
54428d40 87
121b96cd
MR		 88 timer {
89 compatible = "arm,armv7-timer";
90 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
91 <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
92 <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
93 <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
94 clock-frequency = <24000000>;
95 arm,cpu-registers-not-fw-configured;
e53a8b22 96 };
54428d40 97
8aed3b31 98 cpus {
ce78e353 99 enable-method = "allwinner,sun6i-a31";
8aed3b31
MR		 100 #address-cells = <1>;
101 #size-cells = <0>;
102
3a2bc642 103 cpu0: cpu@0 {
8aed3b31
MR		 104 compatible = "arm,cortex-a7";
105 device_type = "cpu";
106 reg = <0>;
78a9f0db 107 clocks = <&ccu CLK_CPU>;
3a2bc642
CYT		 108 clock-latency = <244144>; /* 8 32k periods */
109 operating-points = <
8358aada 110 /* kHz uV */
3a2bc642 111 1008000 1200000
8358aada
MR		 112 864000 1200000
113 720000 1100000
114 480000 1000000
3a2bc642
CYT		 115 >;
116 #cooling-cells = <2>;
117 cooling-min-level = <0>;
118 cooling-max-level = <3>;
8aed3b31
MR		 119 };
120
121 cpu@1 {
122 compatible = "arm,cortex-a7";
123 device_type = "cpu";
124 reg = <1>;
125 };
126
127 cpu@2 {
128 compatible = "arm,cortex-a7";
129 device_type = "cpu";
130 reg = <2>;
131 };
132
133 cpu@3 {
134 compatible = "arm,cortex-a7";
135 device_type = "cpu";
136 reg = <3>;
137 };
138 };
139
eb58b40f
CYT		 140 thermal-zones {
141 cpu_thermal {
142 /* milliseconds */
143 polling-delay-passive = <250>;
144 polling-delay = <1000>;
145 thermal-sensors = <&rtp>;
146
147 cooling-maps {
148 map0 {
149 trip = <&cpu_alert0>;
150 cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
151 };
152 };
153
154 trips {
155 cpu_alert0: cpu_alert0 {
156 /* milliCelsius */
157 temperature = <70000>;
158 hysteresis = <2000>;
159 type = "passive";
160 };
161
162 cpu_crit: cpu_crit {
163 /* milliCelsius */
164 temperature = <100000>;
165 hysteresis = <2000>;
166 type = "critical";
167 };
168 };
169 };
170 };
171
8aed3b31
MR		 172 memory {
173 reg = <0x40000000 0x80000000>;
174 };
175
b5a10b76
MR		 176 pmu {
177 compatible = "arm,cortex-a7-pmu", "arm,cortex-a15-pmu";
19882b84
MR		 178 interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>,
179 <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>,
180 <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>,
181 <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>;
b5a10b76
MR		 182 };
183
8aed3b31
MR		 184 clocks {
185 #address-cells = <1>;
98096560
MR		 186 #size-cells = <1>;
187 ranges;
8aed3b31 188
98096560 189 osc24M: osc24M {
8aed3b31
MR		 190 #clock-cells = <0>;
191 compatible = "fixed-clock";
192 clock-frequency = <24000000>;
193 };
98096560 194
7b5b2909 195 osc32k: clk@0 {
98096560
MR		 196 #clock-cells = <0>;
197 compatible = "fixed-clock";
198 clock-frequency = <32768>;
7b5b2909 199 clock-output-names = "osc32k";
98096560
MR		 200 };
201
ed29861a 202 /*
d8cacaa3
MR		 203 * The following two are dummy clocks, placeholders
204 * used in the gmac_tx clock. The gmac driver will
205 * choose one parent depending on the PHY interface
206 * mode, using clk_set_rate auto-reparenting.
207 *
208 * The actual TX clock rate is not controlled by the
209 * gmac_tx clock.
ed29861a
CYT		 210 */
211 mii_phy_tx_clk: clk@1 {
212 #clock-cells = <0>;
213 compatible = "fixed-clock";
214 clock-frequency = <25000000>;
215 clock-output-names = "mii_phy_tx";
216 };
217
218 gmac_int_tx_clk: clk@2 {
219 #clock-cells = <0>;
220 compatible = "fixed-clock";
221 clock-frequency = <125000000>;
222 clock-output-names = "gmac_int_tx";
223 };
224
225 gmac_tx_clk: clk@01c200d0 {
226 #clock-cells = <0>;
227 compatible = "allwinner,sun7i-a20-gmac-clk";
228 reg = <0x01c200d0 0x4>;
229 clocks = <&mii_phy_tx_clk>, <&gmac_int_tx_clk>;
230 clock-output-names = "gmac_tx";
231 };
8aed3b31
MR		 232 };
233
6d0e5b70
CYT		 234 de: display-engine {
235 compatible = "allwinner,sun6i-a31-display-engine";
236 allwinner,pipelines = <&fe0>;
205ac7b3 237 status = "disabled";
6d0e5b70
CYT		 238 };
239
8aed3b31
MR		 240 soc@01c00000 {
241 compatible = "simple-bus";
242 #address-cells = <1>;
243 #size-cells = <1>;
244 ranges;
245
d2d878c4
MR		 246 dma: dma-controller@01c02000 {
247 compatible = "allwinner,sun6i-a31-dma";
248 reg = <0x01c02000 0x1000>;
19882b84 249 interrupts = <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>;
78a9f0db
CYT		 250 clocks = <&ccu CLK_AHB1_DMA>;
251 resets = <&ccu RST_AHB1_DMA>;
d2d878c4
MR		 252 #dma-cells = <1>;
253 };
254
6d0e5b70
CYT		 255 tcon0: lcd-controller@01c0c000 {
256 compatible = "allwinner,sun6i-a31-tcon";
257 reg = <0x01c0c000 0x1000>;
258 interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
259 resets = <&ccu RST_AHB1_LCD0>;
260 reset-names = "lcd";
261 clocks = <&ccu CLK_AHB1_LCD0>,
262 <&ccu CLK_LCD0_CH0>,
263 <&ccu CLK_LCD0_CH1>;
264 clock-names = "ahb",
265 "tcon-ch0",
266 "tcon-ch1";
267 clock-output-names = "tcon0-pixel-clock";
268 status = "disabled";
269
270 ports {
271 #address-cells = <1>;
272 #size-cells = <0>;
273
274 tcon0_in: port@0 {
275 #address-cells = <1>;
276 #size-cells = <0>;
277 reg = <0>;
278
279 tcon0_in_drc0: endpoint@0 {
280 reg = <0>;
281 remote-endpoint = <&drc0_out_tcon0>;
282 };
283 };
284
285 tcon0_out: port@1 {
286 #address-cells = <1>;
287 #size-cells = <0>;
288 reg = <1>;
289 };
290 };
291 };
292
5b753f0e 293 mmc0: mmc@01c0f000 {
57af711d 294 compatible = "allwinner,sun7i-a20-mmc";
5b753f0e 295 reg = <0x01c0f000 0x1000>;
78a9f0db
CYT		 296 clocks = <&ccu CLK_AHB1_MMC0>,
297 <&ccu CLK_MMC0>,
298 <&ccu CLK_MMC0_OUTPUT>,
299 <&ccu CLK_MMC0_SAMPLE>;
d8c3a392
MR		 300 clock-names = "ahb",
301 "mmc",
302 "output",
303 "sample";
78a9f0db 304 resets = <&ccu RST_AHB1_MMC0>;
5b753f0e 305 reset-names = "ahb";
19882b84 306 interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>;
5b753f0e 307 status = "disabled";
4c1bb9c3
HG		 308 #address-cells = <1>;
309 #size-cells = <0>;
5b753f0e
HG		 310 };
311
312 mmc1: mmc@01c10000 {
57af711d 313 compatible = "allwinner,sun7i-a20-mmc";
5b753f0e 314 reg = <0x01c10000 0x1000>;
78a9f0db
CYT		 315 clocks = <&ccu CLK_AHB1_MMC1>,
316 <&ccu CLK_MMC1>,
317 <&ccu CLK_MMC1_OUTPUT>,
318 <&ccu CLK_MMC1_SAMPLE>;
d8c3a392
MR		 319 clock-names = "ahb",
320 "mmc",
321 "output",
322 "sample";
78a9f0db 323 resets = <&ccu RST_AHB1_MMC1>;
5b753f0e 324 reset-names = "ahb";
19882b84 325 interrupts = <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>;
5b753f0e 326 status = "disabled";
4c1bb9c3
HG		 327 #address-cells = <1>;
328 #size-cells = <0>;
5b753f0e
HG		 329 };
330
331 mmc2: mmc@01c11000 {
57af711d 332 compatible = "allwinner,sun7i-a20-mmc";
5b753f0e 333 reg = <0x01c11000 0x1000>;
78a9f0db
CYT		 334 clocks = <&ccu CLK_AHB1_MMC2>,
335 <&ccu CLK_MMC2>,
336 <&ccu CLK_MMC2_OUTPUT>,
337 <&ccu CLK_MMC2_SAMPLE>;
d8c3a392
MR		 338 clock-names = "ahb",
339 "mmc",
340 "output",
341 "sample";
78a9f0db 342 resets = <&ccu RST_AHB1_MMC2>;
5b753f0e 343 reset-names = "ahb";
19882b84 344 interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>;
5b753f0e 345 status = "disabled";
4c1bb9c3
HG		 346 #address-cells = <1>;
347 #size-cells = <0>;
5b753f0e
HG		 348 };
349
350 mmc3: mmc@01c12000 {
57af711d 351 compatible = "allwinner,sun7i-a20-mmc";
5b753f0e 352 reg = <0x01c12000 0x1000>;
78a9f0db
CYT		 353 clocks = <&ccu CLK_AHB1_MMC3>,
354 <&ccu CLK_MMC3>,
355 <&ccu CLK_MMC3_OUTPUT>,
356 <&ccu CLK_MMC3_SAMPLE>;
d8c3a392
MR		 357 clock-names = "ahb",
358 "mmc",
359 "output",
360 "sample";
78a9f0db 361 resets = <&ccu RST_AHB1_MMC3>;
5b753f0e 362 reset-names = "ahb";
19882b84 363 interrupts = <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>;
5b753f0e 364 status = "disabled";
4c1bb9c3
HG		 365 #address-cells = <1>;
366 #size-cells = <0>;
5b753f0e
HG		 367 };
368
d208eaf2
HG		 369 usb_otg: usb@01c19000 {
370 compatible = "allwinner,sun6i-a31-musb";
371 reg = <0x01c19000 0x0400>;
78a9f0db
CYT		 372 clocks = <&ccu CLK_AHB1_OTG>;
373 resets = <&ccu RST_AHB1_OTG>;
d208eaf2
HG		 374 interrupts = <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>;
375 interrupt-names = "mc";
376 phys = <&usbphy 0>;
377 phy-names = "usb";
378 extcon = <&usbphy 0>;
379 status = "disabled";
380 };
381
ef964085
MR		 382 usbphy: phy@01c19400 {
383 compatible = "allwinner,sun6i-a31-usb-phy";
384 reg = <0x01c19400 0x10>,
385 <0x01c1a800 0x4>,
386 <0x01c1b800 0x4>;
387 reg-names = "phy_ctrl",
388 "pmu1",
389 "pmu2";
78a9f0db
CYT		 390 clocks = <&ccu CLK_USB_PHY0>,
391 <&ccu CLK_USB_PHY1>,
392 <&ccu CLK_USB_PHY2>;
ef964085
MR		 393 clock-names = "usb0_phy",
394 "usb1_phy",
395 "usb2_phy";
78a9f0db
CYT		 396 resets = <&ccu RST_USB_PHY0>,
397 <&ccu RST_USB_PHY1>,
398 <&ccu RST_USB_PHY2>;
ef964085
MR		 399 reset-names = "usb0_reset",
400 "usb1_reset",
401 "usb2_reset";
402 status = "disabled";
403 #phy-cells = <1>;
404 };
405
406 ehci0: usb@01c1a000 {
407 compatible = "allwinner,sun6i-a31-ehci", "generic-ehci";
408 reg = <0x01c1a000 0x100>;
19882b84 409 interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>;
78a9f0db
CYT		 410 clocks = <&ccu CLK_AHB1_EHCI0>;
411 resets = <&ccu RST_AHB1_EHCI0>;
ef964085
MR		 412 phys = <&usbphy 1>;
413 phy-names = "usb";
414 status = "disabled";
415 };
416
417 ohci0: usb@01c1a400 {
418 compatible = "allwinner,sun6i-a31-ohci", "generic-ohci";
419 reg = <0x01c1a400 0x100>;
19882b84 420 interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>;
78a9f0db
CYT		 421 clocks = <&ccu CLK_AHB1_OHCI0>, <&ccu CLK_USB_OHCI0>;
422 resets = <&ccu RST_AHB1_OHCI0>;
ef964085
MR		 423 phys = <&usbphy 1>;
424 phy-names = "usb";
425 status = "disabled";
426 };
427
428 ehci1: usb@01c1b000 {
429 compatible = "allwinner,sun6i-a31-ehci", "generic-ehci";
430 reg = <0x01c1b000 0x100>;
19882b84 431 interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>;
78a9f0db
CYT		 432 clocks = <&ccu CLK_AHB1_EHCI1>;
433 resets = <&ccu RST_AHB1_EHCI1>;
ef964085
MR		 434 phys = <&usbphy 2>;
435 phy-names = "usb";
436 status = "disabled";
437 };
438
439 ohci1: usb@01c1b400 {
440 compatible = "allwinner,sun6i-a31-ohci", "generic-ohci";
441 reg = <0x01c1b400 0x100>;
19882b84 442 interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>;
78a9f0db
CYT		 443 clocks = <&ccu CLK_AHB1_OHCI1>, <&ccu CLK_USB_OHCI1>;
444 resets = <&ccu RST_AHB1_OHCI1>;
ef964085
MR		 445 phys = <&usbphy 2>;
446 phy-names = "usb";
447 status = "disabled";
448 };
449
b294ebbc 450 ohci2: usb@01c1c400 {
ef964085
MR		 451 compatible = "allwinner,sun6i-a31-ohci", "generic-ohci";
452 reg = <0x01c1c400 0x100>;
19882b84 453 interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>;
78a9f0db
CYT		 454 clocks = <&ccu CLK_AHB1_OHCI2>, <&ccu CLK_USB_OHCI2>;
455 resets = <&ccu RST_AHB1_OHCI2>;
ef964085
MR		 456 status = "disabled";
457 };
458
78a9f0db
CYT		 459 ccu: clock@01c20000 {
460 compatible = "allwinner,sun6i-a31-ccu";
461 reg = <0x01c20000 0x400>;
462 clocks = <&osc24M>, <&osc32k>;
463 clock-names = "hosc", "losc";
464 #clock-cells = <1>;
465 #reset-cells = <1>;
466 };
467
140e1721
MR		 468 pio: pinctrl@01c20800 {
469 compatible = "allwinner,sun6i-a31-pinctrl";
470 reg = <0x01c20800 0x400>;
19882b84
MR		 471 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>,
472 <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>,
473 <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>,
474 <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
be7bc6b9
MR		 475 clocks = <&ccu CLK_APB1_PIO>, <&osc24M>, <&osc32k>;
476 clock-names = "apb", "hosc", "losc";
140e1721
MR		 477 gpio-controller;
478 interrupt-controller;
b03e0816 479 #interrupt-cells = <3>;
140e1721 480 #gpio-cells = <3>;
ab4238cd 481
dc0aea38
CYT		 482 gmac_pins_gmii_a: gmac_gmii@0 {
483 allwinner,pins = "PA0", "PA1", "PA2", "PA3",
484 "PA4", "PA5", "PA6", "PA7",
485 "PA8", "PA9", "PA10", "PA11",
486 "PA12", "PA13", "PA14", "PA15",
487 "PA16", "PA17", "PA18", "PA19",
488 "PA20", "PA21", "PA22", "PA23",
489 "PA24", "PA25", "PA26", "PA27";
490 allwinner,function = "gmac";
491 /*
492 * data lines in GMII mode run at 125MHz and
493 * might need a higher signal drive strength
494 */
495 allwinner,drive = <SUN4I_PINCTRL_30_MA>;
496 allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
497 };
498
499 gmac_pins_mii_a: gmac_mii@0 {
500 allwinner,pins = "PA0", "PA1", "PA2", "PA3",
501 "PA8", "PA9", "PA11",
502 "PA12", "PA13", "PA14", "PA19",
503 "PA20", "PA21", "PA22", "PA23",
504 "PA24", "PA26", "PA27";
505 allwinner,function = "gmac";
092a0c3b
MR		 506 allwinner,drive = <SUN4I_PINCTRL_10_MA>;
507 allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
ab4238cd 508 };
8be188b8 509
dc0aea38
CYT		 510 gmac_pins_rgmii_a: gmac_rgmii@0 {
511 allwinner,pins = "PA0", "PA1", "PA2", "PA3",
512 "PA9", "PA10", "PA11",
513 "PA12", "PA13", "PA14", "PA19",
514 "PA20", "PA25", "PA26", "PA27";
515 allwinner,function = "gmac";
516 /*
517 * data lines in RGMII mode use DDR mode
518 * and need a higher signal drive strength
519 */
520 allwinner,drive = <SUN4I_PINCTRL_40_MA>;
521 allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
522 };
523
8be188b8
MR		 524 i2c0_pins_a: i2c0@0 {
525 allwinner,pins = "PH14", "PH15";
526 allwinner,function = "i2c0";
092a0c3b
MR		 527 allwinner,drive = <SUN4I_PINCTRL_10_MA>;
528 allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
8be188b8
MR		 529 };
530
531 i2c1_pins_a: i2c1@0 {
532 allwinner,pins = "PH16", "PH17";
533 allwinner,function = "i2c1";
092a0c3b
MR		 534 allwinner,drive = <SUN4I_PINCTRL_10_MA>;
535 allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
8be188b8
MR		 536 };
537
538 i2c2_pins_a: i2c2@0 {
539 allwinner,pins = "PH18", "PH19";
540 allwinner,function = "i2c2";
092a0c3b
MR		 541 allwinner,drive = <SUN4I_PINCTRL_10_MA>;
542 allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
8be188b8 543 };
9797eb83 544
0ff8219f
CYT		 545 lcd0_rgb888_pins: lcd0_rgb888 {
546 allwinner,pins = "PD0", "PD1", "PD2", "PD3",
547 "PD4", "PD5", "PD6", "PD7",
548 "PD8", "PD9", "PD10", "PD11",
549 "PD12", "PD13", "PD14", "PD15",
550 "PD16", "PD17", "PD18", "PD19",
551 "PD20", "PD21", "PD22", "PD23",
552 "PD24", "PD25", "PD26", "PD27";
553 allwinner,function = "lcd0";
554 allwinner,drive = <SUN4I_PINCTRL_10_MA>;
555 allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
556 };
557
9797eb83 558 mmc0_pins_a: mmc0@0 {
d8cacaa3
MR		 559 allwinner,pins = "PF0", "PF1", "PF2",
560 "PF3", "PF4", "PF5";
9797eb83 561 allwinner,function = "mmc0";
092a0c3b
MR		 562 allwinner,drive = <SUN4I_PINCTRL_30_MA>;
563 allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
9797eb83 564 };
ee39a3e3 565
878c4ded
CYT		 566 mmc1_pins_a: mmc1@0 {
567 allwinner,pins = "PG0", "PG1", "PG2", "PG3",
568 "PG4", "PG5";
569 allwinner,function = "mmc1";
570 allwinner,drive = <SUN4I_PINCTRL_30_MA>;
571 allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
572 };
573
5edab366
HG		 574 mmc2_pins_a: mmc2@0 {
575 allwinner,pins = "PC6", "PC7", "PC8", "PC9",
576 "PC10", "PC11";
577 allwinner,function = "mmc2";
578 allwinner,drive = <SUN4I_PINCTRL_30_MA>;
579 allwinner,pull = <SUN4I_PINCTRL_PULL_UP>;
580 };
581
582 mmc2_8bit_emmc_pins: mmc2@1 {
4917c46c
CYT		 583 allwinner,pins = "PC6", "PC7", "PC8", "PC9",
584 "PC10", "PC11", "PC12",
585 "PC13", "PC14", "PC15",
586 "PC24";
587 allwinner,function = "mmc2";
588 allwinner,drive = <SUN4I_PINCTRL_30_MA>;
589 allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
590 };
591
a22f8b22
CYT		 592 mmc3_8bit_emmc_pins: mmc3@1 {
593 allwinner,pins = "PC6", "PC7", "PC8", "PC9",
594 "PC10", "PC11", "PC12",
595 "PC13", "PC14", "PC15",
596 "PC24";
597 allwinner,function = "mmc3";
598 allwinner,drive = <SUN4I_PINCTRL_40_MA>;
599 allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
600 };
601
dc0aea38
CYT		 602 uart0_pins_a: uart0@0 {
603 allwinner,pins = "PH20", "PH21";
604 allwinner,function = "uart0";
092a0c3b
MR		 605 allwinner,drive = <SUN4I_PINCTRL_10_MA>;
606 allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
ee39a3e3 607 };
140e1721
MR		 608 };
609
8aed3b31 610 timer@01c20c00 {
b4f26440 611 compatible = "allwinner,sun4i-a10-timer";
8aed3b31 612 reg = <0x01c20c00 0xa0>;
19882b84
MR		 613 interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>,
614 <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>,
615 <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>,
616 <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>,
617 <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>;
98096560 618 clocks = <&osc24M>;
8aed3b31
MR		 619 };
620
621 wdt1: watchdog@01c20ca0 {
ca5d04d9 622 compatible = "allwinner,sun6i-a31-wdt";
8aed3b31
MR		 623 reg = <0x01c20ca0 0x20>;
624 };
61d2595c
CYT		 625
626 lradc: lradc@01c22800 {
627 compatible = "allwinner,sun4i-a10-lradc-keys";
628 reg = <0x01c22800 0x100>;
629 interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>;
630 status = "disabled";
631 };
8aed3b31 632
4ec45cd3
CYT		 633 rtp: rtp@01c25000 {
634 compatible = "allwinner,sun6i-a31-ts";
635 reg = <0x01c25000 0x100>;
636 interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>;
637 #thermal-sensor-cells = <0>;
638 };
639
8aed3b31
MR		 640 uart0: serial@01c28000 {
641 compatible = "snps,dw-apb-uart";
642 reg = <0x01c28000 0x400>;
19882b84 643 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>;
8aed3b31
MR		 644 reg-shift = <2>;
645 reg-io-width = <4>;
78a9f0db
CYT		 646 clocks = <&ccu CLK_APB2_UART0>;
647 resets = <&ccu RST_APB2_UART0>;
d2d878c4
MR		 648 dmas = <&dma 6>, <&dma 6>;
649 dma-names = "rx", "tx";
8aed3b31
MR		 650 status = "disabled";
651 };
652
653 uart1: serial@01c28400 {
654 compatible = "snps,dw-apb-uart";
655 reg = <0x01c28400 0x400>;
19882b84 656 interrupts = <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>;
8aed3b31
MR		 657 reg-shift = <2>;
658 reg-io-width = <4>;
78a9f0db
CYT		 659 clocks = <&ccu CLK_APB2_UART1>;
660 resets = <&ccu RST_APB2_UART1>;
d2d878c4
MR		 661 dmas = <&dma 7>, <&dma 7>;
662 dma-names = "rx", "tx";
8aed3b31
MR		 663 status = "disabled";
664 };
665
666 uart2: serial@01c28800 {
667 compatible = "snps,dw-apb-uart";
668 reg = <0x01c28800 0x400>;
19882b84 669 interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>;
8aed3b31
MR		 670 reg-shift = <2>;
671 reg-io-width = <4>;
78a9f0db
CYT		 672 clocks = <&ccu CLK_APB2_UART2>;
673 resets = <&ccu RST_APB2_UART2>;
d2d878c4
MR		 674 dmas = <&dma 8>, <&dma 8>;
675 dma-names = "rx", "tx";
8aed3b31
MR		 676 status = "disabled";
677 };
678
679 uart3: serial@01c28c00 {
680 compatible = "snps,dw-apb-uart";
681 reg = <0x01c28c00 0x400>;
19882b84 682 interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>;
8aed3b31
MR		 683 reg-shift = <2>;
684 reg-io-width = <4>;
78a9f0db
CYT		 685 clocks = <&ccu CLK_APB2_UART3>;
686 resets = <&ccu RST_APB2_UART3>;
d2d878c4
MR		 687 dmas = <&dma 9>, <&dma 9>;
688 dma-names = "rx", "tx";
8aed3b31
MR		 689 status = "disabled";
690 };
691
692 uart4: serial@01c29000 {
693 compatible = "snps,dw-apb-uart";
694 reg = <0x01c29000 0x400>;
19882b84 695 interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>;
8aed3b31
MR		 696 reg-shift = <2>;
697 reg-io-width = <4>;
78a9f0db
CYT		 698 clocks = <&ccu CLK_APB2_UART4>;
699 resets = <&ccu RST_APB2_UART4>;
d2d878c4
MR		 700 dmas = <&dma 10>, <&dma 10>;
701 dma-names = "rx", "tx";
8aed3b31
MR		 702 status = "disabled";
703 };
704
705 uart5: serial@01c29400 {
706 compatible = "snps,dw-apb-uart";
707 reg = <0x01c29400 0x400>;
19882b84 708 interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>;
8aed3b31
MR		 709 reg-shift = <2>;
710 reg-io-width = <4>;
78a9f0db
CYT		 711 clocks = <&ccu CLK_APB2_UART5>;
712 resets = <&ccu RST_APB2_UART5>;
d2d878c4
MR		 713 dmas = <&dma 22>, <&dma 22>;
714 dma-names = "rx", "tx";
8aed3b31
MR		 715 status = "disabled";
716 };
717
96c7cc9b
MR		 718 i2c0: i2c@01c2ac00 {
719 compatible = "allwinner,sun6i-a31-i2c";
720 reg = <0x01c2ac00 0x400>;
19882b84 721 interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
78a9f0db
CYT		 722 clocks = <&ccu CLK_APB2_I2C0>;
723 resets = <&ccu RST_APB2_I2C0>;
96c7cc9b 724 status = "disabled";
495bccf3
CYT		 725 #address-cells = <1>;
726 #size-cells = <0>;
96c7cc9b
MR		 727 };
728
729 i2c1: i2c@01c2b000 {
730 compatible = "allwinner,sun6i-a31-i2c";
731 reg = <0x01c2b000 0x400>;
19882b84 732 interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
78a9f0db
CYT		 733 clocks = <&ccu CLK_APB2_I2C1>;
734 resets = <&ccu RST_APB2_I2C1>;
96c7cc9b 735 status = "disabled";
495bccf3
CYT		 736 #address-cells = <1>;
737 #size-cells = <0>;
96c7cc9b
MR		 738 };
739
740 i2c2: i2c@01c2b400 {
741 compatible = "allwinner,sun6i-a31-i2c";
742 reg = <0x01c2b400 0x400>;
19882b84 743 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
78a9f0db
CYT		 744 clocks = <&ccu CLK_APB2_I2C2>;
745 resets = <&ccu RST_APB2_I2C2>;
96c7cc9b 746 status = "disabled";
495bccf3
CYT		 747 #address-cells = <1>;
748 #size-cells = <0>;
96c7cc9b
MR		 749 };
750
751 i2c3: i2c@01c2b800 {
752 compatible = "allwinner,sun6i-a31-i2c";
753 reg = <0x01c2b800 0x400>;
19882b84 754 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
78a9f0db
CYT		 755 clocks = <&ccu CLK_APB2_I2C3>;
756 resets = <&ccu RST_APB2_I2C3>;
96c7cc9b 757 status = "disabled";
495bccf3
CYT		 758 #address-cells = <1>;
759 #size-cells = <0>;
96c7cc9b
MR		 760 };
761
3dca65f8
CYT		 762 gmac: ethernet@01c30000 {
763 compatible = "allwinner,sun7i-a20-gmac";
764 reg = <0x01c30000 0x1054>;
19882b84 765 interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>;
3dca65f8 766 interrupt-names = "macirq";
78a9f0db 767 clocks = <&ccu CLK_AHB1_EMAC>, <&gmac_tx_clk>;
3dca65f8 768 clock-names = "stmmaceth", "allwinner_gmac_tx";
78a9f0db 769 resets = <&ccu RST_AHB1_EMAC>;
3dca65f8
CYT		 770 reset-names = "stmmaceth";
771 snps,pbl = <2>;
772 snps,fixed-burst;
773 snps,force_sf_dma_mode;
774 status = "disabled";
775 #address-cells = <1>;
776 #size-cells = <0>;
777 };
778
14fee74c
CYT		 779 crypto: crypto-engine@01c15000 {
780 compatible = "allwinner,sun4i-a10-crypto";
781 reg = <0x01c15000 0x1000>;
782 interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>;
78a9f0db 783 clocks = <&ccu CLK_AHB1_SS>, <&ccu CLK_SS>;
14fee74c 784 clock-names = "ahb", "mod";
78a9f0db 785 resets = <&ccu RST_AHB1_SS>;
14fee74c
CYT		 786 reset-names = "ahb";
787 };
788
94a160c6
CYT		 789 codec: codec@01c22c00 {
790 #sound-dai-cells = <0>;
791 compatible = "allwinner,sun6i-a31-codec";
792 reg = <0x01c22c00 0x400>;
793 interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>;
794 clocks = <&ccu CLK_APB1_CODEC>, <&ccu CLK_CODEC>;
795 clock-names = "apb", "codec";
796 resets = <&ccu RST_APB1_CODEC>;
797 dmas = <&dma 15>, <&dma 15>;
798 dma-names = "rx", "tx";
799 status = "disabled";
800 };
801
8cffcb0c 802 timer@01c60000 {
d8cacaa3
MR		 803 compatible = "allwinner,sun6i-a31-hstimer",
804 "allwinner,sun7i-a20-hstimer";
8cffcb0c 805 reg = <0x01c60000 0x1000>;
19882b84
MR		 806 interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>,
807 <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>,
808 <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>,
809 <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>;
78a9f0db
CYT		 810 clocks = <&ccu CLK_AHB1_HSTIMER>;
811 resets = <&ccu RST_AHB1_HSTIMER>;
8cffcb0c
MR		 812 };
813
0d6efe33
MR		 814 spi0: spi@01c68000 {
815 compatible = "allwinner,sun6i-a31-spi";
816 reg = <0x01c68000 0x1000>;
19882b84 817 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>;
78a9f0db 818 clocks = <&ccu CLK_AHB1_SPI0>, <&ccu CLK_SPI0>;
0d6efe33 819 clock-names = "ahb", "mod";
d2d878c4
MR		 820 dmas = <&dma 23>, <&dma 23>;
821 dma-names = "rx", "tx";
78a9f0db 822 resets = <&ccu RST_AHB1_SPI0>;
0d6efe33
MR		 823 status = "disabled";
824 };
825
826 spi1: spi@01c69000 {
827 compatible = "allwinner,sun6i-a31-spi";
828 reg = <0x01c69000 0x1000>;
19882b84 829 interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>;
78a9f0db 830 clocks = <&ccu CLK_AHB1_SPI1>, <&ccu CLK_SPI1>;
0d6efe33 831 clock-names = "ahb", "mod";
d2d878c4
MR		 832 dmas = <&dma 24>, <&dma 24>;
833 dma-names = "rx", "tx";
78a9f0db 834 resets = <&ccu RST_AHB1_SPI1>;
0d6efe33
MR		 835 status = "disabled";
836 };
837
838 spi2: spi@01c6a000 {
839 compatible = "allwinner,sun6i-a31-spi";
840 reg = <0x01c6a000 0x1000>;
19882b84 841 interrupts = <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>;
78a9f0db 842 clocks = <&ccu CLK_AHB1_SPI2>, <&ccu CLK_SPI2>;
0d6efe33 843 clock-names = "ahb", "mod";
d2d878c4
MR		 844 dmas = <&dma 25>, <&dma 25>;
845 dma-names = "rx", "tx";
78a9f0db 846 resets = <&ccu RST_AHB1_SPI2>;
0d6efe33
MR		 847 status = "disabled";
848 };
849
850 spi3: spi@01c6b000 {
851 compatible = "allwinner,sun6i-a31-spi";
852 reg = <0x01c6b000 0x1000>;
19882b84 853 interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>;
78a9f0db 854 clocks = <&ccu CLK_AHB1_SPI3>, <&ccu CLK_SPI3>;
0d6efe33 855 clock-names = "ahb", "mod";
d2d878c4
MR		 856 dmas = <&dma 26>, <&dma 26>;
857 dma-names = "rx", "tx";
78a9f0db 858 resets = <&ccu RST_AHB1_SPI3>;
0d6efe33
MR		 859 status = "disabled";
860 };
861
8aed3b31
MR		 862 gic: interrupt-controller@01c81000 {
863 compatible = "arm,cortex-a7-gic", "arm,cortex-a15-gic";
864 reg = <0x01c81000 0x1000>,
865 <0x01c82000 0x1000>,
866 <0x01c84000 0x2000>,
867 <0x01c86000 0x2000>;
868 interrupt-controller;
869 #interrupt-cells = <3>;
19882b84 870 interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
8aed3b31 871 };
81ee429f 872
6d0e5b70
CYT		 873 fe0: display-frontend@01e00000 {
874 compatible = "allwinner,sun6i-a31-display-frontend";
875 reg = <0x01e00000 0x20000>;
876 interrupts = <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>;
877 clocks = <&ccu CLK_AHB1_FE0>, <&ccu CLK_FE0>,
878 <&ccu CLK_DRAM_FE0>;
879 clock-names = "ahb", "mod",
880 "ram";
881 resets = <&ccu RST_AHB1_FE0>;
882
883 ports {
884 #address-cells = <1>;
885 #size-cells = <0>;
886
887 fe0_out: port@1 {
888 #address-cells = <1>;
889 #size-cells = <0>;
890 reg = <1>;
891
892 fe0_out_be0: endpoint@0 {
893 reg = <0>;
894 remote-endpoint = <&be0_in_fe0>;
895 };
896 };
897 };
898 };
899
900 be0: display-backend@01e60000 {
901 compatible = "allwinner,sun6i-a31-display-backend";
902 reg = <0x01e60000 0x10000>;
903 interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>;
904 clocks = <&ccu CLK_AHB1_BE0>, <&ccu CLK_BE0>,
905 <&ccu CLK_DRAM_BE0>;
906 clock-names = "ahb", "mod",
907 "ram";
908 resets = <&ccu RST_AHB1_BE0>;
909
910 assigned-clocks = <&ccu CLK_BE0>;
911 assigned-clock-rates = <300000000>;
912
913 ports {
914 #address-cells = <1>;
915 #size-cells = <0>;
916
917 be0_in: port@0 {
918 #address-cells = <1>;
919 #size-cells = <0>;
920 reg = <0>;
921
922 be0_in_fe0: endpoint@0 {
923 reg = <0>;
924 remote-endpoint = <&fe0_out_be0>;
925 };
926 };
927
928 be0_out: port@1 {
929 #address-cells = <1>;
930 #size-cells = <0>;
931 reg = <1>;
932
933 be0_out_drc0: endpoint@0 {
934 reg = <0>;
935 remote-endpoint = <&drc0_in_be0>;
936 };
937 };
938 };
939 };
940
941 drc0: drc@01e70000 {
942 compatible = "allwinner,sun6i-a31-drc";
943 reg = <0x01e70000 0x10000>;
944 interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>;
945 clocks = <&ccu CLK_AHB1_DRC0>, <&ccu CLK_IEP_DRC0>,
946 <&ccu CLK_DRAM_DRC0>;
947 clock-names = "ahb", "mod",
948 "ram";
949 resets = <&ccu RST_AHB1_DRC0>;
950
951 assigned-clocks = <&ccu CLK_IEP_DRC0>;
952 assigned-clock-rates = <300000000>;
953
954 ports {
955 #address-cells = <1>;
956 #size-cells = <0>;
957
958 drc0_in: port@0 {
959 #address-cells = <1>;
960 #size-cells = <0>;
961 reg = <0>;
962
963 drc0_in_be0: endpoint@0 {
964 reg = <0>;
965 remote-endpoint = <&be0_out_drc0>;
966 };
967 };
968
969 drc0_out: port@1 {
970 #address-cells = <1>;
971 #size-cells = <0>;
972 reg = <1>;
973
974 drc0_out_tcon0: endpoint@0 {
975 reg = <0>;
976 remote-endpoint = <&tcon0_in_drc0>;
977 };
978 };
979 };
980 };
981
5e700435
CYT		 982 rtc: rtc@01f00000 {
983 compatible = "allwinner,sun6i-a31-rtc";
984 reg = <0x01f00000 0x54>;
19882b84
MR		 985 interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>,
986 <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>;
5e700435
CYT		 987 };
988
28240d27
MR		 989 nmi_intc: interrupt-controller@01f00c0c {
990 compatible = "allwinner,sun6i-a31-sc-nmi";
991 interrupt-controller;
992 #interrupt-cells = <2>;
993 reg = <0x01f00c0c 0x38>;
19882b84 994 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
28240d27
MR		 995 };
996
a42ea603
HG		 997 prcm@01f01400 {
998 compatible = "allwinner,sun6i-a31-prcm";
999 reg = <0x01f01400 0x200>;
cc08f5e9
BB		 1000
1001 ar100: ar100_clk {
1002 compatible = "allwinner,sun6i-a31-ar100-clk";
1003 #clock-cells = <0>;
78a9f0db
CYT		 1004 clocks = <&osc32k>, <&osc24M>,
1005 <&ccu CLK_PLL_PERIPH>,
1006 <&ccu CLK_PLL_PERIPH>;
cc08f5e9
BB		 1007 clock-output-names = "ar100";
1008 };
1009
1010 ahb0: ahb0_clk {
1011 compatible = "fixed-factor-clock";
1012 #clock-cells = <0>;
1013 clock-div = <1>;
1014 clock-mult = <1>;
1015 clocks = <&ar100>;
1016 clock-output-names = "ahb0";
1017 };
1018
1019 apb0: apb0_clk {
1020 compatible = "allwinner,sun6i-a31-apb0-clk";
1021 #clock-cells = <0>;
1022 clocks = <&ahb0>;
1023 clock-output-names = "apb0";
1024 };
1025
1026 apb0_gates: apb0_gates_clk {
1027 compatible = "allwinner,sun6i-a31-apb0-gates-clk";
1028 #clock-cells = <1>;
1029 clocks = <&apb0>;
1030 clock-output-names = "apb0_pio", "apb0_ir",
1031 "apb0_timer", "apb0_p2wi",
1032 "apb0_uart", "apb0_1wire",
1033 "apb0_i2c";
1034 };
1035
9b5c6e06
HG		 1036 ir_clk: ir_clk {
1037 #clock-cells = <0>;
1038 compatible = "allwinner,sun4i-a10-mod0-clk";
1039 clocks = <&osc32k>, <&osc24M>;
1040 clock-output-names = "ir";
1041 };
1042
cc08f5e9
BB		 1043 apb0_rst: apb0_rst {
1044 compatible = "allwinner,sun6i-a31-clock-reset";
1045 #reset-cells = <1>;
1046 };
a42ea603
HG		 1047 };
1048
81ee429f
MR		 1049 cpucfg@01f01c00 {
1050 compatible = "allwinner,sun6i-a31-cpuconfig";
1051 reg = <0x01f01c00 0x300>;
1052 };
209394ae 1053
4ac367b4
HG		 1054 ir: ir@01f02000 {
1055 compatible = "allwinner,sun5i-a13-ir";
1056 clocks = <&apb0_gates 1>, <&ir_clk>;
1057 clock-names = "apb", "ir";
1058 resets = <&apb0_rst 1>;
19882b84 1059 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
4ac367b4
HG		 1060 reg = <0x01f02000 0x40>;
1061 status = "disabled";
1062 };
1063
209394ae
BB		 1064 r_pio: pinctrl@01f02c00 {
1065 compatible = "allwinner,sun6i-a31-r-pinctrl";
1066 reg = <0x01f02c00 0x400>;
19882b84
MR		 1067 interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>,
1068 <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>;
be7bc6b9
MR		 1069 clocks = <&apb0_gates 0>, <&osc24M>, <&osc32k>;
1070 clock-names = "apb", "hosc", "losc";
209394ae
BB		 1071 resets = <&apb0_rst 0>;
1072 gpio-controller;
1073 interrupt-controller;
6d55d339 1074 #interrupt-cells = <3>;
209394ae
BB		 1075 #size-cells = <0>;
1076 #gpio-cells = <3>;
dbbcd881
HG		 1077
1078 ir_pins_a: ir@0 {
1079 allwinner,pins = "PL4";
1080 allwinner,function = "s_ir";
092a0c3b
MR		 1081 allwinner,drive = <SUN4I_PINCTRL_10_MA>;
1082 allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
dbbcd881 1083 };
fcd60138
BB		 1084
1085 p2wi_pins: p2wi {
1086 allwinner,pins = "PL0", "PL1";
1087 allwinner,function = "s_p2wi";
1088 allwinner,drive = <SUN4I_PINCTRL_10_MA>;
1089 allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
1090 };
1091 };
1092
1093 p2wi: i2c@01f03400 {
1094 compatible = "allwinner,sun6i-a31-p2wi";
1095 reg = <0x01f03400 0x400>;
1096 interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>;
1097 clocks = <&apb0_gates 3>;
1098 clock-frequency = <100000>;
1099 resets = <&apb0_rst 3>;
1100 pinctrl-names = "default";
1101 pinctrl-0 = <&p2wi_pins>;
1102 status = "disabled";
1103 #address-cells = <1>;
1104 #size-cells = <0>;
209394ae 1105 };
8aed3b31
MR		 1106 };
1107};
Linux 6.x block layer and io_uring tree(s)