[linux-2.6-block.git] / arch / arm / boot / dts / stm32mp157-pinctrl.dtsi

// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
/*
 * Copyright (C) STMicroelectronics 2017 - All Rights Reserved
 * Author: Ludovic Barre <ludovic.barre@st.com> for STMicroelectronics.
 */
#include <dt-bindings/pinctrl/stm32-pinfunc.h>

/ {
	soc {
		pinctrl: pin-controller@50002000 {
			#address-cells = <1>;
			#size-cells = <1>;
			compatible = "st,stm32mp157-pinctrl";
			ranges = <0 0x50002000 0xa400>;
			interrupt-parent = <&exti>;
			st,syscfg = <&exti 0x60 0xff>;
			pins-are-numbered;

			gpioa: gpio@50002000 {
				gpio-controller;
				#gpio-cells = <2>;
				interrupt-controller;
				#interrupt-cells = <2>;
				reg = <0x0 0x400>;
				clocks = <&rcc GPIOA>;
				st,bank-name = "GPIOA";
				ngpios = <16>;
				gpio-ranges = <&pinctrl 0 0 16>;
			};

			gpiob: gpio@50003000 {
				gpio-controller;
				#gpio-cells = <2>;
				interrupt-controller;
				#interrupt-cells = <2>;
				reg = <0x1000 0x400>;
				clocks = <&rcc GPIOB>;
				st,bank-name = "GPIOB";
				ngpios = <16>;
				gpio-ranges = <&pinctrl 0 16 16>;
			};

			gpioc: gpio@50004000 {
				gpio-controller;
				#gpio-cells = <2>;
				interrupt-controller;
				#interrupt-cells = <2>;
				reg = <0x2000 0x400>;
				clocks = <&rcc GPIOC>;
				st,bank-name = "GPIOC";
				ngpios = <16>;
				gpio-ranges = <&pinctrl 0 32 16>;
			};

			gpiod: gpio@50005000 {
				gpio-controller;
				#gpio-cells = <2>;
				interrupt-controller;
				#interrupt-cells = <2>;
				reg = <0x3000 0x400>;
				clocks = <&rcc GPIOD>;
				st,bank-name = "GPIOD";
				ngpios = <16>;
				gpio-ranges = <&pinctrl 0 48 16>;
			};

			gpioe: gpio@50006000 {
				gpio-controller;
				#gpio-cells = <2>;
				interrupt-controller;
				#interrupt-cells = <2>;
				reg = <0x4000 0x400>;
				clocks = <&rcc GPIOE>;
				st,bank-name = "GPIOE";
				ngpios = <16>;
				gpio-ranges = <&pinctrl 0 64 16>;
			};

			gpiof: gpio@50007000 {
				gpio-controller;
				#gpio-cells = <2>;
				interrupt-controller;
				#interrupt-cells = <2>;
				reg = <0x5000 0x400>;
				clocks = <&rcc GPIOF>;
				st,bank-name = "GPIOF";
				ngpios = <16>;
				gpio-ranges = <&pinctrl 0 80 16>;
			};

			gpiog: gpio@50008000 {
				gpio-controller;
				#gpio-cells = <2>;
				interrupt-controller;
				#interrupt-cells = <2>;
				reg = <0x6000 0x400>;
				clocks = <&rcc GPIOG>;
				st,bank-name = "GPIOG";
				ngpios = <16>;
				gpio-ranges = <&pinctrl 0 96 16>;
			};

			gpioh: gpio@50009000 {
				gpio-controller;
				#gpio-cells = <2>;
				interrupt-controller;
				#interrupt-cells = <2>;
				reg = <0x7000 0x400>;
				clocks = <&rcc GPIOH>;
				st,bank-name = "GPIOH";
				ngpios = <16>;
				gpio-ranges = <&pinctrl 0 112 16>;
			};

			gpioi: gpio@5000a000 {
				gpio-controller;
				#gpio-cells = <2>;
				interrupt-controller;
				#interrupt-cells = <2>;
				reg = <0x8000 0x400>;
				clocks = <&rcc GPIOI>;
				st,bank-name = "GPIOI";
				ngpios = <16>;
				gpio-ranges = <&pinctrl 0 128 16>;
			};

			gpioj: gpio@5000b000 {
				gpio-controller;
				#gpio-cells = <2>;
				interrupt-controller;
				#interrupt-cells = <2>;
				reg = <0x9000 0x400>;
				clocks = <&rcc GPIOJ>;
				st,bank-name = "GPIOJ";
				ngpios = <16>;
				gpio-ranges = <&pinctrl 0 144 16>;
			};

			gpiok: gpio@5000c000 {
				gpio-controller;
				#gpio-cells = <2>;
				interrupt-controller;
				#interrupt-cells = <2>;
				reg = <0xa000 0x400>;
				clocks = <&rcc GPIOK>;
				st,bank-name = "GPIOK";
				ngpios = <8>;
				gpio-ranges = <&pinctrl 0 160 8>;
			};

			cec_pins_a: cec-0 {
				pins {
					pinmux = <STM32_PINMUX('A', 15, AF4)>;
					bias-disable;
					drive-open-drain;
					slew-rate = <0>;
				};
			};

			cec_pins_sleep_a: cec-sleep-0 {
				pins {
					pinmux = <STM32_PINMUX('A', 15, ANALOG)>; /* HDMI_CEC */
				};
			};

			cec_pins_b: cec-1 {
				pins {
					pinmux = <STM32_PINMUX('B', 6, AF5)>;
					bias-disable;
					drive-open-drain;
					slew-rate = <0>;
				};
			};

			cec_pins_sleep_b: cec-sleep-1 {
				pins {
					pinmux = <STM32_PINMUX('B', 6, ANALOG)>; /* HDMI_CEC */
				};
			};

			ethernet0_rgmii_pins_a: rgmii-0 {
				pins1 {
					pinmux = <STM32_PINMUX('G', 5, AF11)>, /* ETH_RGMII_CLK125 */
						 <STM32_PINMUX('G', 4, AF11)>, /* ETH_RGMII_GTX_CLK */
						 <STM32_PINMUX('G', 13, AF11)>, /* ETH_RGMII_TXD0 */
						 <STM32_PINMUX('G', 14, AF11)>, /* ETH_RGMII_TXD1 */
						 <STM32_PINMUX('C', 2, AF11)>, /* ETH_RGMII_TXD2 */
						 <STM32_PINMUX('E', 2, AF11)>, /* ETH_RGMII_TXD3 */
						 <STM32_PINMUX('B', 11, AF11)>, /* ETH_RGMII_TX_CTL */
						 <STM32_PINMUX('A', 2, AF11)>, /* ETH_MDIO */
						 <STM32_PINMUX('C', 1, AF11)>; /* ETH_MDC */
					bias-disable;
					drive-push-pull;
					slew-rate = <3>;
				};
				pins2 {
					pinmux = <STM32_PINMUX('C', 4, AF11)>, /* ETH_RGMII_RXD0 */
						 <STM32_PINMUX('C', 5, AF11)>, /* ETH_RGMII_RXD1 */
						 <STM32_PINMUX('B', 0, AF11)>, /* ETH_RGMII_RXD2 */
						 <STM32_PINMUX('B', 1, AF11)>, /* ETH_RGMII_RXD3 */
						 <STM32_PINMUX('A', 1, AF11)>, /* ETH_RGMII_RX_CLK */
						 <STM32_PINMUX('A', 7, AF11)>; /* ETH_RGMII_RX_CTL */
					bias-disable;
				};
			};

			ethernet0_rgmii_pins_sleep_a: rgmii-sleep-0 {
				pins1 {
					pinmux = <STM32_PINMUX('G', 5, ANALOG)>, /* ETH_RGMII_CLK125 */
						 <STM32_PINMUX('G', 4, ANALOG)>, /* ETH_RGMII_GTX_CLK */
						 <STM32_PINMUX('G', 13, ANALOG)>, /* ETH_RGMII_TXD0 */
						 <STM32_PINMUX('G', 14, ANALOG)>, /* ETH_RGMII_TXD1 */
						 <STM32_PINMUX('C', 2, ANALOG)>, /* ETH_RGMII_TXD2 */
						 <STM32_PINMUX('E', 2, ANALOG)>, /* ETH_RGMII_TXD3 */
						 <STM32_PINMUX('B', 11, ANALOG)>, /* ETH_RGMII_TX_CTL */
						 <STM32_PINMUX('A', 2, ANALOG)>, /* ETH_MDIO */
						 <STM32_PINMUX('C', 1, ANALOG)>, /* ETH_MDC */
						 <STM32_PINMUX('C', 4, ANALOG)>, /* ETH_RGMII_RXD0 */
						 <STM32_PINMUX('C', 5, ANALOG)>, /* ETH_RGMII_RXD1 */
						 <STM32_PINMUX('B', 0, ANALOG)>, /* ETH_RGMII_RXD2 */
						 <STM32_PINMUX('B', 1, ANALOG)>, /* ETH_RGMII_RXD3 */
						 <STM32_PINMUX('A', 1, ANALOG)>, /* ETH_RGMII_RX_CLK */
						 <STM32_PINMUX('A', 7, ANALOG)>; /* ETH_RGMII_RX_CTL */
				};
			};

			i2c1_pins_a: i2c1-0 {
				pins {
					pinmux = <STM32_PINMUX('D', 12, AF5)>, /* I2C1_SCL */
						 <STM32_PINMUX('F', 15, AF5)>; /* I2C1_SDA */
					bias-disable;
					drive-open-drain;
					slew-rate = <0>;
				};
			};

			i2c1_pins_sleep_a: i2c1-1 {
				pins {
					pinmux = <STM32_PINMUX('D', 12, ANALOG)>, /* I2C1_SCL */
						 <STM32_PINMUX('F', 15, ANALOG)>; /* I2C1_SDA */
				};
			};

			i2c2_pins_a: i2c2-0 {
				pins {
					pinmux = <STM32_PINMUX('H', 4, AF4)>, /* I2C2_SCL */
						 <STM32_PINMUX('H', 5, AF4)>; /* I2C2_SDA */
					bias-disable;
					drive-open-drain;
					slew-rate = <0>;
				};
			};

			i2c2_pins_sleep_a: i2c2-1 {
				pins {
					pinmux = <STM32_PINMUX('H', 4, ANALOG)>, /* I2C2_SCL */
						 <STM32_PINMUX('H', 5, ANALOG)>; /* I2C2_SDA */
				};
			};

			i2c5_pins_a: i2c5-0 {
				pins {
					pinmux = <STM32_PINMUX('A', 11, AF4)>, /* I2C5_SCL */
						 <STM32_PINMUX('A', 12, AF4)>; /* I2C5_SDA */
					bias-disable;
					drive-open-drain;
					slew-rate = <0>;
				};
			};

			i2c5_pins_sleep_a: i2c5-1 {
				pins {
					pinmux = <STM32_PINMUX('A', 11, ANALOG)>, /* I2C5_SCL */
						 <STM32_PINMUX('A', 12, ANALOG)>; /* I2C5_SDA */

				};
			};

			ltdc_pins_a: ltdc-a-0 {
				pins {
					pinmux = <STM32_PINMUX('G',  7, AF14)>, /* LCD_CLK */
						 <STM32_PINMUX('I', 10, AF14)>, /* LCD_HSYNC */
						 <STM32_PINMUX('I',  9, AF14)>, /* LCD_VSYNC */
						 <STM32_PINMUX('F', 10, AF14)>, /* LCD_DE */
						 <STM32_PINMUX('H',  2, AF14)>, /* LCD_R0 */
						 <STM32_PINMUX('H',  3, AF14)>, /* LCD_R1 */
						 <STM32_PINMUX('H',  8, AF14)>, /* LCD_R2 */
						 <STM32_PINMUX('H',  9, AF14)>, /* LCD_R3 */
						 <STM32_PINMUX('H', 10, AF14)>, /* LCD_R4 */
						 <STM32_PINMUX('C',  0, AF14)>, /* LCD_R5 */
						 <STM32_PINMUX('H', 12, AF14)>, /* LCD_R6 */
						 <STM32_PINMUX('E', 15, AF14)>, /* LCD_R7 */
						 <STM32_PINMUX('E',  5, AF14)>, /* LCD_G0 */
						 <STM32_PINMUX('E',  6, AF14)>, /* LCD_G1 */
						 <STM32_PINMUX('H', 13, AF14)>, /* LCD_G2 */
						 <STM32_PINMUX('H', 14, AF14)>, /* LCD_G3 */
						 <STM32_PINMUX('H', 15, AF14)>, /* LCD_G4 */
						 <STM32_PINMUX('I',  0, AF14)>, /* LCD_G5 */
						 <STM32_PINMUX('I',  1, AF14)>, /* LCD_G6 */
						 <STM32_PINMUX('I',  2, AF14)>, /* LCD_G7 */
						 <STM32_PINMUX('D',  9, AF14)>, /* LCD_B0 */
						 <STM32_PINMUX('G', 12, AF14)>, /* LCD_B1 */
						 <STM32_PINMUX('G', 10, AF14)>, /* LCD_B2 */
						 <STM32_PINMUX('D', 10, AF14)>, /* LCD_B3 */
						 <STM32_PINMUX('I',  4, AF14)>, /* LCD_B4 */
						 <STM32_PINMUX('A',  3, AF14)>, /* LCD_B5 */
						 <STM32_PINMUX('B',  8, AF14)>, /* LCD_B6 */
						 <STM32_PINMUX('D',  8, AF14)>; /* LCD_B7 */
					bias-disable;
					drive-push-pull;
					slew-rate = <1>;
				};
			};

			ltdc_pins_sleep_a: ltdc-a-1 {
				pins {
					pinmux = <STM32_PINMUX('G',  7, ANALOG)>, /* LCD_CLK */
						 <STM32_PINMUX('I', 10, ANALOG)>, /* LCD_HSYNC */
						 <STM32_PINMUX('I',  9, ANALOG)>, /* LCD_VSYNC */
						 <STM32_PINMUX('F', 10, ANALOG)>, /* LCD_DE */
						 <STM32_PINMUX('H',  2, ANALOG)>, /* LCD_R0 */
						 <STM32_PINMUX('H',  3, ANALOG)>, /* LCD_R1 */
						 <STM32_PINMUX('H',  8, ANALOG)>, /* LCD_R2 */
						 <STM32_PINMUX('H',  9, ANALOG)>, /* LCD_R3 */
						 <STM32_PINMUX('H', 10, ANALOG)>, /* LCD_R4 */
						 <STM32_PINMUX('C',  0, ANALOG)>, /* LCD_R5 */
						 <STM32_PINMUX('H', 12, ANALOG)>, /* LCD_R6 */
						 <STM32_PINMUX('E', 15, ANALOG)>, /* LCD_R7 */
						 <STM32_PINMUX('E',  5, ANALOG)>, /* LCD_G0 */
						 <STM32_PINMUX('E',  6, ANALOG)>, /* LCD_G1 */
						 <STM32_PINMUX('H', 13, ANALOG)>, /* LCD_G2 */
						 <STM32_PINMUX('H', 14, ANALOG)>, /* LCD_G3 */
						 <STM32_PINMUX('H', 15, ANALOG)>, /* LCD_G4 */
						 <STM32_PINMUX('I',  0, ANALOG)>, /* LCD_G5 */
						 <STM32_PINMUX('I',  1, ANALOG)>, /* LCD_G6 */
						 <STM32_PINMUX('I',  2, ANALOG)>, /* LCD_G7 */
						 <STM32_PINMUX('D',  9, ANALOG)>, /* LCD_B0 */
						 <STM32_PINMUX('G', 12, ANALOG)>, /* LCD_B1 */
						 <STM32_PINMUX('G', 10, ANALOG)>, /* LCD_B2 */
						 <STM32_PINMUX('D', 10, ANALOG)>, /* LCD_B3 */
						 <STM32_PINMUX('I',  4, ANALOG)>, /* LCD_B4 */
						 <STM32_PINMUX('A',  3, ANALOG)>, /* LCD_B5 */
						 <STM32_PINMUX('B',  8, ANALOG)>, /* LCD_B6 */
						 <STM32_PINMUX('D',  8, ANALOG)>; /* LCD_B7 */
				};
			};

			ltdc_pins_b: ltdc-b-0 {
				pins {
					pinmux = <STM32_PINMUX('I', 14, AF14)>, /* LCD_CLK */
						 <STM32_PINMUX('I', 12, AF14)>, /* LCD_HSYNC */
						 <STM32_PINMUX('I', 13, AF14)>, /* LCD_VSYNC */
						 <STM32_PINMUX('K',  7, AF14)>, /* LCD_DE */
						 <STM32_PINMUX('I', 15, AF14)>, /* LCD_R0 */
						 <STM32_PINMUX('J',  0, AF14)>, /* LCD_R1 */
						 <STM32_PINMUX('J',  1, AF14)>, /* LCD_R2 */
						 <STM32_PINMUX('J',  2, AF14)>, /* LCD_R3 */
						 <STM32_PINMUX('J',  3, AF14)>, /* LCD_R4 */
						 <STM32_PINMUX('J',  4, AF14)>, /* LCD_R5 */
						 <STM32_PINMUX('J',  5, AF14)>, /* LCD_R6 */
						 <STM32_PINMUX('J',  6, AF14)>, /* LCD_R7 */
						 <STM32_PINMUX('J',  7, AF14)>, /* LCD_G0 */
						 <STM32_PINMUX('J',  8, AF14)>, /* LCD_G1 */
						 <STM32_PINMUX('J',  9, AF14)>, /* LCD_G2 */
						 <STM32_PINMUX('J', 10, AF14)>, /* LCD_G3 */
						 <STM32_PINMUX('J', 11, AF14)>, /* LCD_G4 */
						 <STM32_PINMUX('K',  0, AF14)>, /* LCD_G5 */
						 <STM32_PINMUX('K',  1, AF14)>, /* LCD_G6 */
						 <STM32_PINMUX('K',  2, AF14)>, /* LCD_G7 */
						 <STM32_PINMUX('J', 12, AF14)>, /* LCD_B0 */
						 <STM32_PINMUX('J', 13, AF14)>, /* LCD_B1 */
						 <STM32_PINMUX('J', 14, AF14)>, /* LCD_B2 */
						 <STM32_PINMUX('J', 15, AF14)>, /* LCD_B3 */
						 <STM32_PINMUX('K',  3, AF14)>, /* LCD_B4 */
						 <STM32_PINMUX('K',  4, AF14)>, /* LCD_B5 */
						 <STM32_PINMUX('K',  5, AF14)>, /* LCD_B6 */
						 <STM32_PINMUX('K',  6, AF14)>; /* LCD_B7 */
					bias-disable;
					drive-push-pull;
					slew-rate = <1>;
				};
			};

			ltdc_pins_sleep_b: ltdc-b-1 {
				pins {
					pinmux = <STM32_PINMUX('I', 14, ANALOG)>, /* LCD_CLK */
						 <STM32_PINMUX('I', 12, ANALOG)>, /* LCD_HSYNC */
						 <STM32_PINMUX('I', 13, ANALOG)>, /* LCD_VSYNC */
						 <STM32_PINMUX('K',  7, ANALOG)>, /* LCD_DE */
						 <STM32_PINMUX('I', 15, ANALOG)>, /* LCD_R0 */
						 <STM32_PINMUX('J',  0, ANALOG)>, /* LCD_R1 */
						 <STM32_PINMUX('J',  1, ANALOG)>, /* LCD_R2 */
						 <STM32_PINMUX('J',  2, ANALOG)>, /* LCD_R3 */
						 <STM32_PINMUX('J',  3, ANALOG)>, /* LCD_R4 */
						 <STM32_PINMUX('J',  4, ANALOG)>, /* LCD_R5 */
						 <STM32_PINMUX('J',  5, ANALOG)>, /* LCD_R6 */
						 <STM32_PINMUX('J',  6, ANALOG)>, /* LCD_R7 */
						 <STM32_PINMUX('J',  7, ANALOG)>, /* LCD_G0 */
						 <STM32_PINMUX('J',  8, ANALOG)>, /* LCD_G1 */
						 <STM32_PINMUX('J',  9, ANALOG)>, /* LCD_G2 */
						 <STM32_PINMUX('J', 10, ANALOG)>, /* LCD_G3 */
						 <STM32_PINMUX('J', 11, ANALOG)>, /* LCD_G4 */
						 <STM32_PINMUX('K',  0, ANALOG)>, /* LCD_G5 */
						 <STM32_PINMUX('K',  1, ANALOG)>, /* LCD_G6 */
						 <STM32_PINMUX('K',  2, ANALOG)>, /* LCD_G7 */
						 <STM32_PINMUX('J', 12, ANALOG)>, /* LCD_B0 */
						 <STM32_PINMUX('J', 13, ANALOG)>, /* LCD_B1 */
						 <STM32_PINMUX('J', 14, ANALOG)>, /* LCD_B2 */
						 <STM32_PINMUX('J', 15, ANALOG)>, /* LCD_B3 */
						 <STM32_PINMUX('K',  3, ANALOG)>, /* LCD_B4 */
						 <STM32_PINMUX('K',  4, ANALOG)>, /* LCD_B5 */
						 <STM32_PINMUX('K',  5, ANALOG)>, /* LCD_B6 */
						 <STM32_PINMUX('K',  6, ANALOG)>; /* LCD_B7 */
				};
			};

			m_can1_pins_a: m-can1-0 {
				pins1 {
					pinmux = <STM32_PINMUX('H', 13, AF9)>; /* CAN1_TX */
					slew-rate = <1>;
					drive-push-pull;
					bias-disable;
				};
				pins2 {
					pinmux = <STM32_PINMUX('I', 9, AF9)>; /* CAN1_RX */
					bias-disable;
				};
			};

			m_can1_sleep_pins_a: m_can1-sleep@0 {
				pins {
					pinmux = <STM32_PINMUX('H', 13, ANALOG)>, /* CAN1_TX */
						 <STM32_PINMUX('I', 9, ANALOG)>; /* CAN1_RX */
				};
			};

			pwm2_pins_a: pwm2-0 {
				pins {
					pinmux = <STM32_PINMUX('A', 3, AF1)>; /* TIM2_CH4 */
					bias-pull-down;
					drive-push-pull;
					slew-rate = <0>;
				};
			};

			pwm8_pins_a: pwm8-0 {
				pins {
					pinmux = <STM32_PINMUX('I', 2, AF3)>; /* TIM8_CH4 */
					bias-pull-down;
					drive-push-pull;
					slew-rate = <0>;
				};
			};

			pwm12_pins_a: pwm12-0 {
				pins {
					pinmux = <STM32_PINMUX('H', 6, AF2)>; /* TIM12_CH1 */
					bias-pull-down;
					drive-push-pull;
					slew-rate = <0>;
				};
			};

			qspi_clk_pins_a: qspi-clk-0 {
				pins {
					pinmux = <STM32_PINMUX('F', 10, AF9)>; /* QSPI_CLK */
					bias-disable;
					drive-push-pull;
					slew-rate = <3>;
				};
			};

			qspi_bk1_pins_a: qspi-bk1-0 {
				pins1 {
					pinmux = <STM32_PINMUX('F', 8, AF10)>, /* QSPI_BK1_IO0 */
						 <STM32_PINMUX('F', 9, AF10)>, /* QSPI_BK1_IO1 */
						 <STM32_PINMUX('F', 7, AF9)>, /* QSPI_BK1_IO2 */
						 <STM32_PINMUX('F', 6, AF9)>; /* QSPI_BK1_IO3 */
					bias-disable;
					drive-push-pull;
					slew-rate = <3>;
				};
				pins2 {
					pinmux = <STM32_PINMUX('B', 6, AF10)>; /* QSPI_BK1_NCS */
					bias-pull-up;
					drive-push-pull;
					slew-rate = <3>;
				};
			};

			qspi_bk2_pins_a: qspi-bk2-0 {
				pins1 {
					pinmux = <STM32_PINMUX('H', 2, AF9)>, /* QSPI_BK2_IO0 */
						 <STM32_PINMUX('H', 3, AF9)>, /* QSPI_BK2_IO1 */
						 <STM32_PINMUX('G', 10, AF11)>, /* QSPI_BK2_IO2 */
						 <STM32_PINMUX('G', 7, AF11)>; /* QSPI_BK2_IO3 */
					bias-disable;
					drive-push-pull;
					slew-rate = <3>;
				};
				pins2 {
					pinmux = <STM32_PINMUX('C', 0, AF10)>; /* QSPI_BK2_NCS */
					bias-pull-up;
					drive-push-pull;
					slew-rate = <3>;
				};
			};

			sdmmc1_b4_pins_a: sdmmc1-b4-0 {
				pins {
					pinmux = <STM32_PINMUX('C', 8, AF12)>, /* SDMMC1_D0 */
						 <STM32_PINMUX('C', 9, AF12)>, /* SDMMC1_D1 */
						 <STM32_PINMUX('C', 10, AF12)>, /* SDMMC1_D2 */
						 <STM32_PINMUX('C', 11, AF12)>, /* SDMMC1_D3 */
						 <STM32_PINMUX('C', 12, AF12)>, /* SDMMC1_CK */
						 <STM32_PINMUX('D', 2, AF12)>; /* SDMMC1_CMD */
					slew-rate = <3>;
					drive-push-pull;
					bias-disable;
				};
			};

			sdmmc1_b4_od_pins_a: sdmmc1-b4-od-0 {
				pins1 {
					pinmux = <STM32_PINMUX('C', 8, AF12)>, /* SDMMC1_D0 */
						 <STM32_PINMUX('C', 9, AF12)>, /* SDMMC1_D1 */
						 <STM32_PINMUX('C', 10, AF12)>, /* SDMMC1_D2 */
						 <STM32_PINMUX('C', 11, AF12)>, /* SDMMC1_D3 */
						 <STM32_PINMUX('C', 12, AF12)>; /* SDMMC1_CK */
					slew-rate = <3>;
					drive-push-pull;
					bias-disable;
				};
				pins2{
					pinmux = <STM32_PINMUX('D', 2, AF12)>; /* SDMMC1_CMD */
					slew-rate = <3>;
					drive-open-drain;
					bias-disable;
				};
			};

			sdmmc1_b4_sleep_pins_a: sdmmc1-b4-sleep-0 {
				pins {
					pinmux = <STM32_PINMUX('C', 8, ANALOG)>, /* SDMMC1_D0 */
						 <STM32_PINMUX('C', 9, ANALOG)>, /* SDMMC1_D1 */
						 <STM32_PINMUX('C', 10, ANALOG)>, /* SDMMC1_D2 */
						 <STM32_PINMUX('C', 11, ANALOG)>, /* SDMMC1_D3 */
						 <STM32_PINMUX('C', 12, ANALOG)>, /* SDMMC1_CK */
						 <STM32_PINMUX('D', 2, ANALOG)>; /* SDMMC1_CMD */
				};
			};

			sdmmc1_dir_pins_a: sdmmc1-dir-0 {
				pins1 {
					pinmux = <STM32_PINMUX('F', 2, AF11)>, /* SDMMC1_D0DIR */
						 <STM32_PINMUX('C', 7, AF8)>, /* SDMMC1_D123DIR */
						 <STM32_PINMUX('B', 9, AF11)>; /* SDMMC1_CDIR */
					slew-rate = <3>;
					drive-push-pull;
					bias-pull-up;
				};
				pins2{
					pinmux = <STM32_PINMUX('E', 4, AF8)>; /* SDMMC1_CKIN */
					bias-pull-up;
				};
			};

			sdmmc1_dir_sleep_pins_a: sdmmc1-dir-sleep-0 {
				pins {
					pinmux = <STM32_PINMUX('F', 2, ANALOG)>, /* SDMMC1_D0DIR */
						 <STM32_PINMUX('C', 7, ANALOG)>, /* SDMMC1_D123DIR */
						 <STM32_PINMUX('B', 9, ANALOG)>, /* SDMMC1_CDIR */
						 <STM32_PINMUX('E', 4, ANALOG)>; /* SDMMC1_CKIN */
				};
			};

			spdifrx_pins_a: spdifrx-0 {
				pins {
					pinmux = <STM32_PINMUX('G', 12, AF8)>; /* SPDIF_IN1 */
					bias-disable;
				};
			};

			spdifrx_sleep_pins_a: spdifrx-1 {
				pins {
					pinmux = <STM32_PINMUX('G', 12, ANALOG)>; /* SPDIF_IN1 */
				};
			};

			uart4_pins_a: uart4-0 {
				pins1 {
					pinmux = <STM32_PINMUX('G', 11, AF6)>; /* UART4_TX */
					bias-disable;
					drive-push-pull;
					slew-rate = <0>;
				};
				pins2 {
					pinmux = <STM32_PINMUX('B', 2, AF8)>; /* UART4_RX */
					bias-disable;
				};
			};
		};

		pinctrl_z: pin-controller-z@54004000 {
			#address-cells = <1>;
			#size-cells = <1>;
			compatible = "st,stm32mp157-z-pinctrl";
			ranges = <0 0x54004000 0x400>;
			pins-are-numbered;
			interrupt-parent = <&exti>;
			st,syscfg = <&exti 0x60 0xff>;

			gpioz: gpio@54004000 {
				gpio-controller;
				#gpio-cells = <2>;
				interrupt-controller;
				#interrupt-cells = <2>;
				reg = <0 0x400>;
				clocks = <&rcc GPIOZ>;
				st,bank-name = "GPIOZ";
				st,bank-ioport = <11>;
				ngpios = <8>;
				gpio-ranges = <&pinctrl_z 0 400 8>;
			};

			i2c4_pins_a: i2c4-0 {
				pins {
					pinmux = <STM32_PINMUX('Z', 4, AF6)>, /* I2C4_SCL */
						 <STM32_PINMUX('Z', 5, AF6)>; /* I2C4_SDA */
					bias-disable;
					drive-open-drain;
					slew-rate = <0>;
				};
			};

			i2c4_pins_sleep_a: i2c4-1 {
				pins {
					pinmux = <STM32_PINMUX('Z', 4, ANALOG)>, /* I2C4_SCL */
						 <STM32_PINMUX('Z', 5, ANALOG)>; /* I2C4_SDA */
				};
			};

			spi1_pins_a: spi1-0 {
				pins1 {
					pinmux = <STM32_PINMUX('Z', 0, AF5)>, /* SPI1_SCK */
						 <STM32_PINMUX('Z', 2, AF5)>; /* SPI1_MOSI */
					bias-disable;
					drive-push-pull;
					slew-rate = <1>;
				};

				pins2 {
					pinmux = <STM32_PINMUX('Z', 1, AF5)>; /* SPI1_MISO */
					bias-disable;
				};
			};
		};
	};
};
Commit	Line	Data
8471a202 LB	1	// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
	2	/*
	3	* Copyright (C) STMicroelectronics 2017 - All Rights Reserved
	4	* Author: Ludovic Barre <ludovic.barre@st.com> for STMicroelectronics.
	5	*/
	6	#include <dt-bindings/pinctrl/stm32-pinfunc.h>
	7
	8	/ {
	9	soc {
20ab2d88	10	pinctrl: pin-controller@50002000 {
8471a202 LB	11	#address-cells = <1>;
	12	#size-cells = <1>;
	13	compatible = "st,stm32mp157-pinctrl";
	14	ranges = <0 0x50002000 0xa400>;
6a88c221 LB	15	interrupt-parent = <&exti>;
6a88c221 LB	16	st,syscfg = <&exti 0x60 0xff>;
8471a202 LB	17	pins-are-numbered;
	18
	19	gpioa: gpio@50002000 {
	20	gpio-controller;
	21	#gpio-cells = <2>;
	22	interrupt-controller;
	23	#interrupt-cells = <2>;
	24	reg = <0x0 0x400>;
3599a8af	25	clocks = <&rcc GPIOA>;
8471a202 LB	26	st,bank-name = "GPIOA";
	27	ngpios = <16>;
	28	gpio-ranges = <&pinctrl 0 0 16>;
	29	};
	30
	31	gpiob: gpio@50003000 {
	32	gpio-controller;
	33	#gpio-cells = <2>;
	34	interrupt-controller;
	35	#interrupt-cells = <2>;
	36	reg = <0x1000 0x400>;
3599a8af	37	clocks = <&rcc GPIOB>;
8471a202 LB	38	st,bank-name = "GPIOB";
	39	ngpios = <16>;
	40	gpio-ranges = <&pinctrl 0 16 16>;
	41	};
	42
	43	gpioc: gpio@50004000 {
	44	gpio-controller;
	45	#gpio-cells = <2>;
	46	interrupt-controller;
	47	#interrupt-cells = <2>;
	48	reg = <0x2000 0x400>;
3599a8af	49	clocks = <&rcc GPIOC>;
8471a202 LB	50	st,bank-name = "GPIOC";
	51	ngpios = <16>;
	52	gpio-ranges = <&pinctrl 0 32 16>;
	53	};
	54
	55	gpiod: gpio@50005000 {
	56	gpio-controller;
	57	#gpio-cells = <2>;
	58	interrupt-controller;
	59	#interrupt-cells = <2>;
	60	reg = <0x3000 0x400>;
3599a8af	61	clocks = <&rcc GPIOD>;
8471a202 LB	62	st,bank-name = "GPIOD";
	63	ngpios = <16>;
	64	gpio-ranges = <&pinctrl 0 48 16>;
	65	};
	66
	67	gpioe: gpio@50006000 {
	68	gpio-controller;
	69	#gpio-cells = <2>;
	70	interrupt-controller;
	71	#interrupt-cells = <2>;
	72	reg = <0x4000 0x400>;
3599a8af	73	clocks = <&rcc GPIOE>;
8471a202 LB	74	st,bank-name = "GPIOE";
	75	ngpios = <16>;
	76	gpio-ranges = <&pinctrl 0 64 16>;
	77	};
	78
	79	gpiof: gpio@50007000 {
	80	gpio-controller;
	81	#gpio-cells = <2>;
	82	interrupt-controller;
	83	#interrupt-cells = <2>;
	84	reg = <0x5000 0x400>;
3599a8af	85	clocks = <&rcc GPIOF>;
8471a202 LB	86	st,bank-name = "GPIOF";
	87	ngpios = <16>;
	88	gpio-ranges = <&pinctrl 0 80 16>;
	89	};
	90
	91	gpiog: gpio@50008000 {
	92	gpio-controller;
	93	#gpio-cells = <2>;
	94	interrupt-controller;
	95	#interrupt-cells = <2>;
	96	reg = <0x6000 0x400>;
3599a8af	97	clocks = <&rcc GPIOG>;
8471a202 LB	98	st,bank-name = "GPIOG";
	99	ngpios = <16>;
	100	gpio-ranges = <&pinctrl 0 96 16>;
	101	};
	102
	103	gpioh: gpio@50009000 {
	104	gpio-controller;
	105	#gpio-cells = <2>;
	106	interrupt-controller;
	107	#interrupt-cells = <2>;
	108	reg = <0x7000 0x400>;
3599a8af	109	clocks = <&rcc GPIOH>;
8471a202 LB	110	st,bank-name = "GPIOH";
	111	ngpios = <16>;
	112	gpio-ranges = <&pinctrl 0 112 16>;
	113	};
	114
	115	gpioi: gpio@5000a000 {
	116	gpio-controller;
	117	#gpio-cells = <2>;
	118	interrupt-controller;
	119	#interrupt-cells = <2>;
	120	reg = <0x8000 0x400>;
3599a8af	121	clocks = <&rcc GPIOI>;
8471a202 LB	122	st,bank-name = "GPIOI";
	123	ngpios = <16>;
	124	gpio-ranges = <&pinctrl 0 128 16>;
	125	};
	126
	127	gpioj: gpio@5000b000 {
	128	gpio-controller;
	129	#gpio-cells = <2>;
	130	interrupt-controller;
	131	#interrupt-cells = <2>;
	132	reg = <0x9000 0x400>;
3599a8af	133	clocks = <&rcc GPIOJ>;
8471a202 LB	134	st,bank-name = "GPIOJ";
	135	ngpios = <16>;
	136	gpio-ranges = <&pinctrl 0 144 16>;
	137	};
	138
	139	gpiok: gpio@5000c000 {
	140	gpio-controller;
	141	#gpio-cells = <2>;
	142	interrupt-controller;
	143	#interrupt-cells = <2>;
	144	reg = <0xa000 0x400>;
3599a8af	145	clocks = <&rcc GPIOK>;
8471a202 LB	146	st,bank-name = "GPIOK";
	147	ngpios = <8>;
	148	gpio-ranges = <&pinctrl 0 160 8>;
	149	};
bcc4f4e1	150
7123be3b	151	cec_pins_a: cec-0 {
	152	pins {
	153	pinmux = <STM32_PINMUX('A', 15, AF4)>;
	154	bias-disable;
	155	drive-open-drain;
	156	slew-rate = <0>;
	157	};
	158	};
	159
5eaae049 YF	160	cec_pins_sleep_a: cec-sleep-0 {
	161	pins {
	162	pinmux = <STM32_PINMUX('A', 15, ANALOG)>; /* HDMI_CEC */
	163	};
	164	};
	165
	166	cec_pins_b: cec-1 {
	167	pins {
	168	pinmux = <STM32_PINMUX('B', 6, AF5)>;
	169	bias-disable;
	170	drive-open-drain;
	171	slew-rate = <0>;
	172	};
	173	};
	174
	175	cec_pins_sleep_b: cec-sleep-1 {
	176	pins {
	177	pinmux = <STM32_PINMUX('B', 6, ANALOG)>; /* HDMI_CEC */
	178	};
	179	};
	180
a7419ff8 CR	181	ethernet0_rgmii_pins_a: rgmii-0 {
	182	pins1 {
	183	pinmux = <STM32_PINMUX('G', 5, AF11)>, /* ETH_RGMII_CLK125 */
	184	<STM32_PINMUX('G', 4, AF11)>, /* ETH_RGMII_GTX_CLK */
	185	<STM32_PINMUX('G', 13, AF11)>, /* ETH_RGMII_TXD0 */
	186	<STM32_PINMUX('G', 14, AF11)>, /* ETH_RGMII_TXD1 */
	187	<STM32_PINMUX('C', 2, AF11)>, /* ETH_RGMII_TXD2 */
	188	<STM32_PINMUX('E', 2, AF11)>, /* ETH_RGMII_TXD3 */
	189	<STM32_PINMUX('B', 11, AF11)>, /* ETH_RGMII_TX_CTL */
	190	<STM32_PINMUX('A', 2, AF11)>, /* ETH_MDIO */
	191	<STM32_PINMUX('C', 1, AF11)>; /* ETH_MDC */
	192	bias-disable;
	193	drive-push-pull;
	194	slew-rate = <3>;
	195	};
	196	pins2 {
	197	pinmux = <STM32_PINMUX('C', 4, AF11)>, /* ETH_RGMII_RXD0 */
	198	<STM32_PINMUX('C', 5, AF11)>, /* ETH_RGMII_RXD1 */
	199	<STM32_PINMUX('B', 0, AF11)>, /* ETH_RGMII_RXD2 */
	200	<STM32_PINMUX('B', 1, AF11)>, /* ETH_RGMII_RXD3 */
	201	<STM32_PINMUX('A', 1, AF11)>, /* ETH_RGMII_RX_CLK */
	202	<STM32_PINMUX('A', 7, AF11)>; /* ETH_RGMII_RX_CTL */
	203	bias-disable;
	204	};
	205	};
	206
	207	ethernet0_rgmii_pins_sleep_a: rgmii-sleep-0 {
	208	pins1 {
	209	pinmux = <STM32_PINMUX('G', 5, ANALOG)>, /* ETH_RGMII_CLK125 */
	210	<STM32_PINMUX('G', 4, ANALOG)>, /* ETH_RGMII_GTX_CLK */
	211	<STM32_PINMUX('G', 13, ANALOG)>, /* ETH_RGMII_TXD0 */
	212	<STM32_PINMUX('G', 14, ANALOG)>, /* ETH_RGMII_TXD1 */
	213	<STM32_PINMUX('C', 2, ANALOG)>, /* ETH_RGMII_TXD2 */
	214	<STM32_PINMUX('E', 2, ANALOG)>, /* ETH_RGMII_TXD3 */
	215	<STM32_PINMUX('B', 11, ANALOG)>, /* ETH_RGMII_TX_CTL */
	216	<STM32_PINMUX('A', 2, ANALOG)>, /* ETH_MDIO */
	217	<STM32_PINMUX('C', 1, ANALOG)>, /* ETH_MDC */
	218	<STM32_PINMUX('C', 4, ANALOG)>, /* ETH_RGMII_RXD0 */
	219	<STM32_PINMUX('C', 5, ANALOG)>, /* ETH_RGMII_RXD1 */
	220	<STM32_PINMUX('B', 0, ANALOG)>, /* ETH_RGMII_RXD2 */
	221	<STM32_PINMUX('B', 1, ANALOG)>, /* ETH_RGMII_RXD3 */
	222	<STM32_PINMUX('A', 1, ANALOG)>, /* ETH_RGMII_RX_CLK */
	223	<STM32_PINMUX('A', 7, ANALOG)>; /* ETH_RGMII_RX_CTL */
	224	};
	225	};
	226
4d58a474 PYM	227	i2c1_pins_a: i2c1-0 {
	228	pins {
	229	pinmux = <STM32_PINMUX('D', 12, AF5)>, /* I2C1_SCL */
	230	<STM32_PINMUX('F', 15, AF5)>; /* I2C1_SDA */
	231	bias-disable;
	232	drive-open-drain;
	233	slew-rate = <0>;
	234	};
	235	};
	236
f85c8acc YF	237	i2c1_pins_sleep_a: i2c1-1 {
	238	pins {
	239	pinmux = <STM32_PINMUX('D', 12, ANALOG)>, /* I2C1_SCL */
	240	<STM32_PINMUX('F', 15, ANALOG)>; /* I2C1_SDA */
	241	};
	242	};
	243
4d58a474 PYM	244	i2c2_pins_a: i2c2-0 {
	245	pins {
	246	pinmux = <STM32_PINMUX('H', 4, AF4)>, /* I2C2_SCL */
	247	<STM32_PINMUX('H', 5, AF4)>; /* I2C2_SDA */
	248	bias-disable;
	249	drive-open-drain;
	250	slew-rate = <0>;
	251	};
	252	};
	253
f85c8acc YF	254	i2c2_pins_sleep_a: i2c2-1 {
	255	pins {
	256	pinmux = <STM32_PINMUX('H', 4, ANALOG)>, /* I2C2_SCL */
	257	<STM32_PINMUX('H', 5, ANALOG)>; /* I2C2_SDA */
	258	};
	259	};
	260
4d58a474 PYM	261	i2c5_pins_a: i2c5-0 {
	262	pins {
	263	pinmux = <STM32_PINMUX('A', 11, AF4)>, /* I2C5_SCL */
	264	<STM32_PINMUX('A', 12, AF4)>; /* I2C5_SDA */
	265	bias-disable;
	266	drive-open-drain;
	267	slew-rate = <0>;
	268	};
	269	};
	270
f85c8acc YF	271	i2c5_pins_sleep_a: i2c5-1 {
	272	pins {
	273	pinmux = <STM32_PINMUX('A', 11, ANALOG)>, /* I2C5_SCL */
	274	<STM32_PINMUX('A', 12, ANALOG)>; /* I2C5_SDA */
	275
	276	};
	277	};
	278
63834ff2 YF	279	ltdc_pins_a: ltdc-a-0 {
	280	pins {
	281	pinmux = <STM32_PINMUX('G', 7, AF14)>, /* LCD_CLK */
	282	<STM32_PINMUX('I', 10, AF14)>, /* LCD_HSYNC */
	283	<STM32_PINMUX('I', 9, AF14)>, /* LCD_VSYNC */
	284	<STM32_PINMUX('F', 10, AF14)>, /* LCD_DE */
	285	<STM32_PINMUX('H', 2, AF14)>, /* LCD_R0 */
	286	<STM32_PINMUX('H', 3, AF14)>, /* LCD_R1 */
	287	<STM32_PINMUX('H', 8, AF14)>, /* LCD_R2 */
	288	<STM32_PINMUX('H', 9, AF14)>, /* LCD_R3 */
	289	<STM32_PINMUX('H', 10, AF14)>, /* LCD_R4 */
	290	<STM32_PINMUX('C', 0, AF14)>, /* LCD_R5 */
	291	<STM32_PINMUX('H', 12, AF14)>, /* LCD_R6 */
	292	<STM32_PINMUX('E', 15, AF14)>, /* LCD_R7 */
	293	<STM32_PINMUX('E', 5, AF14)>, /* LCD_G0 */
	294	<STM32_PINMUX('E', 6, AF14)>, /* LCD_G1 */
	295	<STM32_PINMUX('H', 13, AF14)>, /* LCD_G2 */
	296	<STM32_PINMUX('H', 14, AF14)>, /* LCD_G3 */
	297	<STM32_PINMUX('H', 15, AF14)>, /* LCD_G4 */
	298	<STM32_PINMUX('I', 0, AF14)>, /* LCD_G5 */
	299	<STM32_PINMUX('I', 1, AF14)>, /* LCD_G6 */
	300	<STM32_PINMUX('I', 2, AF14)>, /* LCD_G7 */
	301	<STM32_PINMUX('D', 9, AF14)>, /* LCD_B0 */
	302	<STM32_PINMUX('G', 12, AF14)>, /* LCD_B1 */
	303	<STM32_PINMUX('G', 10, AF14)>, /* LCD_B2 */
	304	<STM32_PINMUX('D', 10, AF14)>, /* LCD_B3 */
	305	<STM32_PINMUX('I', 4, AF14)>, /* LCD_B4 */
	306	<STM32_PINMUX('A', 3, AF14)>, /* LCD_B5 */
	307	<STM32_PINMUX('B', 8, AF14)>, /* LCD_B6 */
	308	<STM32_PINMUX('D', 8, AF14)>; /* LCD_B7 */
	309	bias-disable;
	310	drive-push-pull;
	311	slew-rate = <1>;
	312	};
	313	};
	314
	315	ltdc_pins_sleep_a: ltdc-a-1 {
	316	pins {
	317	pinmux = <STM32_PINMUX('G', 7, ANALOG)>, /* LCD_CLK */
	318	<STM32_PINMUX('I', 10, ANALOG)>, /* LCD_HSYNC */
	319	<STM32_PINMUX('I', 9, ANALOG)>, /* LCD_VSYNC */
	320	<STM32_PINMUX('F', 10, ANALOG)>, /* LCD_DE */
	321	<STM32_PINMUX('H', 2, ANALOG)>, /* LCD_R0 */
	322	<STM32_PINMUX('H', 3, ANALOG)>, /* LCD_R1 */
	323	<STM32_PINMUX('H', 8, ANALOG)>, /* LCD_R2 */
	324	<STM32_PINMUX('H', 9, ANALOG)>, /* LCD_R3 */
	325	<STM32_PINMUX('H', 10, ANALOG)>, /* LCD_R4 */
	326	<STM32_PINMUX('C', 0, ANALOG)>, /* LCD_R5 */
	327	<STM32_PINMUX('H', 12, ANALOG)>, /* LCD_R6 */
	328	<STM32_PINMUX('E', 15, ANALOG)>, /* LCD_R7 */
	329	<STM32_PINMUX('E', 5, ANALOG)>, /* LCD_G0 */
	330	<STM32_PINMUX('E', 6, ANALOG)>, /* LCD_G1 */
	331	<STM32_PINMUX('H', 13, ANALOG)>, /* LCD_G2 */
	332	<STM32_PINMUX('H', 14, ANALOG)>, /* LCD_G3 */
	333	<STM32_PINMUX('H', 15, ANALOG)>, /* LCD_G4 */
	334	<STM32_PINMUX('I', 0, ANALOG)>, /* LCD_G5 */
	335	<STM32_PINMUX('I', 1, ANALOG)>, /* LCD_G6 */
	336	<STM32_PINMUX('I', 2, ANALOG)>, /* LCD_G7 */
	337	<STM32_PINMUX('D', 9, ANALOG)>, /* LCD_B0 */
	338	<STM32_PINMUX('G', 12, ANALOG)>, /* LCD_B1 */
	339	<STM32_PINMUX('G', 10, ANALOG)>, /* LCD_B2 */
	340	<STM32_PINMUX('D', 10, ANALOG)>, /* LCD_B3 */
	341	<STM32_PINMUX('I', 4, ANALOG)>, /* LCD_B4 */
	342	<STM32_PINMUX('A', 3, ANALOG)>, /* LCD_B5 */
343	<STM32_PINMUX('B', 8, ANALOG)>, /* LCD_B6 */
344	<STM32_PINMUX('D', 8, ANALOG)>; /* LCD_B7 */
345	};
346	};
347
348	ltdc_pins_b: ltdc-b-0 {
349	pins {
350	pinmux = <STM32_PINMUX('I', 14, AF14)>, /* LCD_CLK */
351	<STM32_PINMUX('I', 12, AF14)>, /* LCD_HSYNC */
352	<STM32_PINMUX('I', 13, AF14)>, /* LCD_VSYNC */
353	<STM32_PINMUX('K', 7, AF14)>, /* LCD_DE */
354	<STM32_PINMUX('I', 15, AF14)>, /* LCD_R0 */
355	<STM32_PINMUX('J', 0, AF14)>, /* LCD_R1 */
356	<STM32_PINMUX('J', 1, AF14)>, /* LCD_R2 */
357	<STM32_PINMUX('J', 2, AF14)>, /* LCD_R3 */
358	<STM32_PINMUX('J', 3, AF14)>, /* LCD_R4 */
359	<STM32_PINMUX('J', 4, AF14)>, /* LCD_R5 */
360	<STM32_PINMUX('J', 5, AF14)>, /* LCD_R6 */
361	<STM32_PINMUX('J', 6, AF14)>, /* LCD_R7 */
362	<STM32_PINMUX('J', 7, AF14)>, /* LCD_G0 */
363	<STM32_PINMUX('J', 8, AF14)>, /* LCD_G1 */
364	<STM32_PINMUX('J', 9, AF14)>, /* LCD_G2 */
365	<STM32_PINMUX('J', 10, AF14)>, /* LCD_G3 */
366	<STM32_PINMUX('J', 11, AF14)>, /* LCD_G4 */
367	<STM32_PINMUX('K', 0, AF14)>, /* LCD_G5 */
368	<STM32_PINMUX('K', 1, AF14)>, /* LCD_G6 */
369	<STM32_PINMUX('K', 2, AF14)>, /* LCD_G7 */
370	<STM32_PINMUX('J', 12, AF14)>, /* LCD_B0 */
371	<STM32_PINMUX('J', 13, AF14)>, /* LCD_B1 */
372	<STM32_PINMUX('J', 14, AF14)>, /* LCD_B2 */
373	<STM32_PINMUX('J', 15, AF14)>, /* LCD_B3 */
374	<STM32_PINMUX('K', 3, AF14)>, /* LCD_B4 */
375	<STM32_PINMUX('K', 4, AF14)>, /* LCD_B5 */
376	<STM32_PINMUX('K', 5, AF14)>, /* LCD_B6 */
377	<STM32_PINMUX('K', 6, AF14)>; /* LCD_B7 */
378	bias-disable;
379	drive-push-pull;
380	slew-rate = <1>;
381	};
382	};
383
384	ltdc_pins_sleep_b: ltdc-b-1 {
385	pins {
386	pinmux = <STM32_PINMUX('I', 14, ANALOG)>, /* LCD_CLK */
387	<STM32_PINMUX('I', 12, ANALOG)>, /* LCD_HSYNC */
388	<STM32_PINMUX('I', 13, ANALOG)>, /* LCD_VSYNC */
389	<STM32_PINMUX('K', 7, ANALOG)>, /* LCD_DE */
390	<STM32_PINMUX('I', 15, ANALOG)>, /* LCD_R0 */
391	<STM32_PINMUX('J', 0, ANALOG)>, /* LCD_R1 */
392	<STM32_PINMUX('J', 1, ANALOG)>, /* LCD_R2 */
393	<STM32_PINMUX('J', 2, ANALOG)>, /* LCD_R3 */
394	<STM32_PINMUX('J', 3, ANALOG)>, /* LCD_R4 */
395	<STM32_PINMUX('J', 4, ANALOG)>, /* LCD_R5 */
396	<STM32_PINMUX('J', 5, ANALOG)>, /* LCD_R6 */
397	<STM32_PINMUX('J', 6, ANALOG)>, /* LCD_R7 */
398	<STM32_PINMUX('J', 7, ANALOG)>, /* LCD_G0 */
399	<STM32_PINMUX('J', 8, ANALOG)>, /* LCD_G1 */
400	<STM32_PINMUX('J', 9, ANALOG)>, /* LCD_G2 */
401	<STM32_PINMUX('J', 10, ANALOG)>, /* LCD_G3 */
402	<STM32_PINMUX('J', 11, ANALOG)>, /* LCD_G4 */
403	<STM32_PINMUX('K', 0, ANALOG)>, /* LCD_G5 */
404	<STM32_PINMUX('K', 1, ANALOG)>, /* LCD_G6 */
405	<STM32_PINMUX('K', 2, ANALOG)>, /* LCD_G7 */
406	<STM32_PINMUX('J', 12, ANALOG)>, /* LCD_B0 */
407	<STM32_PINMUX('J', 13, ANALOG)>, /* LCD_B1 */
408	<STM32_PINMUX('J', 14, ANALOG)>, /* LCD_B2 */
409	<STM32_PINMUX('J', 15, ANALOG)>, /* LCD_B3 */
410	<STM32_PINMUX('K', 3, ANALOG)>, /* LCD_B4 */
411	<STM32_PINMUX('K', 4, ANALOG)>, /* LCD_B5 */
412	<STM32_PINMUX('K', 5, ANALOG)>, /* LCD_B6 */
413	<STM32_PINMUX('K', 6, ANALOG)>; /* LCD_B7 */
414	};
415	};
416
41cc73c5 ELR	417	m_can1_pins_a: m-can1-0 {
	418	pins1 {
	419	pinmux = <STM32_PINMUX('H', 13, AF9)>; /* CAN1_TX */
	420	slew-rate = <1>;
	421	drive-push-pull;
	422	bias-disable;
	423	};
	424	pins2 {
	425	pinmux = <STM32_PINMUX('I', 9, AF9)>; /* CAN1_RX */
	426	bias-disable;
	427	};
	428	};
	429
bb4857cd BH	430	m_can1_sleep_pins_a: m_can1-sleep@0 {
	431	pins {
	432	pinmux = <STM32_PINMUX('H', 13, ANALOG)>, /* CAN1_TX */
	433	<STM32_PINMUX('I', 9, ANALOG)>; /* CAN1_RX */
	434	};
	435	};
	436
52545823 FG	437	pwm2_pins_a: pwm2-0 {
	438	pins {
	439	pinmux = <STM32_PINMUX('A', 3, AF1)>; /* TIM2_CH4 */
	440	bias-pull-down;
	441	drive-push-pull;
	442	slew-rate = <0>;
	443	};
	444	};
	445
	446	pwm8_pins_a: pwm8-0 {
	447	pins {
	448	pinmux = <STM32_PINMUX('I', 2, AF3)>; /* TIM8_CH4 */
	449	bias-pull-down;
	450	drive-push-pull;
	451	slew-rate = <0>;
	452	};
	453	};
	454
	455	pwm12_pins_a: pwm12-0 {
	456	pins {
	457	pinmux = <STM32_PINMUX('H', 6, AF2)>; /* TIM12_CH1 */
	458	bias-pull-down;
	459	drive-push-pull;
	460	slew-rate = <0>;
	461	};
	462	};
	463
84403005 LB	464	qspi_clk_pins_a: qspi-clk-0 {
	465	pins {
	466	pinmux = <STM32_PINMUX('F', 10, AF9)>; /* QSPI_CLK */
	467	bias-disable;
	468	drive-push-pull;
	469	slew-rate = <3>;
	470	};
	471	};
	472
	473	qspi_bk1_pins_a: qspi-bk1-0 {
	474	pins1 {
	475	pinmux = <STM32_PINMUX('F', 8, AF10)>, /* QSPI_BK1_IO0 */
	476	<STM32_PINMUX('F', 9, AF10)>, /* QSPI_BK1_IO1 */
	477	<STM32_PINMUX('F', 7, AF9)>, /* QSPI_BK1_IO2 */
	478	<STM32_PINMUX('F', 6, AF9)>; /* QSPI_BK1_IO3 */
	479	bias-disable;
	480	drive-push-pull;
	481	slew-rate = <3>;
	482	};
	483	pins2 {
	484	pinmux = <STM32_PINMUX('B', 6, AF10)>; /* QSPI_BK1_NCS */
	485	bias-pull-up;
	486	drive-push-pull;
	487	slew-rate = <3>;
	488	};
	489	};
	490
	491	qspi_bk2_pins_a: qspi-bk2-0 {
	492	pins1 {
	493	pinmux = <STM32_PINMUX('H', 2, AF9)>, /* QSPI_BK2_IO0 */
	494	<STM32_PINMUX('H', 3, AF9)>, /* QSPI_BK2_IO1 */
	495	<STM32_PINMUX('G', 10, AF11)>, /* QSPI_BK2_IO2 */
	496	<STM32_PINMUX('G', 7, AF11)>; /* QSPI_BK2_IO3 */
	497	bias-disable;
	498	drive-push-pull;
	499	slew-rate = <3>;
	500	};
	501	pins2 {
	502	pinmux = <STM32_PINMUX('C', 0, AF10)>; /* QSPI_BK2_NCS */
	503	bias-pull-up;
	504	drive-push-pull;
	505	slew-rate = <3>;
	506	};
	507	};
	508
379edbe4 LB	509	sdmmc1_b4_pins_a: sdmmc1-b4-0 {
	510	pins {
	511	pinmux = <STM32_PINMUX('C', 8, AF12)>, /* SDMMC1_D0 */
	512	<STM32_PINMUX('C', 9, AF12)>, /* SDMMC1_D1 */
	513	<STM32_PINMUX('C', 10, AF12)>, /* SDMMC1_D2 */
	514	<STM32_PINMUX('C', 11, AF12)>, /* SDMMC1_D3 */
	515	<STM32_PINMUX('C', 12, AF12)>, /* SDMMC1_CK */
	516	<STM32_PINMUX('D', 2, AF12)>; /* SDMMC1_CMD */
	517	slew-rate = <3>;
	518	drive-push-pull;
	519	bias-disable;
	520	};
	521	};
	522
	523	sdmmc1_b4_od_pins_a: sdmmc1-b4-od-0 {
	524	pins1 {
	525	pinmux = <STM32_PINMUX('C', 8, AF12)>, /* SDMMC1_D0 */
	526	<STM32_PINMUX('C', 9, AF12)>, /* SDMMC1_D1 */
	527	<STM32_PINMUX('C', 10, AF12)>, /* SDMMC1_D2 */
	528	<STM32_PINMUX('C', 11, AF12)>, /* SDMMC1_D3 */
	529	<STM32_PINMUX('C', 12, AF12)>; /* SDMMC1_CK */
	530	slew-rate = <3>;
	531	drive-push-pull;
	532	bias-disable;
	533	};
	534	pins2{
	535	pinmux = <STM32_PINMUX('D', 2, AF12)>; /* SDMMC1_CMD */
	536	slew-rate = <3>;
	537	drive-open-drain;
	538	bias-disable;
	539	};
	540	};
	541
	542	sdmmc1_b4_sleep_pins_a: sdmmc1-b4-sleep-0 {
	543	pins {
	544	pinmux = <STM32_PINMUX('C', 8, ANALOG)>, /* SDMMC1_D0 */
	545	<STM32_PINMUX('C', 9, ANALOG)>, /* SDMMC1_D1 */
	546	<STM32_PINMUX('C', 10, ANALOG)>, /* SDMMC1_D2 */
	547	<STM32_PINMUX('C', 11, ANALOG)>, /* SDMMC1_D3 */
	548	<STM32_PINMUX('C', 12, ANALOG)>, /* SDMMC1_CK */
	549	<STM32_PINMUX('D', 2, ANALOG)>; /* SDMMC1_CMD */
	550	};
	551	};
	552
	553	sdmmc1_dir_pins_a: sdmmc1-dir-0 {
	554	pins1 {
	555	pinmux = <STM32_PINMUX('F', 2, AF11)>, /* SDMMC1_D0DIR */
	556	<STM32_PINMUX('C', 7, AF8)>, /* SDMMC1_D123DIR */
	557	<STM32_PINMUX('B', 9, AF11)>; /* SDMMC1_CDIR */
	558	slew-rate = <3>;
	559	drive-push-pull;
	560	bias-pull-up;
	561	};
	562	pins2{
	563	pinmux = <STM32_PINMUX('E', 4, AF8)>; /* SDMMC1_CKIN */
	564	bias-pull-up;
	565	};
	566	};
	567
	568	sdmmc1_dir_sleep_pins_a: sdmmc1-dir-sleep-0 {
	569	pins {
	570	pinmux = <STM32_PINMUX('F', 2, ANALOG)>, /* SDMMC1_D0DIR */
	571	<STM32_PINMUX('C', 7, ANALOG)>, /* SDMMC1_D123DIR */
	572	<STM32_PINMUX('B', 9, ANALOG)>, /* SDMMC1_CDIR */
573	<STM32_PINMUX('E', 4, ANALOG)>; /* SDMMC1_CKIN */
574	};
575	};
576
94d3d6f4 OM	577	spdifrx_pins_a: spdifrx-0 {
	578	pins {
	579	pinmux = <STM32_PINMUX('G', 12, AF8)>; /* SPDIF_IN1 */
	580	bias-disable;
	581	};
	582	};
	583
	584	spdifrx_sleep_pins_a: spdifrx-1 {
	585	pins {
	586	pinmux = <STM32_PINMUX('G', 12, ANALOG)>; /* SPDIF_IN1 */
	587	};
	588	};
	589
20ab2d88	590	uart4_pins_a: uart4-0 {
bcc4f4e1 LB	591	pins1 {
	592	pinmux = <STM32_PINMUX('G', 11, AF6)>; /* UART4_TX */
	593	bias-disable;
	594	drive-push-pull;
	595	slew-rate = <0>;
	596	};
	597	pins2 {
	598	pinmux = <STM32_PINMUX('B', 2, AF8)>; /* UART4_RX */
	599	bias-disable;
	600	};
	601	};
8471a202 LB	602	};
8471a202 LB	603
20ab2d88	604	pinctrl_z: pin-controller-z@54004000 {
8471a202 LB	605	#address-cells = <1>;
	606	#size-cells = <1>;
	607	compatible = "st,stm32mp157-z-pinctrl";
	608	ranges = <0 0x54004000 0x400>;
	609	pins-are-numbered;
6a88c221 LB	610	interrupt-parent = <&exti>;
6a88c221 LB	611	st,syscfg = <&exti 0x60 0xff>;
8471a202 LB	612
	613	gpioz: gpio@54004000 {
	614	gpio-controller;
	615	#gpio-cells = <2>;
	616	interrupt-controller;
	617	#interrupt-cells = <2>;
	618	reg = <0 0x400>;
3599a8af	619	clocks = <&rcc GPIOZ>;
8471a202 LB	620	st,bank-name = "GPIOZ";
	621	st,bank-ioport = <11>;
	622	ngpios = <8>;
	623	gpio-ranges = <&pinctrl_z 0 400 8>;
	624	};
4d58a474 PYM	625
	626	i2c4_pins_a: i2c4-0 {
	627	pins {
	628	pinmux = <STM32_PINMUX('Z', 4, AF6)>, /* I2C4_SCL */
	629	<STM32_PINMUX('Z', 5, AF6)>; /* I2C4_SDA */
	630	bias-disable;
	631	drive-open-drain;
	632	slew-rate = <0>;
	633	};
	634	};
7e29ed4a	635
f85c8acc YF	636	i2c4_pins_sleep_a: i2c4-1 {
	637	pins {
	638	pinmux = <STM32_PINMUX('Z', 4, ANALOG)>, /* I2C4_SCL */
	639	<STM32_PINMUX('Z', 5, ANALOG)>; /* I2C4_SDA */
	640	};
	641	};
	642
7e29ed4a AD	643	spi1_pins_a: spi1-0 {
	644	pins1 {
	645	pinmux = <STM32_PINMUX('Z', 0, AF5)>, /* SPI1_SCK */
	646	<STM32_PINMUX('Z', 2, AF5)>; /* SPI1_MOSI */
	647	bias-disable;
	648	drive-push-pull;
	649	slew-rate = <1>;
	650	};
	651
	652	pins2 {
	653	pinmux = <STM32_PINMUX('Z', 1, AF5)>; /* SPI1_MISO */
	654	bias-disable;
	655	};
	656	};
8471a202 LB	657	};
	658	};
	659	};