[linux-block.git] / arch / arm / boot / dts / stm32h743.dtsi

/*
 * Copyright 2017 - Alexandre Torgue <alexandre.torgue@st.com>
 *
 * This file is dual-licensed: you can use it either under the terms
 * of the GPL or the X11 license, at your option. Note that this dual
 * licensing only applies to this file, and not this project as a
 * whole.
 *
 *  a) This file is free software; you can redistribute it and/or
 *     modify it under the terms of the GNU General Public License as
 *     published by the Free Software Foundation; either version 2 of the
 *     License, or (at your option) any later version.
 *
 *     This file is distributed in the hope that it will be useful,
 *     but WITHOUT ANY WARRANTY; without even the implied warranty of
 *     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 *     GNU General Public License for more details.
 *
 * Or, alternatively,
 *
 *  b) Permission is hereby granted, free of charge, to any person
 *     obtaining a copy of this software and associated documentation
 *     files (the "Software"), to deal in the Software without
 *     restriction, including without limitation the rights to use,
 *     copy, modify, merge, publish, distribute, sublicense, and/or
 *     sell copies of the Software, and to permit persons to whom the
 *     Software is furnished to do so, subject to the following
 *     conditions:
 *
 *     The above copyright notice and this permission notice shall be
 *     included in all copies or substantial portions of the Software.
 *
 *     THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
 *     EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
 *     OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
 *     NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
 *     HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
 *     WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
 *     FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
 *     OTHER DEALINGS IN THE SOFTWARE.
 */

#include "skeleton.dtsi"
#include "armv7-m.dtsi"
#include <dt-bindings/clock/stm32h7-clks.h>
#include <dt-bindings/mfd/stm32h7-rcc.h>

/ {
	clocks {
		clk_hse: clk-hse {
			#clock-cells = <0>;
			compatible = "fixed-clock";
			clock-frequency = <0>;
		};

		clk_lse: clk-lse {
			#clock-cells = <0>;
			compatible = "fixed-clock";
			clock-frequency = <32768>;
		};

		clk_i2s: i2s_ckin {
			#clock-cells = <0>;
			compatible = "fixed-clock";
			clock-frequency = <0>;
		};
	};

	soc {
		timer5: timer@40000c00 {
			compatible = "st,stm32-timer";
			reg = <0x40000c00 0x400>;
			interrupts = <50>;
			clocks = <&rcc TIM5_CK>;
		};

		lptimer1: timer@40002400 {
			#address-cells = <1>;
			#size-cells = <0>;
			compatible = "st,stm32-lptimer";
			reg = <0x40002400 0x400>;
			clocks = <&rcc LPTIM1_CK>;
			clock-names = "mux";
			status = "disabled";

			pwm {
				compatible = "st,stm32-pwm-lp";
				status = "disabled";
			};

			trigger@0 {
				compatible = "st,stm32-lptimer-trigger";
				reg = <0>;
				status = "disabled";
			};

			counter {
				compatible = "st,stm32-lptimer-counter";
				status = "disabled";
			};
		};

		usart2: serial@40004400 {
			compatible = "st,stm32f7-uart";
			reg = <0x40004400 0x400>;
			interrupts = <38>;
			status = "disabled";
			clocks = <&rcc USART2_CK>;
		};

		dac: dac@40007400 {
			compatible = "st,stm32h7-dac-core";
			reg = <0x40007400 0x400>;
			clocks = <&rcc DAC12_CK>;
			clock-names = "pclk";
			#address-cells = <1>;
			#size-cells = <0>;
			status = "disabled";

			dac1: dac@1 {
				compatible = "st,stm32-dac";
				#io-channels-cells = <1>;
				reg = <1>;
				status = "disabled";
			};

			dac2: dac@2 {
				compatible = "st,stm32-dac";
				#io-channels-cells = <1>;
				reg = <2>;
				status = "disabled";
			};
		};

		usart1: serial@40011000 {
			compatible = "st,stm32f7-uart";
			reg = <0x40011000 0x400>;
			interrupts = <37>;
			status = "disabled";
			clocks = <&rcc USART1_CK>;
		};

		dma1: dma@40020000 {
			compatible = "st,stm32-dma";
			reg = <0x40020000 0x400>;
			interrupts = <11>,
				     <12>,
				     <13>,
				     <14>,
				     <15>,
				     <16>,
				     <17>,
				     <47>;
			clocks = <&rcc DMA1_CK>;
			#dma-cells = <4>;
			st,mem2mem;
			dma-requests = <8>;
			status = "disabled";
		};

		dma2: dma@40020400 {
			compatible = "st,stm32-dma";
			reg = <0x40020400 0x400>;
			interrupts = <56>,
				     <57>,
				     <58>,
				     <59>,
				     <60>,
				     <68>,
				     <69>,
				     <70>;
			clocks = <&rcc DMA2_CK>;
			#dma-cells = <4>;
			st,mem2mem;
			dma-requests = <8>;
			status = "disabled";
		};

		dmamux1: dma-router@40020800 {
			compatible = "st,stm32h7-dmamux";
			reg = <0x40020800 0x1c>;
			#dma-cells = <3>;
			dma-channels = <16>;
			dma-requests = <128>;
			dma-masters = <&dma1 &dma2>;
			clocks = <&rcc DMA1_CK>;
		};

		adc_12: adc@40022000 {
			compatible = "st,stm32h7-adc-core";
			reg = <0x40022000 0x400>;
			interrupts = <18>;
			clocks = <&rcc ADC12_CK>;
			clock-names = "bus";
			interrupt-controller;
			#interrupt-cells = <1>;
			#address-cells = <1>;
			#size-cells = <0>;
			status = "disabled";

			adc1: adc@0 {
				compatible = "st,stm32h7-adc";
				#io-channel-cells = <1>;
				reg = <0x0>;
				interrupt-parent = <&adc_12>;
				interrupts = <0>;
				status = "disabled";
			};

			adc2: adc@100 {
				compatible = "st,stm32h7-adc";
				#io-channel-cells = <1>;
				reg = <0x100>;
				interrupt-parent = <&adc_12>;
				interrupts = <1>;
				status = "disabled";
			};
		};

		mdma1: dma@52000000 {
			compatible = "st,stm32h7-mdma";
			reg = <0x52000000 0x1000>;
			interrupts = <122>;
			clocks = <&rcc MDMA_CK>;
			#dma-cells = <5>;
			dma-channels = <16>;
			dma-requests = <32>;
		};

		lptimer2: timer@58002400 {
			#address-cells = <1>;
			#size-cells = <0>;
			compatible = "st,stm32-lptimer";
			reg = <0x58002400 0x400>;
			clocks = <&rcc LPTIM2_CK>;
			clock-names = "mux";
			status = "disabled";

			pwm {
				compatible = "st,stm32-pwm-lp";
				status = "disabled";
			};

			trigger@1 {
				compatible = "st,stm32-lptimer-trigger";
				reg = <1>;
				status = "disabled";
			};

			counter {
				compatible = "st,stm32-lptimer-counter";
				status = "disabled";
			};
		};

		lptimer3: timer@58002800 {
			#address-cells = <1>;
			#size-cells = <0>;
			compatible = "st,stm32-lptimer";
			reg = <0x58002800 0x400>;
			clocks = <&rcc LPTIM3_CK>;
			clock-names = "mux";
			status = "disabled";

			pwm {
				compatible = "st,stm32-pwm-lp";
				status = "disabled";
			};

			trigger@2 {
				compatible = "st,stm32-lptimer-trigger";
				reg = <2>;
				status = "disabled";
			};
		};

		lptimer4: timer@58002c00 {
			#address-cells = <1>;
			#size-cells = <0>;
			compatible = "st,stm32-lptimer";
			reg = <0x58002c00 0x400>;
			clocks = <&rcc LPTIM4_CK>;
			clock-names = "mux";
			status = "disabled";

			pwm {
				compatible = "st,stm32-pwm-lp";
				status = "disabled";
			};
		};

		lptimer5: timer@58003000 {
			#address-cells = <1>;
			#size-cells = <0>;
			compatible = "st,stm32-lptimer";
			reg = <0x58003000 0x400>;
			clocks = <&rcc LPTIM5_CK>;
			clock-names = "mux";
			status = "disabled";

			pwm {
				compatible = "st,stm32-pwm-lp";
				status = "disabled";
			};
		};

		vrefbuf: regulator@58003C00 {
			compatible = "st,stm32-vrefbuf";
			reg = <0x58003C00 0x8>;
			clocks = <&rcc VREF_CK>;
			regulator-min-microvolt = <1500000>;
			regulator-max-microvolt = <2500000>;
			status = "disabled";
		};

		rcc: reset-clock-controller@58024400 {
			compatible = "st,stm32h743-rcc", "st,stm32-rcc";
			reg = <0x58024400 0x400>;
			#clock-cells = <1>;
			#reset-cells = <1>;
			clocks = <&clk_hse>, <&clk_lse>, <&clk_i2s>;
			st,syscfg = <&pwrcfg>;
		};

		pwrcfg: power-config@58024800 {
			compatible = "syscon";
			reg = <0x58024800 0x400>;
		};

		adc_3: adc@58026000 {
			compatible = "st,stm32h7-adc-core";
			reg = <0x58026000 0x400>;
			interrupts = <127>;
			clocks = <&rcc ADC3_CK>;
			clock-names = "bus";
			interrupt-controller;
			#interrupt-cells = <1>;
			#address-cells = <1>;
			#size-cells = <0>;
			status = "disabled";

			adc3: adc@0 {
				compatible = "st,stm32h7-adc";
				#io-channel-cells = <1>;
				reg = <0x0>;
				interrupt-parent = <&adc_3>;
				interrupts = <0>;
				status = "disabled";
			};
		};
	};
};

&systick {
	clock-frequency = <250000000>;
	status = "okay";
};
Commit	Line	Data
500cdb23 AT	1	/*
	2	* Copyright 2017 - Alexandre Torgue <alexandre.torgue@st.com>
	3	*
	4	* This file is dual-licensed: you can use it either under the terms
	5	* of the GPL or the X11 license, at your option. Note that this dual
	6	* licensing only applies to this file, and not this project as a
	7	* whole.
	8	*
	9	* a) This file is free software; you can redistribute it and/or
	10	* modify it under the terms of the GNU General Public License as
	11	* published by the Free Software Foundation; either version 2 of the
	12	* License, or (at your option) any later version.
	13	*
	14	* This file is distributed in the hope that it will be useful,
	15	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	16	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	17	* GNU General Public License for more details.
	18	*
	19	* Or, alternatively,
	20	*
	21	* b) Permission is hereby granted, free of charge, to any person
	22	* obtaining a copy of this software and associated documentation
	23	* files (the "Software"), to deal in the Software without
	24	* restriction, including without limitation the rights to use,
	25	* copy, modify, merge, publish, distribute, sublicense, and/or
	26	* sell copies of the Software, and to permit persons to whom the
	27	* Software is furnished to do so, subject to the following
	28	* conditions:
	29	*
	30	* The above copyright notice and this permission notice shall be
	31	* included in all copies or substantial portions of the Software.
	32	*
	33	* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
	34	* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
	35	* OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
	36	* NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
	37	* HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
	38	* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
	39	* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
	40	* OTHER DEALINGS IN THE SOFTWARE.
	41	*/
	42
	43	#include "skeleton.dtsi"
	44	#include "armv7-m.dtsi"
6d3b3745 GF	45	#include <dt-bindings/clock/stm32h7-clks.h>
6d3b3745 GF	46	#include <dt-bindings/mfd/stm32h7-rcc.h>
500cdb23 AT	47
	48	/ {
	49	clocks {
	50	clk_hse: clk-hse {
	51	#clock-cells = <0>;
	52	compatible = "fixed-clock";
	53	clock-frequency = <0>;
	54	};
	55
6d3b3745	56	clk_lse: clk-lse {
500cdb23 AT	57	#clock-cells = <0>;
500cdb23 AT	58	compatible = "fixed-clock";
6d3b3745 GF	59	clock-frequency = <32768>;
	60	};
	61
	62	clk_i2s: i2s_ckin {
	63	#clock-cells = <0>;
	64	compatible = "fixed-clock";
	65	clock-frequency = <0>;
500cdb23 AT	66	};
	67	};
	68
	69	soc {
978edf15 AT	70	timer5: timer@40000c00 {
	71	compatible = "st,stm32-timer";
	72	reg = <0x40000c00 0x400>;
	73	interrupts = <50>;
6d3b3745	74	clocks = <&rcc TIM5_CK>;
500cdb23 AT	75	};
500cdb23 AT	76
74f4c322 FG	77	lptimer1: timer@40002400 {
	78	#address-cells = <1>;
	79	#size-cells = <0>;
	80	compatible = "st,stm32-lptimer";
	81	reg = <0x40002400 0x400>;
6d3b3745	82	clocks = <&rcc LPTIM1_CK>;
74f4c322 FG	83	clock-names = "mux";
	84	status = "disabled";
	85
	86	pwm {
	87	compatible = "st,stm32-pwm-lp";
	88	status = "disabled";
	89	};
	90
	91	trigger@0 {
	92	compatible = "st,stm32-lptimer-trigger";
	93	reg = <0>;
	94	status = "disabled";
	95	};
	96
	97	counter {
	98	compatible = "st,stm32-lptimer-counter";
	99	status = "disabled";
	100	};
500cdb23 AT	101	};
500cdb23 AT	102
a56678cd	103	usart2: serial@40004400 {
6c7b8412	104	compatible = "st,stm32f7-uart";
a56678cd PC	105	reg = <0x40004400 0x400>;
	106	interrupts = <38>;
	107	status = "disabled";
6d3b3745	108	clocks = <&rcc USART2_CK>;
a56678cd PC	109	};
a56678cd PC	110
1536dec4 FG	111	dac: dac@40007400 {
	112	compatible = "st,stm32h7-dac-core";
	113	reg = <0x40007400 0x400>;
6d3b3745	114	clocks = <&rcc DAC12_CK>;
1536dec4 FG	115	clock-names = "pclk";
	116	#address-cells = <1>;
	117	#size-cells = <0>;
	118	status = "disabled";
	119
	120	dac1: dac@1 {
	121	compatible = "st,stm32-dac";
	122	#io-channels-cells = <1>;
	123	reg = <1>;
	124	status = "disabled";
	125	};
	126
	127	dac2: dac@2 {
	128	compatible = "st,stm32-dac";
	129	#io-channels-cells = <1>;
	130	reg = <2>;
	131	status = "disabled";
	132	};
	133	};
	134
978edf15	135	usart1: serial@40011000 {
6c7b8412	136	compatible = "st,stm32f7-uart";
978edf15 AT	137	reg = <0x40011000 0x400>;
	138	interrupts = <37>;
	139	status = "disabled";
6d3b3745	140	clocks = <&rcc USART1_CK>;
500cdb23	141	};
079af0c4	142
01d281b6 PYM	143	dma1: dma@40020000 {
	144	compatible = "st,stm32-dma";
	145	reg = <0x40020000 0x400>;
	146	interrupts = <11>,
	147	<12>,
	148	<13>,
	149	<14>,
	150	<15>,
	151	<16>,
	152	<17>,
	153	<47>;
6d3b3745	154	clocks = <&rcc DMA1_CK>;
01d281b6 PYM	155	#dma-cells = <4>;
01d281b6 PYM	156	st,mem2mem;
e40992cb	157	dma-requests = <8>;
01d281b6 PYM	158	status = "disabled";
	159	};
	160
	161	dma2: dma@40020400 {
	162	compatible = "st,stm32-dma";
	163	reg = <0x40020400 0x400>;
	164	interrupts = <56>,
	165	<57>,
	166	<58>,
	167	<59>,
	168	<60>,
	169	<68>,
	170	<69>,
	171	<70>;
6d3b3745	172	clocks = <&rcc DMA2_CK>;
01d281b6 PYM	173	#dma-cells = <4>;
01d281b6 PYM	174	st,mem2mem;
e40992cb	175	dma-requests = <8>;
01d281b6 PYM	176	status = "disabled";
	177	};
	178
e40992cb PYM	179	dmamux1: dma-router@40020800 {
	180	compatible = "st,stm32h7-dmamux";
	181	reg = <0x40020800 0x1c>;
	182	#dma-cells = <3>;
	183	dma-channels = <16>;
	184	dma-requests = <128>;
	185	dma-masters = <&dma1 &dma2>;
6d3b3745	186	clocks = <&rcc DMA1_CK>;
e40992cb PYM	187	};
e40992cb PYM	188
079af0c4 FG	189	adc_12: adc@40022000 {
	190	compatible = "st,stm32h7-adc-core";
	191	reg = <0x40022000 0x400>;
	192	interrupts = <18>;
6d3b3745	193	clocks = <&rcc ADC12_CK>;
079af0c4 FG	194	clock-names = "bus";
	195	interrupt-controller;
	196	#interrupt-cells = <1>;
	197	#address-cells = <1>;
	198	#size-cells = <0>;
	199	status = "disabled";
	200
	201	adc1: adc@0 {
	202	compatible = "st,stm32h7-adc";
	203	#io-channel-cells = <1>;
	204	reg = <0x0>;
	205	interrupt-parent = <&adc_12>;
	206	interrupts = <0>;
	207	status = "disabled";
	208	};
	209
	210	adc2: adc@100 {
	211	compatible = "st,stm32h7-adc";
	212	#io-channel-cells = <1>;
	213	reg = <0x100>;
	214	interrupt-parent = <&adc_12>;
	215	interrupts = <1>;
	216	status = "disabled";
	217	};
	218	};
	219
4bd93eb3 PYM	220	mdma1: dma@52000000 {
	221	compatible = "st,stm32h7-mdma";
	222	reg = <0x52000000 0x1000>;
	223	interrupts = <122>;
	224	clocks = <&rcc MDMA_CK>;
	225	#dma-cells = <5>;
	226	dma-channels = <16>;
	227	dma-requests = <32>;
	228	};
	229
74f4c322 FG	230	lptimer2: timer@58002400 {
	231	#address-cells = <1>;
	232	#size-cells = <0>;
	233	compatible = "st,stm32-lptimer";
	234	reg = <0x58002400 0x400>;
6d3b3745	235	clocks = <&rcc LPTIM2_CK>;
74f4c322 FG	236	clock-names = "mux";
	237	status = "disabled";
	238
	239	pwm {
	240	compatible = "st,stm32-pwm-lp";
	241	status = "disabled";
	242	};
	243
	244	trigger@1 {
	245	compatible = "st,stm32-lptimer-trigger";
	246	reg = <1>;
	247	status = "disabled";
	248	};
	249
	250	counter {
	251	compatible = "st,stm32-lptimer-counter";
	252	status = "disabled";
	253	};
	254	};
	255
	256	lptimer3: timer@58002800 {
	257	#address-cells = <1>;
	258	#size-cells = <0>;
	259	compatible = "st,stm32-lptimer";
	260	reg = <0x58002800 0x400>;
6d3b3745	261	clocks = <&rcc LPTIM3_CK>;
74f4c322 FG	262	clock-names = "mux";
	263	status = "disabled";
	264
	265	pwm {
	266	compatible = "st,stm32-pwm-lp";
	267	status = "disabled";
	268	};
	269
	270	trigger@2 {
	271	compatible = "st,stm32-lptimer-trigger";
	272	reg = <2>;
	273	status = "disabled";
	274	};
	275	};
	276
	277	lptimer4: timer@58002c00 {
	278	#address-cells = <1>;
	279	#size-cells = <0>;
	280	compatible = "st,stm32-lptimer";
	281	reg = <0x58002c00 0x400>;
6d3b3745	282	clocks = <&rcc LPTIM4_CK>;
74f4c322 FG	283	clock-names = "mux";
	284	status = "disabled";
	285
	286	pwm {
	287	compatible = "st,stm32-pwm-lp";
	288	status = "disabled";
	289	};
	290	};
	291
	292	lptimer5: timer@58003000 {
	293	#address-cells = <1>;
	294	#size-cells = <0>;
	295	compatible = "st,stm32-lptimer";
	296	reg = <0x58003000 0x400>;
6d3b3745	297	clocks = <&rcc LPTIM5_CK>;
74f4c322 FG	298	clock-names = "mux";
	299	status = "disabled";
	300
	301	pwm {
	302	compatible = "st,stm32-pwm-lp";
	303	status = "disabled";
	304	};
	305	};
	306
846f2f1c FG	307	vrefbuf: regulator@58003C00 {
	308	compatible = "st,stm32-vrefbuf";
	309	reg = <0x58003C00 0x8>;
6d3b3745	310	clocks = <&rcc VREF_CK>;
846f2f1c FG	311	regulator-min-microvolt = <1500000>;
	312	regulator-max-microvolt = <2500000>;
	313	status = "disabled";
	314	};
	315
6d3b3745 GF	316	rcc: reset-clock-controller@58024400 {
	317	compatible = "st,stm32h743-rcc", "st,stm32-rcc";
	318	reg = <0x58024400 0x400>;
	319	#clock-cells = <1>;
	320	#reset-cells = <1>;
	321	clocks = <&clk_hse>, <&clk_lse>, <&clk_i2s>;
	322	st,syscfg = <&pwrcfg>;
	323	};
	324
	325	pwrcfg: power-config@58024800 {
	326	compatible = "syscon";
	327	reg = <0x58024800 0x400>;
	328	};
	329
079af0c4 FG	330	adc_3: adc@58026000 {
	331	compatible = "st,stm32h7-adc-core";
	332	reg = <0x58026000 0x400>;
	333	interrupts = <127>;
6d3b3745	334	clocks = <&rcc ADC3_CK>;
079af0c4 FG	335	clock-names = "bus";
	336	interrupt-controller;
	337	#interrupt-cells = <1>;
	338	#address-cells = <1>;
	339	#size-cells = <0>;
	340	status = "disabled";
	341
	342	adc3: adc@0 {
	343	compatible = "st,stm32h7-adc";
	344	#io-channel-cells = <1>;
	345	reg = <0x0>;
	346	interrupt-parent = <&adc_3>;
	347	interrupts = <0>;
	348	status = "disabled";
	349	};
	350	};
500cdb23 AT	351	};
	352	};
	353
	354	&systick {
	355	clock-frequency = <250000000>;
	356	status = "okay";
	357	};