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338a6aaa MC |
1 | /* |
2 | * Copyright 2015 - Maxime Coquelin <mcoquelin.stm32@gmail.com> | |
3 | * | |
4 | * This file is dual-licensed: you can use it either under the terms | |
5 | * of the GPL or the X11 license, at your option. Note that this dual | |
6 | * licensing only applies to this file, and not this project as a | |
7 | * whole. | |
8 | * | |
9 | * a) This file is free software; you can redistribute it and/or | |
10 | * modify it under the terms of the GNU General Public License as | |
11 | * published by the Free Software Foundation; either version 2 of the | |
12 | * License, or (at your option) any later version. | |
13 | * | |
14 | * This file is distributed in the hope that it will be useful, | |
15 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
16 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
17 | * GNU General Public License for more details. | |
18 | * | |
19 | * You should have received a copy of the GNU General Public | |
20 | * License along with this file; if not, write to the Free | |
21 | * Software Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, | |
22 | * MA 02110-1301 USA | |
23 | * | |
24 | * Or, alternatively, | |
25 | * | |
26 | * b) Permission is hereby granted, free of charge, to any person | |
27 | * obtaining a copy of this software and associated documentation | |
28 | * files (the "Software"), to deal in the Software without | |
29 | * restriction, including without limitation the rights to use, | |
30 | * copy, modify, merge, publish, distribute, sublicense, and/or | |
31 | * sell copies of the Software, and to permit persons to whom the | |
32 | * Software is furnished to do so, subject to the following | |
33 | * conditions: | |
34 | * | |
35 | * The above copyright notice and this permission notice shall be | |
36 | * included in all copies or substantial portions of the Software. | |
37 | * | |
38 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, | |
39 | * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES | |
40 | * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND | |
41 | * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT | |
42 | * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, | |
43 | * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING | |
44 | * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR | |
45 | * OTHER DEALINGS IN THE SOFTWARE. | |
46 | */ | |
47 | ||
05b23ebc | 48 | #include "skeleton.dtsi" |
338a6aaa | 49 | #include "armv7-m.dtsi" |
2dbd0593 | 50 | #include <dt-bindings/pinctrl/stm32f429-pinfunc.h> |
2da751b0 | 51 | #include <dt-bindings/clock/stm32fx-clock.h> |
f20a406b | 52 | #include <dt-bindings/mfd/stm32f4-rcc.h> |
338a6aaa MC |
53 | |
54 | / { | |
55 | clocks { | |
9dc24a2d | 56 | clk_hse: clk-hse { |
338a6aaa MC |
57 | #clock-cells = <0>; |
58 | compatible = "fixed-clock"; | |
9dc24a2d | 59 | clock-frequency = <0>; |
338a6aaa | 60 | }; |
f6dbbff4 GF |
61 | |
62 | clk-lse { | |
63 | #clock-cells = <0>; | |
64 | compatible = "fixed-clock"; | |
65 | clock-frequency = <32768>; | |
66 | }; | |
67 | ||
68 | clk-lsi { | |
69 | #clock-cells = <0>; | |
70 | compatible = "fixed-clock"; | |
71 | clock-frequency = <32000>; | |
72 | }; | |
305b0495 GF |
73 | |
74 | clk_i2s_ckin: i2s-ckin { | |
75 | #clock-cells = <0>; | |
76 | compatible = "fixed-clock"; | |
77 | clock-frequency = <0>; | |
78 | }; | |
338a6aaa MC |
79 | }; |
80 | ||
81 | soc { | |
82 | timer2: timer@40000000 { | |
83 | compatible = "st,stm32-timer"; | |
84 | reg = <0x40000000 0x400>; | |
85 | interrupts = <28>; | |
f20a406b | 86 | clocks = <&rcc 0 STM32F4_APB1_CLOCK(TIM2)>; |
338a6aaa MC |
87 | status = "disabled"; |
88 | }; | |
89 | ||
c0e14fc7 BG |
90 | timers2: timers@40000000 { |
91 | #address-cells = <1>; | |
92 | #size-cells = <0>; | |
93 | compatible = "st,stm32-timers"; | |
94 | reg = <0x40000000 0x400>; | |
f20a406b | 95 | clocks = <&rcc 0 STM32F4_APB1_CLOCK(TIM2)>; |
c0e14fc7 BG |
96 | clock-names = "int"; |
97 | status = "disabled"; | |
98 | ||
99 | pwm { | |
100 | compatible = "st,stm32-pwm"; | |
101 | status = "disabled"; | |
102 | }; | |
103 | ||
104 | timer@1 { | |
105 | compatible = "st,stm32-timer-trigger"; | |
106 | reg = <1>; | |
107 | status = "disabled"; | |
108 | }; | |
109 | }; | |
110 | ||
338a6aaa MC |
111 | timer3: timer@40000400 { |
112 | compatible = "st,stm32-timer"; | |
113 | reg = <0x40000400 0x400>; | |
114 | interrupts = <29>; | |
f20a406b | 115 | clocks = <&rcc 0 STM32F4_APB1_CLOCK(TIM3)>; |
338a6aaa MC |
116 | status = "disabled"; |
117 | }; | |
118 | ||
c0e14fc7 BG |
119 | timers3: timers@40000400 { |
120 | #address-cells = <1>; | |
121 | #size-cells = <0>; | |
122 | compatible = "st,stm32-timers"; | |
123 | reg = <0x40000400 0x400>; | |
f20a406b | 124 | clocks = <&rcc 0 STM32F4_APB1_CLOCK(TIM3)>; |
c0e14fc7 BG |
125 | clock-names = "int"; |
126 | status = "disabled"; | |
127 | ||
128 | pwm { | |
129 | compatible = "st,stm32-pwm"; | |
130 | status = "disabled"; | |
131 | }; | |
132 | ||
133 | timer@2 { | |
134 | compatible = "st,stm32-timer-trigger"; | |
135 | reg = <2>; | |
136 | status = "disabled"; | |
137 | }; | |
138 | }; | |
139 | ||
338a6aaa MC |
140 | timer4: timer@40000800 { |
141 | compatible = "st,stm32-timer"; | |
142 | reg = <0x40000800 0x400>; | |
143 | interrupts = <30>; | |
f20a406b | 144 | clocks = <&rcc 0 STM32F4_APB1_CLOCK(TIM4)>; |
338a6aaa MC |
145 | status = "disabled"; |
146 | }; | |
147 | ||
c0e14fc7 BG |
148 | timers4: timers@40000800 { |
149 | #address-cells = <1>; | |
150 | #size-cells = <0>; | |
151 | compatible = "st,stm32-timers"; | |
152 | reg = <0x40000800 0x400>; | |
f20a406b | 153 | clocks = <&rcc 0 STM32F4_APB1_CLOCK(TIM4)>; |
c0e14fc7 BG |
154 | clock-names = "int"; |
155 | status = "disabled"; | |
156 | ||
157 | pwm { | |
158 | compatible = "st,stm32-pwm"; | |
159 | status = "disabled"; | |
160 | }; | |
161 | ||
162 | timer@3 { | |
163 | compatible = "st,stm32-timer-trigger"; | |
164 | reg = <3>; | |
165 | status = "disabled"; | |
166 | }; | |
167 | }; | |
168 | ||
338a6aaa MC |
169 | timer5: timer@40000c00 { |
170 | compatible = "st,stm32-timer"; | |
171 | reg = <0x40000c00 0x400>; | |
172 | interrupts = <50>; | |
f20a406b | 173 | clocks = <&rcc 0 STM32F4_APB1_CLOCK(TIM5)>; |
338a6aaa MC |
174 | }; |
175 | ||
c0e14fc7 BG |
176 | timers5: timers@40000c00 { |
177 | #address-cells = <1>; | |
178 | #size-cells = <0>; | |
179 | compatible = "st,stm32-timers"; | |
180 | reg = <0x40000C00 0x400>; | |
f20a406b | 181 | clocks = <&rcc 0 STM32F4_APB1_CLOCK(TIM5)>; |
c0e14fc7 BG |
182 | clock-names = "int"; |
183 | status = "disabled"; | |
184 | ||
185 | pwm { | |
186 | compatible = "st,stm32-pwm"; | |
187 | status = "disabled"; | |
188 | }; | |
189 | ||
190 | timer@4 { | |
191 | compatible = "st,stm32-timer-trigger"; | |
192 | reg = <4>; | |
193 | status = "disabled"; | |
194 | }; | |
195 | }; | |
196 | ||
338a6aaa MC |
197 | timer6: timer@40001000 { |
198 | compatible = "st,stm32-timer"; | |
199 | reg = <0x40001000 0x400>; | |
200 | interrupts = <54>; | |
f20a406b | 201 | clocks = <&rcc 0 STM32F4_APB1_CLOCK(TIM6)>; |
338a6aaa MC |
202 | status = "disabled"; |
203 | }; | |
204 | ||
c0e14fc7 BG |
205 | timers6: timers@40001000 { |
206 | #address-cells = <1>; | |
207 | #size-cells = <0>; | |
208 | compatible = "st,stm32-timers"; | |
209 | reg = <0x40001000 0x400>; | |
f20a406b | 210 | clocks = <&rcc 0 STM32F4_APB1_CLOCK(TIM6)>; |
c0e14fc7 BG |
211 | clock-names = "int"; |
212 | status = "disabled"; | |
213 | ||
214 | timer@5 { | |
215 | compatible = "st,stm32-timer-trigger"; | |
216 | reg = <5>; | |
217 | status = "disabled"; | |
218 | }; | |
219 | }; | |
220 | ||
338a6aaa MC |
221 | timer7: timer@40001400 { |
222 | compatible = "st,stm32-timer"; | |
223 | reg = <0x40001400 0x400>; | |
224 | interrupts = <55>; | |
f20a406b | 225 | clocks = <&rcc 0 STM32F4_APB1_CLOCK(TIM7)>; |
338a6aaa MC |
226 | status = "disabled"; |
227 | }; | |
228 | ||
c0e14fc7 BG |
229 | timers7: timers@40001400 { |
230 | #address-cells = <1>; | |
231 | #size-cells = <0>; | |
232 | compatible = "st,stm32-timers"; | |
233 | reg = <0x40001400 0x400>; | |
f20a406b | 234 | clocks = <&rcc 0 STM32F4_APB1_CLOCK(TIM7)>; |
c0e14fc7 BG |
235 | clock-names = "int"; |
236 | status = "disabled"; | |
237 | ||
238 | timer@6 { | |
239 | compatible = "st,stm32-timer-trigger"; | |
240 | reg = <6>; | |
241 | status = "disabled"; | |
242 | }; | |
243 | }; | |
244 | ||
245 | timers12: timers@40001800 { | |
246 | #address-cells = <1>; | |
247 | #size-cells = <0>; | |
248 | compatible = "st,stm32-timers"; | |
249 | reg = <0x40001800 0x400>; | |
f20a406b | 250 | clocks = <&rcc 0 STM32F4_APB1_CLOCK(TIM12)>; |
c0e14fc7 BG |
251 | clock-names = "int"; |
252 | status = "disabled"; | |
253 | ||
254 | pwm { | |
255 | compatible = "st,stm32-pwm"; | |
256 | status = "disabled"; | |
257 | }; | |
258 | ||
259 | timer@11 { | |
260 | compatible = "st,stm32-timer-trigger"; | |
261 | reg = <11>; | |
262 | status = "disabled"; | |
263 | }; | |
264 | }; | |
265 | ||
266 | timers13: timers@40001c00 { | |
267 | #address-cells = <1>; | |
268 | #size-cells = <0>; | |
269 | compatible = "st,stm32-timers"; | |
270 | reg = <0x40001C00 0x400>; | |
f20a406b | 271 | clocks = <&rcc 0 STM32F4_APB1_CLOCK(TIM13)>; |
c0e14fc7 BG |
272 | clock-names = "int"; |
273 | status = "disabled"; | |
274 | ||
275 | pwm { | |
276 | compatible = "st,stm32-pwm"; | |
277 | status = "disabled"; | |
278 | }; | |
279 | }; | |
280 | ||
281 | timers14: timers@40002000 { | |
282 | #address-cells = <1>; | |
283 | #size-cells = <0>; | |
284 | compatible = "st,stm32-timers"; | |
285 | reg = <0x40002000 0x400>; | |
f20a406b | 286 | clocks = <&rcc 0 STM32F4_APB1_CLOCK(TIM14)>; |
c0e14fc7 BG |
287 | clock-names = "int"; |
288 | status = "disabled"; | |
289 | ||
290 | pwm { | |
291 | compatible = "st,stm32-pwm"; | |
292 | status = "disabled"; | |
293 | }; | |
294 | }; | |
295 | ||
5e6ec1b5 AD |
296 | rtc: rtc@40002800 { |
297 | compatible = "st,stm32-rtc"; | |
298 | reg = <0x40002800 0x400>; | |
299 | clocks = <&rcc 1 CLK_RTC>; | |
300 | clock-names = "ck_rtc"; | |
301 | assigned-clocks = <&rcc 1 CLK_RTC>; | |
302 | assigned-clock-parents = <&rcc 1 CLK_LSE>; | |
303 | interrupt-parent = <&exti>; | |
304 | interrupts = <17 1>; | |
305 | interrupt-names = "alarm"; | |
306 | st,syscfg = <&pwrcfg>; | |
307 | status = "disabled"; | |
308 | }; | |
309 | ||
338a6aaa MC |
310 | usart2: serial@40004400 { |
311 | compatible = "st,stm32-usart", "st,stm32-uart"; | |
312 | reg = <0x40004400 0x400>; | |
313 | interrupts = <38>; | |
f20a406b | 314 | clocks = <&rcc 0 STM32F4_APB1_CLOCK(UART2)>; |
338a6aaa MC |
315 | status = "disabled"; |
316 | }; | |
317 | ||
318 | usart3: serial@40004800 { | |
319 | compatible = "st,stm32-usart", "st,stm32-uart"; | |
320 | reg = <0x40004800 0x400>; | |
321 | interrupts = <39>; | |
f20a406b | 322 | clocks = <&rcc 0 STM32F4_APB1_CLOCK(UART3)>; |
338a6aaa | 323 | status = "disabled"; |
f1134389 AT |
324 | dmas = <&dma1 1 4 0x400 0x0>, |
325 | <&dma1 3 4 0x400 0x0>; | |
326 | dma-names = "rx", "tx"; | |
338a6aaa MC |
327 | }; |
328 | ||
329 | usart4: serial@40004c00 { | |
330 | compatible = "st,stm32-uart"; | |
331 | reg = <0x40004c00 0x400>; | |
332 | interrupts = <52>; | |
f20a406b | 333 | clocks = <&rcc 0 STM32F4_APB1_CLOCK(UART4)>; |
338a6aaa MC |
334 | status = "disabled"; |
335 | }; | |
336 | ||
337 | usart5: serial@40005000 { | |
338 | compatible = "st,stm32-uart"; | |
339 | reg = <0x40005000 0x400>; | |
340 | interrupts = <53>; | |
f20a406b | 341 | clocks = <&rcc 0 STM32F4_APB1_CLOCK(UART5)>; |
338a6aaa MC |
342 | status = "disabled"; |
343 | }; | |
344 | ||
51576d36 CM |
345 | i2c1: i2c@40005400 { |
346 | compatible = "st,stm32f4-i2c"; | |
347 | reg = <0x40005400 0x400>; | |
348 | interrupts = <31>, | |
349 | <32>; | |
350 | resets = <&rcc STM32F4_APB1_RESET(I2C1)>; | |
351 | clocks = <&rcc 0 STM32F4_APB1_CLOCK(I2C1)>; | |
352 | #address-cells = <1>; | |
353 | #size-cells = <0>; | |
354 | status = "disabled"; | |
355 | }; | |
356 | ||
338a6aaa MC |
357 | usart7: serial@40007800 { |
358 | compatible = "st,stm32-usart", "st,stm32-uart"; | |
359 | reg = <0x40007800 0x400>; | |
360 | interrupts = <82>; | |
f20a406b | 361 | clocks = <&rcc 0 STM32F4_APB1_CLOCK(UART7)>; |
338a6aaa MC |
362 | status = "disabled"; |
363 | }; | |
364 | ||
365 | usart8: serial@40007c00 { | |
366 | compatible = "st,stm32-usart", "st,stm32-uart"; | |
367 | reg = <0x40007c00 0x400>; | |
368 | interrupts = <83>; | |
f20a406b | 369 | clocks = <&rcc 0 STM32F4_APB1_CLOCK(UART8)>; |
338a6aaa MC |
370 | status = "disabled"; |
371 | }; | |
372 | ||
c0e14fc7 BG |
373 | timers1: timers@40010000 { |
374 | #address-cells = <1>; | |
375 | #size-cells = <0>; | |
376 | compatible = "st,stm32-timers"; | |
377 | reg = <0x40010000 0x400>; | |
f20a406b | 378 | clocks = <&rcc 0 STM32F4_APB2_CLOCK(TIM1)>; |
c0e14fc7 BG |
379 | clock-names = "int"; |
380 | status = "disabled"; | |
381 | ||
382 | pwm { | |
383 | compatible = "st,stm32-pwm"; | |
384 | status = "disabled"; | |
385 | }; | |
386 | ||
387 | timer@0 { | |
388 | compatible = "st,stm32-timer-trigger"; | |
389 | reg = <0>; | |
390 | status = "disabled"; | |
391 | }; | |
392 | }; | |
393 | ||
394 | timers8: timers@40010400 { | |
395 | #address-cells = <1>; | |
396 | #size-cells = <0>; | |
397 | compatible = "st,stm32-timers"; | |
398 | reg = <0x40010400 0x400>; | |
f20a406b | 399 | clocks = <&rcc 0 STM32F4_APB2_CLOCK(TIM8)>; |
c0e14fc7 BG |
400 | clock-names = "int"; |
401 | status = "disabled"; | |
402 | ||
403 | pwm { | |
404 | compatible = "st,stm32-pwm"; | |
405 | status = "disabled"; | |
406 | }; | |
407 | ||
408 | timer@7 { | |
409 | compatible = "st,stm32-timer-trigger"; | |
410 | reg = <7>; | |
411 | status = "disabled"; | |
412 | }; | |
413 | }; | |
414 | ||
338a6aaa MC |
415 | usart1: serial@40011000 { |
416 | compatible = "st,stm32-usart", "st,stm32-uart"; | |
417 | reg = <0x40011000 0x400>; | |
418 | interrupts = <37>; | |
f20a406b | 419 | clocks = <&rcc 0 STM32F4_APB2_CLOCK(USART1)>; |
338a6aaa | 420 | status = "disabled"; |
73767f19 GB |
421 | dmas = <&dma2 2 4 0x400 0x0>, |
422 | <&dma2 7 4 0x400 0x0>; | |
423 | dma-names = "rx", "tx"; | |
338a6aaa MC |
424 | }; |
425 | ||
426 | usart6: serial@40011400 { | |
427 | compatible = "st,stm32-usart", "st,stm32-uart"; | |
428 | reg = <0x40011400 0x400>; | |
429 | interrupts = <71>; | |
f20a406b | 430 | clocks = <&rcc 0 STM32F4_APB2_CLOCK(USART6)>; |
338a6aaa MC |
431 | status = "disabled"; |
432 | }; | |
9dc24a2d | 433 | |
ee58bfa1 FG |
434 | adc: adc@40012000 { |
435 | compatible = "st,stm32f4-adc-core"; | |
436 | reg = <0x40012000 0x400>; | |
437 | interrupts = <18>; | |
f20a406b | 438 | clocks = <&rcc 0 STM32F4_APB2_CLOCK(ADC1)>; |
ee58bfa1 FG |
439 | clock-names = "adc"; |
440 | interrupt-controller; | |
441 | #interrupt-cells = <1>; | |
442 | #address-cells = <1>; | |
443 | #size-cells = <0>; | |
444 | status = "disabled"; | |
445 | ||
446 | adc1: adc@0 { | |
447 | compatible = "st,stm32f4-adc"; | |
448 | #io-channel-cells = <1>; | |
449 | reg = <0x0>; | |
f20a406b | 450 | clocks = <&rcc 0 STM32F4_APB2_CLOCK(ADC1)>; |
ee58bfa1 FG |
451 | interrupt-parent = <&adc>; |
452 | interrupts = <0>; | |
453 | status = "disabled"; | |
454 | }; | |
455 | ||
456 | adc2: adc@100 { | |
457 | compatible = "st,stm32f4-adc"; | |
458 | #io-channel-cells = <1>; | |
459 | reg = <0x100>; | |
f20a406b | 460 | clocks = <&rcc 0 STM32F4_APB2_CLOCK(ADC2)>; |
ee58bfa1 FG |
461 | interrupt-parent = <&adc>; |
462 | interrupts = <1>; | |
463 | status = "disabled"; | |
464 | }; | |
465 | ||
466 | adc3: adc@200 { | |
467 | compatible = "st,stm32f4-adc"; | |
468 | #io-channel-cells = <1>; | |
469 | reg = <0x200>; | |
f20a406b | 470 | clocks = <&rcc 0 STM32F4_APB2_CLOCK(ADC3)>; |
ee58bfa1 FG |
471 | interrupt-parent = <&adc>; |
472 | interrupts = <2>; | |
473 | status = "disabled"; | |
474 | }; | |
475 | }; | |
476 | ||
e78b6555 AT |
477 | syscfg: system-config@40013800 { |
478 | compatible = "syscon"; | |
479 | reg = <0x40013800 0x400>; | |
480 | }; | |
481 | ||
5a79d596 AT |
482 | exti: interrupt-controller@40013c00 { |
483 | compatible = "st,stm32-exti"; | |
484 | interrupt-controller; | |
485 | #interrupt-cells = <2>; | |
486 | reg = <0x40013C00 0x400>; | |
487 | interrupts = <1>, <2>, <3>, <6>, <7>, <8>, <9>, <10>, <23>, <40>, <41>, <42>, <62>, <76>; | |
488 | }; | |
489 | ||
c0e14fc7 BG |
490 | timers9: timers@40014000 { |
491 | #address-cells = <1>; | |
492 | #size-cells = <0>; | |
493 | compatible = "st,stm32-timers"; | |
494 | reg = <0x40014000 0x400>; | |
f20a406b | 495 | clocks = <&rcc 0 STM32F4_APB2_CLOCK(TIM9)>; |
c0e14fc7 BG |
496 | clock-names = "int"; |
497 | status = "disabled"; | |
498 | ||
499 | pwm { | |
500 | compatible = "st,stm32-pwm"; | |
501 | status = "disabled"; | |
502 | }; | |
503 | ||
504 | timer@8 { | |
505 | compatible = "st,stm32-timer-trigger"; | |
506 | reg = <8>; | |
507 | status = "disabled"; | |
508 | }; | |
509 | }; | |
510 | ||
511 | timers10: timers@40014400 { | |
512 | #address-cells = <1>; | |
513 | #size-cells = <0>; | |
514 | compatible = "st,stm32-timers"; | |
515 | reg = <0x40014400 0x400>; | |
f20a406b | 516 | clocks = <&rcc 0 STM32F4_APB2_CLOCK(TIM10)>; |
c0e14fc7 BG |
517 | clock-names = "int"; |
518 | status = "disabled"; | |
519 | ||
520 | pwm { | |
521 | compatible = "st,stm32-pwm"; | |
522 | status = "disabled"; | |
523 | }; | |
524 | }; | |
525 | ||
526 | timers11: timers@40014800 { | |
527 | #address-cells = <1>; | |
528 | #size-cells = <0>; | |
529 | compatible = "st,stm32-timers"; | |
530 | reg = <0x40014800 0x400>; | |
f20a406b | 531 | clocks = <&rcc 0 STM32F4_APB2_CLOCK(TIM11)>; |
c0e14fc7 BG |
532 | clock-names = "int"; |
533 | status = "disabled"; | |
534 | ||
535 | pwm { | |
536 | compatible = "st,stm32-pwm"; | |
537 | status = "disabled"; | |
538 | }; | |
539 | }; | |
540 | ||
f6dbbff4 GF |
541 | pwrcfg: power-config@40007000 { |
542 | compatible = "syscon"; | |
543 | reg = <0x40007000 0x400>; | |
544 | }; | |
545 | ||
2dbd0593 MC |
546 | pin-controller { |
547 | #address-cells = <1>; | |
548 | #size-cells = <1>; | |
549 | compatible = "st,stm32f429-pinctrl"; | |
550 | ranges = <0 0x40020000 0x3000>; | |
ed01154f MC |
551 | interrupt-parent = <&exti>; |
552 | st,syscfg = <&syscfg 0x8>; | |
2dbd0593 MC |
553 | pins-are-numbered; |
554 | ||
555 | gpioa: gpio@40020000 { | |
556 | gpio-controller; | |
557 | #gpio-cells = <2>; | |
558 | reg = <0x0 0x400>; | |
f20a406b | 559 | clocks = <&rcc 0 STM32F4_AHB1_CLOCK(GPIOA)>; |
2dbd0593 MC |
560 | st,bank-name = "GPIOA"; |
561 | }; | |
562 | ||
563 | gpiob: gpio@40020400 { | |
564 | gpio-controller; | |
565 | #gpio-cells = <2>; | |
566 | reg = <0x400 0x400>; | |
f20a406b | 567 | clocks = <&rcc 0 STM32F4_AHB1_CLOCK(GPIOB)>; |
2dbd0593 MC |
568 | st,bank-name = "GPIOB"; |
569 | }; | |
570 | ||
571 | gpioc: gpio@40020800 { | |
572 | gpio-controller; | |
573 | #gpio-cells = <2>; | |
574 | reg = <0x800 0x400>; | |
f20a406b | 575 | clocks = <&rcc 0 STM32F4_AHB1_CLOCK(GPIOC)>; |
2dbd0593 MC |
576 | st,bank-name = "GPIOC"; |
577 | }; | |
578 | ||
579 | gpiod: gpio@40020c00 { | |
580 | gpio-controller; | |
581 | #gpio-cells = <2>; | |
582 | reg = <0xc00 0x400>; | |
f20a406b | 583 | clocks = <&rcc 0 STM32F4_AHB1_CLOCK(GPIOD)>; |
2dbd0593 MC |
584 | st,bank-name = "GPIOD"; |
585 | }; | |
586 | ||
587 | gpioe: gpio@40021000 { | |
588 | gpio-controller; | |
589 | #gpio-cells = <2>; | |
590 | reg = <0x1000 0x400>; | |
f20a406b | 591 | clocks = <&rcc 0 STM32F4_AHB1_CLOCK(GPIOE)>; |
2dbd0593 MC |
592 | st,bank-name = "GPIOE"; |
593 | }; | |
594 | ||
595 | gpiof: gpio@40021400 { | |
596 | gpio-controller; | |
597 | #gpio-cells = <2>; | |
598 | reg = <0x1400 0x400>; | |
f20a406b | 599 | clocks = <&rcc 0 STM32F4_AHB1_CLOCK(GPIOF)>; |
2dbd0593 MC |
600 | st,bank-name = "GPIOF"; |
601 | }; | |
602 | ||
603 | gpiog: gpio@40021800 { | |
604 | gpio-controller; | |
605 | #gpio-cells = <2>; | |
606 | reg = <0x1800 0x400>; | |
f20a406b | 607 | clocks = <&rcc 0 STM32F4_AHB1_CLOCK(GPIOG)>; |
2dbd0593 MC |
608 | st,bank-name = "GPIOG"; |
609 | }; | |
610 | ||
611 | gpioh: gpio@40021c00 { | |
612 | gpio-controller; | |
613 | #gpio-cells = <2>; | |
614 | reg = <0x1c00 0x400>; | |
f20a406b | 615 | clocks = <&rcc 0 STM32F4_AHB1_CLOCK(GPIOH)>; |
2dbd0593 MC |
616 | st,bank-name = "GPIOH"; |
617 | }; | |
618 | ||
619 | gpioi: gpio@40022000 { | |
620 | gpio-controller; | |
621 | #gpio-cells = <2>; | |
622 | reg = <0x2000 0x400>; | |
f20a406b | 623 | clocks = <&rcc 0 STM32F4_AHB1_CLOCK(GPIOI)>; |
2dbd0593 MC |
624 | st,bank-name = "GPIOI"; |
625 | }; | |
626 | ||
627 | gpioj: gpio@40022400 { | |
628 | gpio-controller; | |
629 | #gpio-cells = <2>; | |
630 | reg = <0x2400 0x400>; | |
f20a406b | 631 | clocks = <&rcc 0 STM32F4_AHB1_CLOCK(GPIOJ)>; |
2dbd0593 MC |
632 | st,bank-name = "GPIOJ"; |
633 | }; | |
634 | ||
635 | gpiok: gpio@40022800 { | |
636 | gpio-controller; | |
637 | #gpio-cells = <2>; | |
638 | reg = <0x2800 0x400>; | |
f20a406b | 639 | clocks = <&rcc 0 STM32F4_AHB1_CLOCK(GPIOK)>; |
2dbd0593 MC |
640 | st,bank-name = "GPIOK"; |
641 | }; | |
521df6f5 MC |
642 | |
643 | usart1_pins_a: usart1@0 { | |
644 | pins1 { | |
645 | pinmux = <STM32F429_PA9_FUNC_USART1_TX>; | |
646 | bias-disable; | |
647 | drive-push-pull; | |
648 | slew-rate = <0>; | |
649 | }; | |
650 | pins2 { | |
651 | pinmux = <STM32F429_PA10_FUNC_USART1_RX>; | |
652 | bias-disable; | |
653 | }; | |
654 | }; | |
c8cc1b72 | 655 | |
872c87f0 BMH |
656 | usart3_pins_a: usart3@0 { |
657 | pins1 { | |
658 | pinmux = <STM32F429_PB10_FUNC_USART3_TX>; | |
659 | bias-disable; | |
660 | drive-push-pull; | |
661 | slew-rate = <0>; | |
662 | }; | |
663 | pins2 { | |
664 | pinmux = <STM32F429_PB11_FUNC_USART3_RX>; | |
665 | bias-disable; | |
666 | }; | |
667 | }; | |
668 | ||
c8cc1b72 MC |
669 | usbotg_hs_pins_a: usbotg_hs@0 { |
670 | pins { | |
671 | pinmux = <STM32F429_PH4_FUNC_OTG_HS_ULPI_NXT>, | |
672 | <STM32F429_PI11_FUNC_OTG_HS_ULPI_DIR>, | |
673 | <STM32F429_PC0_FUNC_OTG_HS_ULPI_STP>, | |
674 | <STM32F429_PA5_FUNC_OTG_HS_ULPI_CK>, | |
675 | <STM32F429_PA3_FUNC_OTG_HS_ULPI_D0>, | |
676 | <STM32F429_PB0_FUNC_OTG_HS_ULPI_D1>, | |
677 | <STM32F429_PB1_FUNC_OTG_HS_ULPI_D2>, | |
678 | <STM32F429_PB10_FUNC_OTG_HS_ULPI_D3>, | |
679 | <STM32F429_PB11_FUNC_OTG_HS_ULPI_D4>, | |
680 | <STM32F429_PB12_FUNC_OTG_HS_ULPI_D5>, | |
681 | <STM32F429_PB13_FUNC_OTG_HS_ULPI_D6>, | |
682 | <STM32F429_PB5_FUNC_OTG_HS_ULPI_D7>; | |
683 | bias-disable; | |
684 | drive-push-pull; | |
685 | slew-rate = <2>; | |
686 | }; | |
687 | }; | |
9ee33d66 | 688 | |
d9b296b9 | 689 | ethernet_mii: mii@0 { |
9ee33d66 AT |
690 | pins { |
691 | pinmux = <STM32F429_PG13_FUNC_ETH_MII_TXD0_ETH_RMII_TXD0>, | |
692 | <STM32F429_PG14_FUNC_ETH_MII_TXD1_ETH_RMII_TXD1>, | |
693 | <STM32F429_PC2_FUNC_ETH_MII_TXD2>, | |
694 | <STM32F429_PB8_FUNC_ETH_MII_TXD3>, | |
695 | <STM32F429_PC3_FUNC_ETH_MII_TX_CLK>, | |
696 | <STM32F429_PG11_FUNC_ETH_MII_TX_EN_ETH_RMII_TX_EN>, | |
697 | <STM32F429_PA2_FUNC_ETH_MDIO>, | |
698 | <STM32F429_PC1_FUNC_ETH_MDC>, | |
699 | <STM32F429_PA1_FUNC_ETH_MII_RX_CLK_ETH_RMII_REF_CLK>, | |
700 | <STM32F429_PA7_FUNC_ETH_MII_RX_DV_ETH_RMII_CRS_DV>, | |
701 | <STM32F429_PC4_FUNC_ETH_MII_RXD0_ETH_RMII_RXD0>, | |
702 | <STM32F429_PC5_FUNC_ETH_MII_RXD1_ETH_RMII_RXD1>, | |
703 | <STM32F429_PH6_FUNC_ETH_MII_RXD2>, | |
704 | <STM32F429_PH7_FUNC_ETH_MII_RXD3>; | |
705 | slew-rate = <2>; | |
706 | }; | |
707 | }; | |
ee58bfa1 FG |
708 | |
709 | adc3_in8_pin: adc@200 { | |
710 | pins { | |
711 | pinmux = <STM32F429_PF10_FUNC_ANALOG>; | |
712 | }; | |
713 | }; | |
c0e14fc7 BG |
714 | |
715 | pwm1_pins: pwm@1 { | |
716 | pins { | |
717 | pinmux = <STM32F429_PA8_FUNC_TIM1_CH1>, | |
718 | <STM32F429_PB13_FUNC_TIM1_CH1N>, | |
719 | <STM32F429_PB12_FUNC_TIM1_BKIN>; | |
720 | }; | |
721 | }; | |
722 | ||
723 | pwm3_pins: pwm@3 { | |
724 | pins { | |
725 | pinmux = <STM32F429_PB4_FUNC_TIM3_CH1>, | |
726 | <STM32F429_PB5_FUNC_TIM3_CH2>; | |
727 | }; | |
728 | }; | |
51576d36 CM |
729 | |
730 | i2c1_pins: i2c1@0 { | |
731 | pins { | |
732 | pinmux = <STM32F429_PB9_FUNC_I2C1_SDA>, | |
733 | <STM32F429_PB6_FUNC_I2C1_SCL>; | |
734 | bias-disable; | |
735 | drive-open-drain; | |
736 | slew-rate = <3>; | |
737 | }; | |
738 | }; | |
2dbd0593 MC |
739 | }; |
740 | ||
9dc24a2d | 741 | rcc: rcc@40023810 { |
9af80712 | 742 | #reset-cells = <1>; |
9dc24a2d DT |
743 | #clock-cells = <2>; |
744 | compatible = "st,stm32f42xx-rcc", "st,stm32-rcc"; | |
745 | reg = <0x40023800 0x400>; | |
305b0495 | 746 | clocks = <&clk_hse>, <&clk_i2s_ckin>; |
f6dbbff4 | 747 | st,syscfg = <&pwrcfg>; |
8867295d AD |
748 | assigned-clocks = <&rcc 1 CLK_HSE_RTC>; |
749 | assigned-clock-rates = <1000000>; | |
9dc24a2d | 750 | }; |
b47c9fab | 751 | |
9ee9e281 CM |
752 | dma1: dma-controller@40026000 { |
753 | compatible = "st,stm32-dma"; | |
754 | reg = <0x40026000 0x400>; | |
755 | interrupts = <11>, | |
756 | <12>, | |
757 | <13>, | |
758 | <14>, | |
759 | <15>, | |
760 | <16>, | |
761 | <17>, | |
762 | <47>; | |
f20a406b | 763 | clocks = <&rcc 0 STM32F4_AHB1_CLOCK(DMA1)>; |
9ee9e281 CM |
764 | #dma-cells = <4>; |
765 | }; | |
766 | ||
767 | dma2: dma-controller@40026400 { | |
768 | compatible = "st,stm32-dma"; | |
769 | reg = <0x40026400 0x400>; | |
770 | interrupts = <56>, | |
771 | <57>, | |
772 | <58>, | |
773 | <59>, | |
774 | <60>, | |
775 | <68>, | |
776 | <69>, | |
777 | <70>; | |
f20a406b | 778 | clocks = <&rcc 0 STM32F4_AHB1_CLOCK(DMA2)>; |
9ee9e281 CM |
779 | #dma-cells = <4>; |
780 | st,mem2mem; | |
781 | }; | |
782 | ||
d9b296b9 | 783 | mac: ethernet@40028000 { |
9ee33d66 AT |
784 | compatible = "st,stm32-dwmac", "snps,dwmac-3.50a"; |
785 | reg = <0x40028000 0x8000>; | |
786 | reg-names = "stmmaceth"; | |
ed75bf33 AT |
787 | interrupts = <61>; |
788 | interrupt-names = "macirq"; | |
d9b296b9 | 789 | clock-names = "stmmaceth", "mac-clk-tx", "mac-clk-rx"; |
f20a406b GF |
790 | clocks = <&rcc 0 STM32F4_AHB1_CLOCK(ETHMAC)>, |
791 | <&rcc 0 STM32F4_AHB1_CLOCK(ETHMACTX)>, | |
792 | <&rcc 0 STM32F4_AHB1_CLOCK(ETHMACRX)>; | |
9ee33d66 AT |
793 | st,syscon = <&syscfg 0x4>; |
794 | snps,pbl = <8>; | |
795 | snps,mixed-burst; | |
9ee33d66 AT |
796 | status = "disabled"; |
797 | }; | |
798 | ||
c8cc1b72 MC |
799 | usbotg_hs: usb@40040000 { |
800 | compatible = "snps,dwc2"; | |
c8cc1b72 MC |
801 | reg = <0x40040000 0x40000>; |
802 | interrupts = <77>; | |
f20a406b | 803 | clocks = <&rcc 0 STM32F4_AHB1_CLOCK(OTGHS)>; |
c8cc1b72 MC |
804 | clock-names = "otg"; |
805 | status = "disabled"; | |
806 | }; | |
807 | ||
b47c9fab DT |
808 | rng: rng@50060800 { |
809 | compatible = "st,stm32-rng"; | |
810 | reg = <0x50060800 0x400>; | |
811 | interrupts = <80>; | |
f20a406b GF |
812 | clocks = <&rcc 0 STM32F4_AHB2_CLOCK(RNG)>; |
813 | ||
b47c9fab | 814 | }; |
338a6aaa MC |
815 | }; |
816 | }; | |
817 | ||
818 | &systick { | |
f20a406b | 819 | clocks = <&rcc 1 SYSTICK>; |
338a6aaa MC |
820 | status = "okay"; |
821 | }; |