Commit | Line | Data |
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15969b45 SK |
1 | |
2 | /* | |
3 | * Copyright (C) 2013 STMicroelectronics Limited. | |
4 | * Author: Srinivas Kandagatla <srinivas.kandagatla@st.com> | |
5 | * | |
6 | * This program is free software; you can redistribute it and/or modify | |
7 | * it under the terms of the GNU General Public License version 2 as | |
8 | * publishhed by the Free Software Foundation. | |
9 | */ | |
10 | #include "st-pincfg.h" | |
bdda8b05 | 11 | #include <dt-bindings/interrupt-controller/arm-gic.h> |
15969b45 SK |
12 | / { |
13 | ||
14 | aliases { | |
15 | gpio0 = &PIO0; | |
16 | gpio1 = &PIO1; | |
17 | gpio2 = &PIO2; | |
18 | gpio3 = &PIO3; | |
19 | gpio4 = &PIO4; | |
20 | gpio5 = &PIO40; | |
21 | gpio6 = &PIO5; | |
22 | gpio7 = &PIO6; | |
23 | gpio8 = &PIO7; | |
24 | gpio9 = &PIO8; | |
25 | gpio10 = &PIO9; | |
26 | gpio11 = &PIO10; | |
27 | gpio12 = &PIO11; | |
28 | gpio13 = &PIO12; | |
29 | gpio14 = &PIO30; | |
30 | gpio15 = &PIO31; | |
31 | gpio16 = &PIO13; | |
32 | gpio17 = &PIO14; | |
33 | gpio18 = &PIO15; | |
34 | gpio19 = &PIO16; | |
35 | gpio20 = &PIO17; | |
36 | gpio21 = &PIO18; | |
37 | gpio22 = &PIO100; | |
38 | gpio23 = &PIO101; | |
39 | gpio24 = &PIO102; | |
40 | gpio25 = &PIO103; | |
41 | gpio26 = &PIO104; | |
42 | gpio27 = &PIO105; | |
43 | gpio28 = &PIO106; | |
44 | gpio29 = &PIO107; | |
45 | }; | |
46 | ||
47 | soc { | |
48 | pin-controller-sbc { | |
49 | #address-cells = <1>; | |
50 | #size-cells = <1>; | |
51 | compatible = "st,stih416-sbc-pinctrl"; | |
52 | st,syscfg = <&syscfg_sbc>; | |
bdda8b05 SK |
53 | reg = <0xfe61f080 0x4>; |
54 | reg-names = "irqmux"; | |
55 | interrupts = <GIC_SPI 182 IRQ_TYPE_LEVEL_HIGH>; | |
ae107d06 | 56 | interrupt-names = "irqmux"; |
15969b45 SK |
57 | ranges = <0 0xfe610000 0x6000>; |
58 | ||
59 | PIO0: gpio@fe610000 { | |
60 | gpio-controller; | |
61 | #gpio-cells = <1>; | |
bdda8b05 SK |
62 | interrupt-controller; |
63 | #interrupt-cells = <2>; | |
15969b45 SK |
64 | reg = <0 0x100>; |
65 | st,bank-name = "PIO0"; | |
66 | }; | |
67 | PIO1: gpio@fe611000 { | |
68 | gpio-controller; | |
69 | #gpio-cells = <1>; | |
bdda8b05 SK |
70 | interrupt-controller; |
71 | #interrupt-cells = <2>; | |
15969b45 SK |
72 | reg = <0x1000 0x100>; |
73 | st,bank-name = "PIO1"; | |
74 | }; | |
75 | PIO2: gpio@fe612000 { | |
76 | gpio-controller; | |
77 | #gpio-cells = <1>; | |
bdda8b05 SK |
78 | interrupt-controller; |
79 | #interrupt-cells = <2>; | |
15969b45 SK |
80 | reg = <0x2000 0x100>; |
81 | st,bank-name = "PIO2"; | |
82 | }; | |
83 | PIO3: gpio@fe613000 { | |
84 | gpio-controller; | |
85 | #gpio-cells = <1>; | |
bdda8b05 SK |
86 | interrupt-controller; |
87 | #interrupt-cells = <2>; | |
15969b45 SK |
88 | reg = <0x3000 0x100>; |
89 | st,bank-name = "PIO3"; | |
90 | }; | |
91 | PIO4: gpio@fe614000 { | |
92 | gpio-controller; | |
93 | #gpio-cells = <1>; | |
bdda8b05 SK |
94 | interrupt-controller; |
95 | #interrupt-cells = <2>; | |
15969b45 SK |
96 | reg = <0x4000 0x100>; |
97 | st,bank-name = "PIO4"; | |
98 | }; | |
99 | PIO40: gpio@fe615000 { | |
100 | gpio-controller; | |
101 | #gpio-cells = <1>; | |
bdda8b05 SK |
102 | interrupt-controller; |
103 | #interrupt-cells = <2>; | |
15969b45 SK |
104 | reg = <0x5000 0x100>; |
105 | st,bank-name = "PIO40"; | |
106 | st,retime-pin-mask = <0x7f>; | |
107 | }; | |
108 | ||
e063735f SK |
109 | rc{ |
110 | pinctrl_ir: ir0 { | |
111 | st,pins { | |
112 | ir = <&PIO4 0 ALT2 IN>; | |
113 | }; | |
114 | }; | |
115 | }; | |
15969b45 SK |
116 | sbc_serial1 { |
117 | pinctrl_sbc_serial1: sbc_serial1 { | |
118 | st,pins { | |
119 | tx = <&PIO2 6 ALT3 OUT>; | |
120 | rx = <&PIO2 7 ALT3 IN>; | |
121 | }; | |
122 | }; | |
123 | }; | |
f53e99a9 MC |
124 | |
125 | sbc_i2c0 { | |
126 | pinctrl_sbc_i2c0_default: sbc_i2c0-default { | |
127 | st,pins { | |
128 | sda = <&PIO4 6 ALT1 BIDIR>; | |
129 | scl = <&PIO4 5 ALT1 BIDIR>; | |
130 | }; | |
131 | }; | |
132 | }; | |
133 | ||
134 | sbc_i2c1 { | |
135 | pinctrl_sbc_i2c1_default: sbc_i2c1-default { | |
136 | st,pins { | |
137 | sda = <&PIO3 2 ALT2 BIDIR>; | |
138 | scl = <&PIO3 1 ALT2 BIDIR>; | |
139 | }; | |
140 | }; | |
141 | }; | |
d25ea584 SK |
142 | |
143 | gmac1 { | |
144 | pinctrl_mii1: mii1 { | |
145 | st,pins { | |
146 | txd0 = <&PIO0 0 ALT1 OUT SE_NICLK_IO 0 CLK_A>; | |
147 | txd1 = <&PIO0 1 ALT1 OUT SE_NICLK_IO 0 CLK_A>; | |
148 | txd2 = <&PIO0 2 ALT1 OUT SE_NICLK_IO 0 CLK_A>; | |
149 | txd3 = <&PIO0 3 ALT1 OUT SE_NICLK_IO 0 CLK_A>; | |
150 | txer = <&PIO0 4 ALT1 OUT SE_NICLK_IO 0 CLK_A>; | |
151 | txen = <&PIO0 5 ALT1 OUT SE_NICLK_IO 0 CLK_A>; | |
152 | txclk = <&PIO0 6 ALT1 IN NICLK 0 CLK_A>; | |
153 | col = <&PIO0 7 ALT1 IN BYPASS 1000>; | |
154 | ||
155 | mdio = <&PIO1 0 ALT1 OUT BYPASS 1500>; | |
156 | mdc = <&PIO1 1 ALT1 OUT NICLK 0 CLK_A>; | |
157 | crs = <&PIO1 2 ALT1 IN BYPASS 1000>; | |
158 | mdint = <&PIO1 3 ALT1 IN BYPASS 0>; | |
159 | rxd0 = <&PIO1 4 ALT1 IN SE_NICLK_IO 0 CLK_A>; | |
160 | rxd1 = <&PIO1 5 ALT1 IN SE_NICLK_IO 0 CLK_A>; | |
161 | rxd2 = <&PIO1 6 ALT1 IN SE_NICLK_IO 0 CLK_A>; | |
162 | rxd3 = <&PIO1 7 ALT1 IN SE_NICLK_IO 0 CLK_A>; | |
163 | ||
164 | rxdv = <&PIO2 0 ALT1 IN SE_NICLK_IO 0 CLK_A>; | |
165 | rx_er = <&PIO2 1 ALT1 IN SE_NICLK_IO 0 CLK_A>; | |
166 | rxclk = <&PIO2 2 ALT1 IN NICLK 0 CLK_A>; | |
167 | phyclk = <&PIO2 3 ALT1 OUT NICLK 0 CLK_A>; | |
168 | }; | |
169 | }; | |
170 | pinctrl_rgmii1: rgmii1-0 { | |
171 | st,pins { | |
172 | txd0 = <&PIO0 0 ALT1 OUT DE_IO 500 CLK_A>; | |
173 | txd1 = <&PIO0 1 ALT1 OUT DE_IO 500 CLK_A>; | |
174 | txd2 = <&PIO0 2 ALT1 OUT DE_IO 500 CLK_A>; | |
175 | txd3 = <&PIO0 3 ALT1 OUT DE_IO 500 CLK_A>; | |
176 | txen = <&PIO0 5 ALT1 OUT DE_IO 0 CLK_A>; | |
177 | txclk = <&PIO0 6 ALT1 IN NICLK 0 CLK_A>; | |
178 | ||
179 | mdio = <&PIO1 0 ALT1 OUT BYPASS 0>; | |
180 | mdc = <&PIO1 1 ALT1 OUT NICLK 0 CLK_A>; | |
181 | rxd0 = <&PIO1 4 ALT1 IN DE_IO 500 CLK_A>; | |
182 | rxd1 = <&PIO1 5 ALT1 IN DE_IO 500 CLK_A>; | |
183 | rxd2 = <&PIO1 6 ALT1 IN DE_IO 500 CLK_A>; | |
184 | rxd3 = <&PIO1 7 ALT1 IN DE_IO 500 CLK_A>; | |
185 | ||
186 | rxdv = <&PIO2 0 ALT1 IN DE_IO 500 CLK_A>; | |
187 | rxclk = <&PIO2 2 ALT1 IN NICLK 0 CLK_A>; | |
188 | phyclk = <&PIO2 3 ALT4 OUT NICLK 0 CLK_B>; | |
189 | ||
190 | clk125= <&PIO3 7 ALT4 IN NICLK 0 CLK_A>; | |
191 | }; | |
192 | }; | |
193 | }; | |
15969b45 SK |
194 | }; |
195 | ||
196 | pin-controller-front { | |
197 | #address-cells = <1>; | |
198 | #size-cells = <1>; | |
199 | compatible = "st,stih416-front-pinctrl"; | |
200 | st,syscfg = <&syscfg_front>; | |
bdda8b05 SK |
201 | reg = <0xfee0f080 0x4>; |
202 | reg-names = "irqmux"; | |
203 | interrupts = <GIC_SPI 183 IRQ_TYPE_LEVEL_HIGH>; | |
ae107d06 | 204 | interrupt-names = "irqmux"; |
15969b45 SK |
205 | ranges = <0 0xfee00000 0x10000>; |
206 | ||
207 | PIO5: gpio@fee00000 { | |
208 | gpio-controller; | |
209 | #gpio-cells = <1>; | |
bdda8b05 SK |
210 | interrupt-controller; |
211 | #interrupt-cells = <2>; | |
15969b45 SK |
212 | reg = <0 0x100>; |
213 | st,bank-name = "PIO5"; | |
214 | }; | |
215 | PIO6: gpio@fee01000 { | |
216 | gpio-controller; | |
217 | #gpio-cells = <1>; | |
bdda8b05 SK |
218 | interrupt-controller; |
219 | #interrupt-cells = <2>; | |
15969b45 SK |
220 | reg = <0x1000 0x100>; |
221 | st,bank-name = "PIO6"; | |
222 | }; | |
223 | PIO7: gpio@fee02000 { | |
224 | gpio-controller; | |
225 | #gpio-cells = <1>; | |
bdda8b05 SK |
226 | interrupt-controller; |
227 | #interrupt-cells = <2>; | |
15969b45 SK |
228 | reg = <0x2000 0x100>; |
229 | st,bank-name = "PIO7"; | |
230 | }; | |
231 | PIO8: gpio@fee03000 { | |
232 | gpio-controller; | |
233 | #gpio-cells = <1>; | |
bdda8b05 SK |
234 | interrupt-controller; |
235 | #interrupt-cells = <2>; | |
15969b45 SK |
236 | reg = <0x3000 0x100>; |
237 | st,bank-name = "PIO8"; | |
238 | }; | |
239 | PIO9: gpio@fee04000 { | |
240 | gpio-controller; | |
241 | #gpio-cells = <1>; | |
bdda8b05 SK |
242 | interrupt-controller; |
243 | #interrupt-cells = <2>; | |
15969b45 SK |
244 | reg = <0x4000 0x100>; |
245 | st,bank-name = "PIO9"; | |
246 | }; | |
247 | PIO10: gpio@fee05000 { | |
248 | gpio-controller; | |
249 | #gpio-cells = <1>; | |
bdda8b05 SK |
250 | interrupt-controller; |
251 | #interrupt-cells = <2>; | |
15969b45 SK |
252 | reg = <0x5000 0x100>; |
253 | st,bank-name = "PIO10"; | |
254 | }; | |
255 | PIO11: gpio@fee06000 { | |
256 | gpio-controller; | |
257 | #gpio-cells = <1>; | |
bdda8b05 SK |
258 | interrupt-controller; |
259 | #interrupt-cells = <2>; | |
15969b45 SK |
260 | reg = <0x6000 0x100>; |
261 | st,bank-name = "PIO11"; | |
262 | }; | |
263 | PIO12: gpio@fee07000 { | |
264 | gpio-controller; | |
265 | #gpio-cells = <1>; | |
bdda8b05 SK |
266 | interrupt-controller; |
267 | #interrupt-cells = <2>; | |
15969b45 SK |
268 | reg = <0x7000 0x100>; |
269 | st,bank-name = "PIO12"; | |
270 | }; | |
271 | PIO30: gpio@fee08000 { | |
272 | gpio-controller; | |
273 | #gpio-cells = <1>; | |
bdda8b05 SK |
274 | interrupt-controller; |
275 | #interrupt-cells = <2>; | |
15969b45 SK |
276 | reg = <0x8000 0x100>; |
277 | st,bank-name = "PIO30"; | |
278 | }; | |
279 | PIO31: gpio@fee09000 { | |
280 | gpio-controller; | |
281 | #gpio-cells = <1>; | |
bdda8b05 SK |
282 | interrupt-controller; |
283 | #interrupt-cells = <2>; | |
15969b45 SK |
284 | reg = <0x9000 0x100>; |
285 | st,bank-name = "PIO31"; | |
286 | }; | |
334ab91d SK |
287 | |
288 | serial2-oe { | |
289 | pinctrl_serial2_oe: serial2-1 { | |
290 | st,pins { | |
291 | output-enable = <&PIO11 3 ALT2 OUT>; | |
292 | }; | |
293 | }; | |
294 | }; | |
295 | ||
f53e99a9 MC |
296 | i2c0 { |
297 | pinctrl_i2c0_default: i2c0-default { | |
298 | st,pins { | |
299 | sda = <&PIO9 3 ALT1 BIDIR>; | |
300 | scl = <&PIO9 2 ALT1 BIDIR>; | |
301 | }; | |
302 | }; | |
303 | }; | |
304 | ||
305 | i2c1 { | |
306 | pinctrl_i2c1_default: i2c1-default { | |
307 | st,pins { | |
308 | sda = <&PIO12 1 ALT1 BIDIR>; | |
309 | scl = <&PIO12 0 ALT1 BIDIR>; | |
310 | }; | |
311 | }; | |
312 | }; | |
77f8d9b7 LJ |
313 | |
314 | fsm { | |
315 | pinctrl_fsm: fsm { | |
316 | st,pins { | |
317 | spi-fsm-clk = <&PIO12 2 ALT1 OUT>; | |
318 | spi-fsm-cs = <&PIO12 3 ALT1 OUT>; | |
319 | spi-fsm-mosi = <&PIO12 4 ALT1 OUT>; | |
320 | spi-fsm-miso = <&PIO12 5 ALT1 IN>; | |
321 | spi-fsm-hol = <&PIO12 6 ALT1 OUT>; | |
322 | spi-fsm-wp = <&PIO12 7 ALT1 OUT>; | |
323 | }; | |
324 | }; | |
325 | }; | |
15969b45 SK |
326 | }; |
327 | ||
328 | pin-controller-rear { | |
329 | #address-cells = <1>; | |
330 | #size-cells = <1>; | |
331 | compatible = "st,stih416-rear-pinctrl"; | |
332 | st,syscfg = <&syscfg_rear>; | |
bdda8b05 SK |
333 | reg = <0xfe82f080 0x4>; |
334 | reg-names = "irqmux"; | |
335 | interrupts = <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>; | |
ae107d06 | 336 | interrupt-names = "irqmux"; |
15969b45 SK |
337 | ranges = <0 0xfe820000 0x6000>; |
338 | ||
339 | PIO13: gpio@fe820000 { | |
340 | gpio-controller; | |
341 | #gpio-cells = <1>; | |
bdda8b05 SK |
342 | interrupt-controller; |
343 | #interrupt-cells = <2>; | |
15969b45 SK |
344 | reg = <0 0x100>; |
345 | st,bank-name = "PIO13"; | |
346 | }; | |
347 | PIO14: gpio@fe821000 { | |
348 | gpio-controller; | |
349 | #gpio-cells = <1>; | |
bdda8b05 SK |
350 | interrupt-controller; |
351 | #interrupt-cells = <2>; | |
15969b45 SK |
352 | reg = <0x1000 0x100>; |
353 | st,bank-name = "PIO14"; | |
354 | }; | |
355 | PIO15: gpio@fe822000 { | |
356 | gpio-controller; | |
357 | #gpio-cells = <1>; | |
bdda8b05 SK |
358 | interrupt-controller; |
359 | #interrupt-cells = <2>; | |
15969b45 SK |
360 | reg = <0x2000 0x100>; |
361 | st,bank-name = "PIO15"; | |
362 | }; | |
363 | PIO16: gpio@fe823000 { | |
364 | gpio-controller; | |
365 | #gpio-cells = <1>; | |
bdda8b05 SK |
366 | interrupt-controller; |
367 | #interrupt-cells = <2>; | |
15969b45 SK |
368 | reg = <0x3000 0x100>; |
369 | st,bank-name = "PIO16"; | |
370 | }; | |
371 | PIO17: gpio@fe824000 { | |
372 | gpio-controller; | |
373 | #gpio-cells = <1>; | |
bdda8b05 SK |
374 | interrupt-controller; |
375 | #interrupt-cells = <2>; | |
15969b45 SK |
376 | reg = <0x4000 0x100>; |
377 | st,bank-name = "PIO17"; | |
378 | }; | |
379 | PIO18: gpio@fe825000 { | |
380 | gpio-controller; | |
381 | #gpio-cells = <1>; | |
bdda8b05 SK |
382 | interrupt-controller; |
383 | #interrupt-cells = <2>; | |
15969b45 SK |
384 | reg = <0x5000 0x100>; |
385 | st,bank-name = "PIO18"; | |
386 | st,retime-pin-mask = <0xf>; | |
387 | }; | |
388 | ||
389 | serial2 { | |
390 | pinctrl_serial2: serial2-0 { | |
391 | st,pins { | |
392 | tx = <&PIO17 4 ALT2 OUT>; | |
393 | rx = <&PIO17 5 ALT2 IN>; | |
15969b45 SK |
394 | }; |
395 | }; | |
396 | }; | |
d25ea584 SK |
397 | |
398 | gmac0 { | |
399 | pinctrl_mii0: mii0 { | |
400 | st,pins { | |
401 | mdint = <&PIO13 6 ALT2 IN BYPASS 0>; | |
402 | txen = <&PIO13 7 ALT2 OUT SE_NICLK_IO 0 CLK_A>; | |
403 | txd0 = <&PIO14 0 ALT2 OUT SE_NICLK_IO 0 CLK_A>; | |
404 | txd1 = <&PIO14 1 ALT2 OUT SE_NICLK_IO 0 CLK_A>; | |
405 | txd2 = <&PIO14 2 ALT2 OUT SE_NICLK_IO 0 CLK_B>; | |
406 | txd3 = <&PIO14 3 ALT2 OUT SE_NICLK_IO 0 CLK_B>; | |
407 | ||
408 | txclk = <&PIO15 0 ALT2 IN NICLK 0 CLK_A>; | |
409 | txer = <&PIO15 1 ALT2 OUT SE_NICLK_IO 0 CLK_A>; | |
410 | crs = <&PIO15 2 ALT2 IN BYPASS 1000>; | |
411 | col = <&PIO15 3 ALT2 IN BYPASS 1000>; | |
412 | mdio= <&PIO15 4 ALT2 OUT BYPASS 1500>; | |
413 | mdc = <&PIO15 5 ALT2 OUT NICLK 0 CLK_B>; | |
414 | ||
415 | rxd0 = <&PIO16 0 ALT2 IN SE_NICLK_IO 0 CLK_A>; | |
416 | rxd1 = <&PIO16 1 ALT2 IN SE_NICLK_IO 0 CLK_A>; | |
417 | rxd2 = <&PIO16 2 ALT2 IN SE_NICLK_IO 0 CLK_A>; | |
418 | rxd3 = <&PIO16 3 ALT2 IN SE_NICLK_IO 0 CLK_A>; | |
419 | rxdv = <&PIO15 6 ALT2 IN SE_NICLK_IO 0 CLK_A>; | |
420 | rx_er = <&PIO15 7 ALT2 IN SE_NICLK_IO 0 CLK_A>; | |
421 | rxclk = <&PIO17 0 ALT2 IN NICLK 0 CLK_A>; | |
422 | phyclk = <&PIO13 5 ALT2 OUT NICLK 0 CLK_B>; | |
423 | }; | |
424 | }; | |
425 | ||
426 | pinctrl_gmii0: gmii0 { | |
427 | st,pins { | |
428 | }; | |
429 | }; | |
430 | pinctrl_rgmii0: rgmii0 { | |
431 | st,pins { | |
432 | phyclk = <&PIO13 5 ALT4 OUT NICLK 0 CLK_B>; | |
433 | txen = <&PIO13 7 ALT2 OUT DE_IO 0 CLK_A>; | |
434 | txd0 = <&PIO14 0 ALT2 OUT DE_IO 500 CLK_A>; | |
435 | txd1 = <&PIO14 1 ALT2 OUT DE_IO 500 CLK_A>; | |
436 | txd2 = <&PIO14 2 ALT2 OUT DE_IO 500 CLK_B>; | |
437 | txd3 = <&PIO14 3 ALT2 OUT DE_IO 500 CLK_B>; | |
438 | txclk = <&PIO15 0 ALT2 IN NICLK 0 CLK_A>; | |
439 | ||
440 | mdio = <&PIO15 4 ALT2 OUT BYPASS 0>; | |
441 | mdc = <&PIO15 5 ALT2 OUT NICLK 0 CLK_B>; | |
442 | ||
443 | rxdv = <&PIO15 6 ALT2 IN DE_IO 500 CLK_A>; | |
444 | rxd0 =<&PIO16 0 ALT2 IN DE_IO 500 CLK_A>; | |
445 | rxd1 =<&PIO16 1 ALT2 IN DE_IO 500 CLK_A>; | |
446 | rxd2 =<&PIO16 2 ALT2 IN DE_IO 500 CLK_A>; | |
447 | rxd3 =<&PIO16 3 ALT2 IN DE_IO 500 CLK_A>; | |
448 | rxclk =<&PIO17 0 ALT2 IN NICLK 0 CLK_A>; | |
449 | ||
450 | clk125=<&PIO17 6 ALT1 IN NICLK 0 CLK_A>; | |
451 | }; | |
452 | }; | |
453 | }; | |
15969b45 SK |
454 | }; |
455 | ||
456 | pin-controller-fvdp-fe { | |
457 | #address-cells = <1>; | |
458 | #size-cells = <1>; | |
459 | compatible = "st,stih416-fvdp-fe-pinctrl"; | |
460 | st,syscfg = <&syscfg_fvdp_fe>; | |
bdda8b05 SK |
461 | reg = <0xfd6bf080 0x4>; |
462 | reg-names = "irqmux"; | |
463 | interrupts = <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>; | |
ae107d06 | 464 | interrupt-names = "irqmux"; |
15969b45 SK |
465 | ranges = <0 0xfd6b0000 0x3000>; |
466 | ||
467 | PIO100: gpio@fd6b0000 { | |
468 | gpio-controller; | |
469 | #gpio-cells = <1>; | |
bdda8b05 SK |
470 | interrupt-controller; |
471 | #interrupt-cells = <2>; | |
15969b45 SK |
472 | reg = <0 0x100>; |
473 | st,bank-name = "PIO100"; | |
474 | }; | |
475 | PIO101: gpio@fd6b1000 { | |
476 | gpio-controller; | |
477 | #gpio-cells = <1>; | |
bdda8b05 SK |
478 | interrupt-controller; |
479 | #interrupt-cells = <2>; | |
15969b45 SK |
480 | reg = <0x1000 0x100>; |
481 | st,bank-name = "PIO101"; | |
482 | }; | |
483 | PIO102: gpio@fd6b2000 { | |
484 | gpio-controller; | |
485 | #gpio-cells = <1>; | |
bdda8b05 SK |
486 | interrupt-controller; |
487 | #interrupt-cells = <2>; | |
15969b45 SK |
488 | reg = <0x2000 0x100>; |
489 | st,bank-name = "PIO102"; | |
490 | }; | |
491 | }; | |
492 | ||
493 | pin-controller-fvdp-lite { | |
494 | #address-cells = <1>; | |
495 | #size-cells = <1>; | |
496 | compatible = "st,stih416-fvdp-lite-pinctrl"; | |
497 | st,syscfg = <&syscfg_fvdp_lite>; | |
bdda8b05 SK |
498 | reg = <0xfd33f080 0x4>; |
499 | reg-names = "irqmux"; | |
500 | interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>; | |
ae107d06 | 501 | interrupt-names = "irqmux"; |
15969b45 SK |
502 | ranges = <0 0xfd330000 0x5000>; |
503 | ||
504 | PIO103: gpio@fd330000 { | |
505 | gpio-controller; | |
506 | #gpio-cells = <1>; | |
bdda8b05 SK |
507 | interrupt-controller; |
508 | #interrupt-cells = <2>; | |
15969b45 SK |
509 | reg = <0 0x100>; |
510 | st,bank-name = "PIO103"; | |
511 | }; | |
512 | PIO104: gpio@fd331000 { | |
513 | gpio-controller; | |
514 | #gpio-cells = <1>; | |
bdda8b05 SK |
515 | interrupt-controller; |
516 | #interrupt-cells = <2>; | |
15969b45 SK |
517 | reg = <0x1000 0x100>; |
518 | st,bank-name = "PIO104"; | |
519 | }; | |
520 | PIO105: gpio@fd332000 { | |
521 | gpio-controller; | |
522 | #gpio-cells = <1>; | |
bdda8b05 SK |
523 | interrupt-controller; |
524 | #interrupt-cells = <2>; | |
15969b45 SK |
525 | reg = <0x2000 0x100>; |
526 | st,bank-name = "PIO105"; | |
527 | }; | |
528 | PIO106: gpio@fd333000 { | |
529 | gpio-controller; | |
530 | #gpio-cells = <1>; | |
bdda8b05 SK |
531 | interrupt-controller; |
532 | #interrupt-cells = <2>; | |
15969b45 SK |
533 | reg = <0x3000 0x100>; |
534 | st,bank-name = "PIO106"; | |
535 | }; | |
536 | ||
537 | PIO107: gpio@fd334000 { | |
538 | gpio-controller; | |
539 | #gpio-cells = <1>; | |
bdda8b05 SK |
540 | interrupt-controller; |
541 | #interrupt-cells = <2>; | |
15969b45 SK |
542 | reg = <0x4000 0x100>; |
543 | st,bank-name = "PIO107"; | |
544 | st,retime-pin-mask = <0xf>; | |
545 | }; | |
546 | }; | |
547 | }; | |
548 | }; |