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65ebcc11 SK |
1 | /* |
2 | * Copyright (C) 2013 STMicroelectronics (R&D) Limited. | |
3 | * Author: Srinivas Kandagatla <srinivas.kandagatla@st.com> | |
4 | * | |
5 | * This program is free software; you can redistribute it and/or modify | |
6 | * it under the terms of the GNU General Public License version 2 as | |
7 | * publishhed by the Free Software Foundation. | |
8 | */ | |
9 | #include "st-pincfg.h" | |
7ec5183a | 10 | #include <dt-bindings/interrupt-controller/arm-gic.h> |
65ebcc11 SK |
11 | / { |
12 | ||
13 | aliases { | |
14 | gpio0 = &PIO0; | |
15 | gpio1 = &PIO1; | |
16 | gpio2 = &PIO2; | |
17 | gpio3 = &PIO3; | |
18 | gpio4 = &PIO4; | |
19 | gpio5 = &PIO5; | |
20 | gpio6 = &PIO6; | |
21 | gpio7 = &PIO7; | |
22 | gpio8 = &PIO8; | |
23 | gpio9 = &PIO9; | |
24 | gpio10 = &PIO10; | |
25 | gpio11 = &PIO11; | |
26 | gpio12 = &PIO12; | |
27 | gpio13 = &PIO13; | |
28 | gpio14 = &PIO14; | |
29 | gpio15 = &PIO15; | |
30 | gpio16 = &PIO16; | |
31 | gpio17 = &PIO17; | |
32 | gpio18 = &PIO18; | |
33 | gpio19 = &PIO100; | |
34 | gpio20 = &PIO101; | |
35 | gpio21 = &PIO102; | |
36 | gpio22 = &PIO103; | |
37 | gpio23 = &PIO104; | |
38 | gpio24 = &PIO105; | |
39 | gpio25 = &PIO106; | |
40 | gpio26 = &PIO107; | |
41 | }; | |
42 | ||
43 | soc { | |
44 | pin-controller-sbc { | |
45 | #address-cells = <1>; | |
46 | #size-cells = <1>; | |
47 | compatible = "st,stih415-sbc-pinctrl"; | |
48 | st,syscfg = <&syscfg_sbc>; | |
7ec5183a SK |
49 | reg = <0xfe61f080 0x4>; |
50 | reg-names = "irqmux"; | |
51 | interrupts = <GIC_SPI 180 IRQ_TYPE_LEVEL_HIGH>; | |
ae107d06 | 52 | interrupt-names = "irqmux"; |
65ebcc11 SK |
53 | ranges = <0 0xfe610000 0x5000>; |
54 | ||
55 | PIO0: gpio@fe610000 { | |
56 | gpio-controller; | |
57 | #gpio-cells = <1>; | |
7ec5183a SK |
58 | interrupt-controller; |
59 | #interrupt-cells = <2>; | |
65ebcc11 SK |
60 | reg = <0 0x100>; |
61 | st,bank-name = "PIO0"; | |
62 | }; | |
63 | PIO1: gpio@fe611000 { | |
64 | gpio-controller; | |
65 | #gpio-cells = <1>; | |
7ec5183a SK |
66 | interrupt-controller; |
67 | #interrupt-cells = <2>; | |
65ebcc11 SK |
68 | reg = <0x1000 0x100>; |
69 | st,bank-name = "PIO1"; | |
70 | }; | |
71 | PIO2: gpio@fe612000 { | |
72 | gpio-controller; | |
73 | #gpio-cells = <1>; | |
7ec5183a SK |
74 | interrupt-controller; |
75 | #interrupt-cells = <2>; | |
65ebcc11 SK |
76 | reg = <0x2000 0x100>; |
77 | st,bank-name = "PIO2"; | |
78 | }; | |
79 | PIO3: gpio@fe613000 { | |
80 | gpio-controller; | |
81 | #gpio-cells = <1>; | |
7ec5183a SK |
82 | interrupt-controller; |
83 | #interrupt-cells = <2>; | |
65ebcc11 SK |
84 | reg = <0x3000 0x100>; |
85 | st,bank-name = "PIO3"; | |
86 | }; | |
87 | PIO4: gpio@fe614000 { | |
88 | gpio-controller; | |
89 | #gpio-cells = <1>; | |
7ec5183a SK |
90 | interrupt-controller; |
91 | #interrupt-cells = <2>; | |
65ebcc11 SK |
92 | reg = <0x4000 0x100>; |
93 | st,bank-name = "PIO4"; | |
94 | }; | |
95 | ||
96 | sbc_serial1 { | |
97 | pinctrl_sbc_serial1:sbc_serial1 { | |
98 | st,pins { | |
99 | tx = <&PIO2 6 ALT3 OUT>; | |
100 | rx = <&PIO2 7 ALT3 IN>; | |
101 | }; | |
102 | }; | |
103 | }; | |
5bbb7527 MC |
104 | |
105 | sbc_i2c0 { | |
106 | pinctrl_sbc_i2c0_default: sbc_i2c0-default { | |
107 | st,pins { | |
108 | sda = <&PIO4 6 ALT1 BIDIR>; | |
109 | scl = <&PIO4 5 ALT1 BIDIR>; | |
110 | }; | |
111 | }; | |
112 | }; | |
113 | ||
114 | sbc_i2c1 { | |
115 | pinctrl_sbc_i2c1_default: sbc_i2c1-default { | |
116 | st,pins { | |
117 | sda = <&PIO3 2 ALT2 BIDIR>; | |
118 | scl = <&PIO3 1 ALT2 BIDIR>; | |
119 | }; | |
120 | }; | |
121 | }; | |
c80fe335 | 122 | |
8ccd3f3a SK |
123 | rc{ |
124 | pinctrl_ir: ir0 { | |
125 | st,pins { | |
126 | ir = <&PIO4 0 ALT2 IN>; | |
127 | }; | |
128 | }; | |
129 | }; | |
130 | ||
c80fe335 SK |
131 | gmac1 { |
132 | pinctrl_mii1: mii1 { | |
133 | st,pins { | |
134 | txd0 = <&PIO0 0 ALT1 OUT SE_NICLK_IO 0 CLK_A>; | |
135 | txd1 = <&PIO0 1 ALT1 OUT SE_NICLK_IO 0 CLK_A>; | |
136 | txd2 = <&PIO0 2 ALT1 OUT SE_NICLK_IO 0 CLK_A>; | |
137 | txd3 = <&PIO0 3 ALT1 OUT SE_NICLK_IO 0 CLK_A>; | |
138 | txer = <&PIO0 4 ALT1 OUT SE_NICLK_IO 0 CLK_A>; | |
139 | txen = <&PIO0 5 ALT1 OUT SE_NICLK_IO 0 CLK_A>; | |
140 | txclk = <&PIO0 6 ALT1 IN NICLK 0 CLK_A>; | |
141 | col = <&PIO0 7 ALT1 IN BYPASS 1000>; | |
142 | mdio = <&PIO1 0 ALT1 OUT BYPASS 0>; | |
143 | mdc = <&PIO1 1 ALT1 OUT NICLK 0 CLK_A>; | |
144 | crs = <&PIO1 2 ALT1 IN BYPASS 1000>; | |
145 | mdint = <&PIO1 3 ALT1 IN BYPASS 0>; | |
146 | rxd0 = <&PIO1 4 ALT1 IN SE_NICLK_IO 0 CLK_A>; | |
147 | rxd1 = <&PIO1 5 ALT1 IN SE_NICLK_IO 0 CLK_A>; | |
148 | rxd2 = <&PIO1 6 ALT1 IN SE_NICLK_IO 0 CLK_A>; | |
149 | rxd3 = <&PIO1 7 ALT1 IN SE_NICLK_IO 0 CLK_A>; | |
150 | rxdv = <&PIO2 0 ALT1 IN SE_NICLK_IO 0 CLK_A>; | |
151 | rx_er = <&PIO2 1 ALT1 IN SE_NICLK_IO 0 CLK_A>; | |
152 | rxclk = <&PIO2 2 ALT1 IN NICLK 0 CLK_A>; | |
153 | phyclk = <&PIO2 3 ALT1 IN NICLK 1000 CLK_A>; | |
154 | }; | |
155 | }; | |
156 | ||
157 | pinctrl_rgmii1: rgmii1-0 { | |
158 | st,pins { | |
159 | txd0 = <&PIO0 0 ALT1 OUT DE_IO 1000 CLK_A>; | |
160 | txd1 = <&PIO0 1 ALT1 OUT DE_IO 1000 CLK_A>; | |
161 | txd2 = <&PIO0 2 ALT1 OUT DE_IO 1000 CLK_A>; | |
162 | txd3 = <&PIO0 3 ALT1 OUT DE_IO 1000 CLK_A>; | |
163 | txen = <&PIO0 5 ALT1 OUT DE_IO 0 CLK_A>; | |
164 | txclk = <&PIO0 6 ALT1 IN NICLK 0 CLK_A>; | |
165 | mdio = <&PIO1 0 ALT1 OUT BYPASS 0>; | |
166 | mdc = <&PIO1 1 ALT1 OUT NICLK 0 CLK_A>; | |
167 | rxd0 = <&PIO1 4 ALT1 IN DE_IO 0 CLK_A>; | |
168 | rxd1 = <&PIO1 5 ALT1 IN DE_IO 0 CLK_A>; | |
169 | rxd2 = <&PIO1 6 ALT1 IN DE_IO 0 CLK_A>; | |
170 | rxd3 = <&PIO1 7 ALT1 IN DE_IO 0 CLK_A>; | |
171 | ||
172 | rxdv = <&PIO2 0 ALT1 IN DE_IO 500 CLK_A>; | |
173 | rxclk = <&PIO2 2 ALT1 IN NICLK 0 CLK_A>; | |
174 | phyclk = <&PIO2 3 ALT4 OUT NICLK 0 CLK_B>; | |
175 | ||
176 | clk125= <&PIO3 7 ALT4 IN NICLK 0 CLK_A>; | |
177 | }; | |
178 | }; | |
179 | }; | |
65ebcc11 SK |
180 | }; |
181 | ||
182 | pin-controller-front { | |
183 | #address-cells = <1>; | |
184 | #size-cells = <1>; | |
185 | compatible = "st,stih415-front-pinctrl"; | |
186 | st,syscfg = <&syscfg_front>; | |
7ec5183a SK |
187 | reg = <0xfee0f080 0x4>; |
188 | reg-names = "irqmux"; | |
189 | interrupts = <GIC_SPI 181 IRQ_TYPE_LEVEL_HIGH>; | |
ae107d06 | 190 | interrupt-names = "irqmux"; |
65ebcc11 SK |
191 | ranges = <0 0xfee00000 0x8000>; |
192 | ||
193 | PIO5: gpio@fee00000 { | |
194 | gpio-controller; | |
195 | #gpio-cells = <1>; | |
7ec5183a SK |
196 | interrupt-controller; |
197 | #interrupt-cells = <2>; | |
65ebcc11 SK |
198 | reg = <0 0x100>; |
199 | st,bank-name = "PIO5"; | |
200 | }; | |
201 | PIO6: gpio@fee01000 { | |
202 | gpio-controller; | |
203 | #gpio-cells = <1>; | |
7ec5183a SK |
204 | interrupt-controller; |
205 | #interrupt-cells = <2>; | |
65ebcc11 SK |
206 | reg = <0x1000 0x100>; |
207 | st,bank-name = "PIO6"; | |
208 | }; | |
209 | PIO7: gpio@fee02000 { | |
210 | gpio-controller; | |
211 | #gpio-cells = <1>; | |
7ec5183a SK |
212 | interrupt-controller; |
213 | #interrupt-cells = <2>; | |
65ebcc11 SK |
214 | reg = <0x2000 0x100>; |
215 | st,bank-name = "PIO7"; | |
216 | }; | |
217 | PIO8: gpio@fee03000 { | |
218 | gpio-controller; | |
219 | #gpio-cells = <1>; | |
7ec5183a SK |
220 | interrupt-controller; |
221 | #interrupt-cells = <2>; | |
65ebcc11 SK |
222 | reg = <0x3000 0x100>; |
223 | st,bank-name = "PIO8"; | |
224 | }; | |
225 | PIO9: gpio@fee04000 { | |
226 | gpio-controller; | |
227 | #gpio-cells = <1>; | |
7ec5183a SK |
228 | interrupt-controller; |
229 | #interrupt-cells = <2>; | |
65ebcc11 SK |
230 | reg = <0x4000 0x100>; |
231 | st,bank-name = "PIO9"; | |
232 | }; | |
233 | PIO10: gpio@fee05000 { | |
234 | gpio-controller; | |
235 | #gpio-cells = <1>; | |
7ec5183a SK |
236 | interrupt-controller; |
237 | #interrupt-cells = <2>; | |
65ebcc11 SK |
238 | reg = <0x5000 0x100>; |
239 | st,bank-name = "PIO10"; | |
240 | }; | |
241 | PIO11: gpio@fee06000 { | |
242 | gpio-controller; | |
243 | #gpio-cells = <1>; | |
7ec5183a SK |
244 | interrupt-controller; |
245 | #interrupt-cells = <2>; | |
65ebcc11 SK |
246 | reg = <0x6000 0x100>; |
247 | st,bank-name = "PIO11"; | |
248 | }; | |
249 | PIO12: gpio@fee07000 { | |
250 | gpio-controller; | |
251 | #gpio-cells = <1>; | |
7ec5183a SK |
252 | interrupt-controller; |
253 | #interrupt-cells = <2>; | |
65ebcc11 SK |
254 | reg = <0x7000 0x100>; |
255 | st,bank-name = "PIO12"; | |
256 | }; | |
5bbb7527 MC |
257 | |
258 | i2c0 { | |
259 | pinctrl_i2c0_default: i2c0-default { | |
260 | st,pins { | |
261 | sda = <&PIO9 3 ALT1 BIDIR>; | |
262 | scl = <&PIO9 2 ALT1 BIDIR>; | |
263 | }; | |
264 | }; | |
265 | }; | |
266 | ||
267 | i2c1 { | |
268 | pinctrl_i2c1_default: i2c1-default { | |
269 | st,pins { | |
270 | sda = <&PIO12 1 ALT1 BIDIR>; | |
271 | scl = <&PIO12 0 ALT1 BIDIR>; | |
272 | }; | |
273 | }; | |
274 | }; | |
65ebcc11 SK |
275 | }; |
276 | ||
277 | pin-controller-rear { | |
278 | #address-cells = <1>; | |
279 | #size-cells = <1>; | |
280 | compatible = "st,stih415-rear-pinctrl"; | |
281 | st,syscfg = <&syscfg_rear>; | |
7ec5183a SK |
282 | reg = <0xfe82f080 0x4>; |
283 | reg-names = "irqmux"; | |
284 | interrupts = <GIC_SPI 182 IRQ_TYPE_LEVEL_HIGH>; | |
ae107d06 | 285 | interrupt-names = "irqmux"; |
65ebcc11 SK |
286 | ranges = <0 0xfe820000 0x8000>; |
287 | ||
288 | PIO13: gpio@fe820000 { | |
289 | gpio-controller; | |
290 | #gpio-cells = <1>; | |
7ec5183a SK |
291 | interrupt-controller; |
292 | #interrupt-cells = <2>; | |
65ebcc11 SK |
293 | reg = <0 0x100>; |
294 | st,bank-name = "PIO13"; | |
295 | }; | |
296 | PIO14: gpio@fe821000 { | |
297 | gpio-controller; | |
298 | #gpio-cells = <1>; | |
7ec5183a SK |
299 | interrupt-controller; |
300 | #interrupt-cells = <2>; | |
65ebcc11 SK |
301 | reg = <0x1000 0x100>; |
302 | st,bank-name = "PIO14"; | |
303 | }; | |
304 | PIO15: gpio@fe822000 { | |
305 | gpio-controller; | |
306 | #gpio-cells = <1>; | |
7ec5183a SK |
307 | interrupt-controller; |
308 | #interrupt-cells = <2>; | |
65ebcc11 SK |
309 | reg = <0x2000 0x100>; |
310 | st,bank-name = "PIO15"; | |
311 | }; | |
312 | PIO16: gpio@fe823000 { | |
313 | gpio-controller; | |
314 | #gpio-cells = <1>; | |
7ec5183a SK |
315 | interrupt-controller; |
316 | #interrupt-cells = <2>; | |
65ebcc11 SK |
317 | reg = <0x3000 0x100>; |
318 | st,bank-name = "PIO16"; | |
319 | }; | |
320 | PIO17: gpio@fe824000 { | |
321 | gpio-controller; | |
322 | #gpio-cells = <1>; | |
7ec5183a SK |
323 | interrupt-controller; |
324 | #interrupt-cells = <2>; | |
65ebcc11 SK |
325 | reg = <0x4000 0x100>; |
326 | st,bank-name = "PIO17"; | |
327 | }; | |
328 | PIO18: gpio@fe825000 { | |
329 | gpio-controller; | |
330 | #gpio-cells = <1>; | |
7ec5183a SK |
331 | interrupt-controller; |
332 | #interrupt-cells = <2>; | |
65ebcc11 SK |
333 | reg = <0x5000 0x100>; |
334 | st,bank-name = "PIO18"; | |
335 | }; | |
336 | ||
337 | serial2 { | |
338 | pinctrl_serial2: serial2-0 { | |
339 | st,pins { | |
340 | tx = <&PIO17 4 ALT2 OUT>; | |
341 | rx = <&PIO17 5 ALT2 IN>; | |
342 | }; | |
343 | }; | |
344 | }; | |
c80fe335 SK |
345 | |
346 | gmac0{ | |
347 | pinctrl_mii0: mii0 { | |
348 | st,pins { | |
349 | mdint = <&PIO13 6 ALT2 IN BYPASS 0>; | |
350 | txen = <&PIO13 7 ALT2 OUT SE_NICLK_IO 0 CLK_A>; | |
351 | ||
352 | txd0 = <&PIO14 0 ALT2 OUT SE_NICLK_IO 0 CLK_A>; | |
353 | txd1 = <&PIO14 1 ALT2 OUT SE_NICLK_IO 0 CLK_A>; | |
354 | txd2 = <&PIO14 2 ALT2 OUT SE_NICLK_IO 0 CLK_B>; | |
355 | txd3 = <&PIO14 3 ALT2 OUT SE_NICLK_IO 0 CLK_B>; | |
356 | ||
357 | txclk = <&PIO15 0 ALT2 IN NICLK 0 CLK_A>; | |
358 | txer = <&PIO15 1 ALT2 OUT SE_NICLK_IO 0 CLK_A>; | |
359 | crs = <&PIO15 2 ALT2 IN BYPASS 1000>; | |
360 | col = <&PIO15 3 ALT2 IN BYPASS 1000>; | |
361 | mdio = <&PIO15 4 ALT2 OUT BYPASS 3000>; | |
362 | mdc = <&PIO15 5 ALT2 OUT NICLK 0 CLK_B>; | |
363 | ||
364 | rxd0 = <&PIO16 0 ALT2 IN SE_NICLK_IO 0 CLK_A>; | |
365 | rxd1 = <&PIO16 1 ALT2 IN SE_NICLK_IO 0 CLK_A>; | |
366 | rxd2 = <&PIO16 2 ALT2 IN SE_NICLK_IO 0 CLK_A>; | |
367 | rxd3 = <&PIO16 3 ALT2 IN SE_NICLK_IO 0 CLK_A>; | |
368 | rxdv = <&PIO15 6 ALT2 IN SE_NICLK_IO 0 CLK_A>; | |
369 | rx_er = <&PIO15 7 ALT2 IN SE_NICLK_IO 0 CLK_A>; | |
370 | rxclk = <&PIO17 0 ALT2 IN NICLK 0 CLK_A>; | |
371 | phyclk = <&PIO13 5 ALT2 OUT NICLK 1000 CLK_A>; | |
372 | ||
373 | }; | |
374 | }; | |
375 | ||
376 | pinctrl_gmii0: gmii0 { | |
377 | st,pins { | |
378 | mdint = <&PIO13 6 ALT2 IN BYPASS 0>; | |
379 | mdio = <&PIO15 4 ALT2 OUT BYPASS 3000>; | |
380 | mdc = <&PIO15 5 ALT2 OUT NICLK 0 CLK_B>; | |
381 | txen = <&PIO13 7 ALT2 OUT SE_NICLK_IO 3000 CLK_A>; | |
382 | ||
383 | txd0 = <&PIO14 0 ALT2 OUT SE_NICLK_IO 3000 CLK_A>; | |
384 | txd1 = <&PIO14 1 ALT2 OUT SE_NICLK_IO 3000 CLK_A>; | |
385 | txd2 = <&PIO14 2 ALT2 OUT SE_NICLK_IO 3000 CLK_B>; | |
386 | txd3 = <&PIO14 3 ALT2 OUT SE_NICLK_IO 3000 CLK_B>; | |
387 | txd4 = <&PIO14 4 ALT2 OUT SE_NICLK_IO 3000 CLK_B>; | |
388 | txd5 = <&PIO14 5 ALT2 OUT SE_NICLK_IO 3000 CLK_B>; | |
389 | txd6 = <&PIO14 6 ALT2 OUT SE_NICLK_IO 3000 CLK_B>; | |
390 | txd7 = <&PIO14 7 ALT2 OUT SE_NICLK_IO 3000 CLK_B>; | |
391 | ||
392 | txclk = <&PIO15 0 ALT2 IN NICLK 0 CLK_A>; | |
393 | txer = <&PIO15 1 ALT2 OUT SE_NICLK_IO 3000 CLK_A>; | |
394 | crs = <&PIO15 2 ALT2 IN BYPASS 1000>; | |
395 | col = <&PIO15 3 ALT2 IN BYPASS 1000>; | |
396 | rxdv = <&PIO15 6 ALT2 IN SE_NICLK_IO 1500 CLK_A>; | |
397 | rx_er = <&PIO15 7 ALT2 IN SE_NICLK_IO 1500 CLK_A>; | |
398 | ||
399 | rxd0 = <&PIO16 0 ALT2 IN SE_NICLK_IO 1500 CLK_A>; | |
400 | rxd1 = <&PIO16 1 ALT2 IN SE_NICLK_IO 1500 CLK_A>; | |
401 | rxd2 = <&PIO16 2 ALT2 IN SE_NICLK_IO 1500 CLK_A>; | |
402 | rxd3 = <&PIO16 3 ALT2 IN SE_NICLK_IO 1500 CLK_A>; | |
403 | rxd4 = <&PIO16 4 ALT2 IN SE_NICLK_IO 1500 CLK_A>; | |
404 | rxd5 = <&PIO16 5 ALT2 IN SE_NICLK_IO 1500 CLK_A>; | |
405 | rxd6 = <&PIO16 6 ALT2 IN SE_NICLK_IO 1500 CLK_A>; | |
406 | rxd7 = <&PIO16 7 ALT2 IN SE_NICLK_IO 1500 CLK_A>; | |
407 | ||
408 | rxclk = <&PIO17 0 ALT2 IN NICLK 0 CLK_A>; | |
409 | clk125 = <&PIO17 6 ALT1 IN NICLK 0 CLK_A>; | |
410 | phyclk = <&PIO13 5 ALT4 OUT NICLK 0 CLK_B>; | |
411 | ||
412 | ||
413 | }; | |
414 | }; | |
415 | }; | |
65ebcc11 SK |
416 | }; |
417 | ||
418 | pin-controller-left { | |
419 | #address-cells = <1>; | |
420 | #size-cells = <1>; | |
421 | compatible = "st,stih415-left-pinctrl"; | |
422 | st,syscfg = <&syscfg_left>; | |
7ec5183a SK |
423 | reg = <0xfd6bf080 0x4>; |
424 | reg-names = "irqmux"; | |
425 | interrupts = <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>; | |
ae107d06 | 426 | interrupt-names = "irqmux"; |
65ebcc11 SK |
427 | ranges = <0 0xfd6b0000 0x3000>; |
428 | ||
429 | PIO100: gpio@fd6b0000 { | |
430 | gpio-controller; | |
431 | #gpio-cells = <1>; | |
7ec5183a SK |
432 | interrupt-controller; |
433 | #interrupt-cells = <2>; | |
65ebcc11 SK |
434 | reg = <0 0x100>; |
435 | st,bank-name = "PIO100"; | |
436 | }; | |
437 | PIO101: gpio@fd6b1000 { | |
438 | gpio-controller; | |
439 | #gpio-cells = <1>; | |
7ec5183a SK |
440 | interrupt-controller; |
441 | #interrupt-cells = <2>; | |
65ebcc11 SK |
442 | reg = <0x1000 0x100>; |
443 | st,bank-name = "PIO101"; | |
444 | }; | |
445 | PIO102: gpio@fd6b2000 { | |
446 | gpio-controller; | |
447 | #gpio-cells = <1>; | |
7ec5183a SK |
448 | interrupt-controller; |
449 | #interrupt-cells = <2>; | |
65ebcc11 SK |
450 | reg = <0x2000 0x100>; |
451 | st,bank-name = "PIO102"; | |
452 | }; | |
453 | }; | |
454 | ||
455 | pin-controller-right { | |
456 | #address-cells = <1>; | |
457 | #size-cells = <1>; | |
458 | compatible = "st,stih415-right-pinctrl"; | |
459 | st,syscfg = <&syscfg_right>; | |
7ec5183a SK |
460 | reg = <0xfd33f080 0x4>; |
461 | reg-names = "irqmux"; | |
462 | interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>; | |
ae107d06 | 463 | interrupt-names = "irqmux"; |
65ebcc11 SK |
464 | ranges = <0 0xfd330000 0x5000>; |
465 | ||
466 | PIO103: gpio@fd330000 { | |
467 | gpio-controller; | |
468 | #gpio-cells = <1>; | |
7ec5183a SK |
469 | interrupt-controller; |
470 | #interrupt-cells = <2>; | |
65ebcc11 SK |
471 | reg = <0 0x100>; |
472 | st,bank-name = "PIO103"; | |
473 | }; | |
474 | PIO104: gpio@fd331000 { | |
475 | gpio-controller; | |
476 | #gpio-cells = <1>; | |
7ec5183a SK |
477 | interrupt-controller; |
478 | #interrupt-cells = <2>; | |
65ebcc11 SK |
479 | reg = <0x1000 0x100>; |
480 | st,bank-name = "PIO104"; | |
481 | }; | |
482 | PIO105: gpio@fd332000 { | |
483 | gpio-controller; | |
484 | #gpio-cells = <1>; | |
7ec5183a SK |
485 | interrupt-controller; |
486 | #interrupt-cells = <2>; | |
65ebcc11 SK |
487 | reg = <0x2000 0x100>; |
488 | st,bank-name = "PIO105"; | |
489 | }; | |
490 | PIO106: gpio@fd333000 { | |
491 | gpio-controller; | |
492 | #gpio-cells = <1>; | |
7ec5183a SK |
493 | interrupt-controller; |
494 | #interrupt-cells = <2>; | |
65ebcc11 SK |
495 | reg = <0x3000 0x100>; |
496 | st,bank-name = "PIO106"; | |
497 | }; | |
498 | PIO107: gpio@fd334000 { | |
499 | gpio-controller; | |
500 | #gpio-cells = <1>; | |
7ec5183a SK |
501 | interrupt-controller; |
502 | #interrupt-cells = <2>; | |
65ebcc11 SK |
503 | reg = <0x4000 0x100>; |
504 | st,bank-name = "PIO107"; | |
505 | }; | |
506 | }; | |
507 | }; | |
508 | }; |