[linux-2.6-block.git] / arch / arm / boot / dts / ste-href-family-pinctrl.dtsi

/*
 * Copyright 2013 Linaro Ltd.
 *
 * The code contained herein is licensed under the GNU General Public
 * License. You may obtain a copy of the GNU General Public License
 * Version 2 or later at the following locations:
 *
 * http://www.opensource.org/licenses/gpl-license.html
 * http://www.gnu.org/copyleft/gpl.html
 */

#include "ste-nomadik-pinctrl.dtsi"

/ {
	soc {
		pinctrl {
			/* Settings for all UART default and sleep states */
			uart0 {
				uart0_default_mode: uart0_default {
					default_mux {
						ste,function = "u0";
						ste,pins = "u0_a_1";
					};
					default_cfg1 {
						ste,pins = "GPIO0_AJ5", "GPIO2_AH4"; /* CTS+RXD */
						ste,config = <&in_pu>;
					};

					default_cfg2 {
						ste,pins = "GPIO1_AJ3", "GPIO3_AH3"; /* RTS+TXD */
						ste,config = <&out_hi>;
					};
				};

				uart0_sleep_mode: uart0_sleep {
					sleep_cfg1 {
						ste,pins = "GPIO0_AJ5", "GPIO2_AH4"; /* CTS+RXD */
						ste,config = <&slpm_in_wkup_pdis>;
					};

					sleep_cfg2 {
						ste,pins = "GPIO1_AJ3"; /* RTS */
						ste,config = <&slpm_out_hi_wkup_pdis>;
					};

					sleep_cfg3 {
						ste,pins = "GPIO3_AH3"; /* TXD */
						ste,config = <&slpm_out_wkup_pdis>;
					};
				};
			};

			uart1 {
				uart1_default_mode: uart1_default {
					default_mux {
						ste,function = "u1";
						ste,pins = "u1rxtx_a_1";
					};
					default_cfg1 {
						ste,pins = "GPIO4_AH6"; /* RXD */
						ste,config = <&in_pu>;
					};

					default_cfg2 {
						ste,pins = "GPIO5_AG6"; /* TXD */
						ste,config = <&out_hi>;
					};
				};

				uart1_sleep_mode: uart1_sleep {
					sleep_cfg1 {
						ste,pins = "GPIO4_AH6"; /* RXD */
						ste,config = <&slpm_in_wkup_pdis>;
					};

					sleep_cfg2 {
						ste,pins = "GPIO5_AG6"; /* TXD */
						ste,config = <&slpm_out_wkup_pdis>;
					};
				};
			};

			uart2 {
				uart2_default_mode: uart2_default {
					default_mux {
						ste,function = "u2";
						ste,pins = "u2rxtx_c_1";
					};
					default_cfg1 {
						ste,pins = "GPIO29_W2"; /* RXD */
						ste,config = <&in_pu>;
					};

					default_cfg2 {
						ste,pins = "GPIO30_W3"; /* TXD */
						ste,config = <&out_hi>;
					};
				};

				uart2_sleep_mode: uart2_sleep {
					sleep_cfg1 {
						ste,pins = "GPIO29_W2"; /* RXD */
						ste,config = <&in_wkup_pdis>;
					};

					sleep_cfg2 {
						ste,pins = "GPIO30_W3"; /* TXD */
						ste,config = <&out_wkup_pdis>;
					};
				};
			};

			/* Settings for all I2C default and sleep states */
			i2c0 {
				i2c0_default_mode: i2c_default {
					default_mux {
						ste,function = "i2c0";
						ste,pins = "i2c0_a_1";
					};
					default_cfg1 {
						ste,pins = "GPIO147_C15", "GPIO148_B16"; /* SDA/SCL */
						ste,config = <&in_pu>;
					};
				};

				i2c0_sleep_mode: i2c_sleep {
					sleep_cfg1 {
						ste,pins = "GPIO147_C15", "GPIO148_B16"; /* SDA/SCL */
						ste,config = <&slpm_in_wkup_pdis>;
					};
				};
			};

			i2c1 {
				i2c1_default_mode: i2c_default {
					default_mux {
						ste,function = "i2c1";
						ste,pins = "i2c1_b_2";
					};
					default_cfg1 {
						ste,pins = "GPIO16_AD3", "GPIO17_AD4"; /* SDA/SCL */
						ste,config = <&in_pu>;
					};
				};

				i2c1_sleep_mode: i2c_sleep {
					sleep_cfg1 {
						ste,pins = "GPIO16_AD3", "GPIO17_AD4"; /* SDA/SCL */
						ste,config = <&slpm_in_wkup_pdis>;
					};
				};
			};

			i2c2 {
				i2c2_default_mode: i2c_default {
					default_mux {
						ste,function = "i2c2";
						ste,pins = "i2c2_b_2";
					};
					default_cfg1 {
						ste,pins = "GPIO10_AF5", "GPIO11_AG4"; /* SDA/SCL */
						ste,config = <&in_pu>;
					};
				};

				i2c2_sleep_mode: i2c_sleep {
					sleep_cfg1 {
						ste,pins = "GPIO10_AF5", "GPIO11_AG4"; /* SDA/SCL */
						ste,config = <&slpm_in_wkup_pdis>;
					};
				};
			};

			i2c3 {
				i2c3_default_mode: i2c_default {
					default_mux {
						ste,function = "i2c3";
						ste,pins = "i2c3_c_2";
					};
					default_cfg1 {
						ste,pins = "GPIO229_AG7", "GPIO230_AF7"; /* SDA/SCL */
						ste,config = <&in_pu>;
					};
				};

				i2c3_sleep_mode: i2c_sleep {
					sleep_cfg1 {
						ste,pins = "GPIO229_AG7", "GPIO230_AF7"; /* SDA/SCL */
						ste,config = <&slpm_in_wkup_pdis>;
					};
				};
			};

			/*
			 * Activating I2C4 will conflict with UART1 about the same pins so do not
			 * enable I2C4 and UART1 at the same time.
			 */
			i2c4 {
				i2c4_default_mode: i2c_default {
					default_mux {
						ste,function = "i2c4";
						ste,pins = "i2c4_b_1";
					};
					default_cfg1 {
						ste,pins = "GPIO4_AH6", "GPIO5_AG6"; /* SDA/SCL */
						ste,config = <&in_pu>;
					};
				};

				i2c4_sleep_mode: i2c_sleep {
					sleep_cfg1 {
						ste,pins = "GPIO4_AH6", "GPIO5_AG6"; /* SDA/SCL */
						ste,config = <&slpm_in_wkup_pdis>;
					};
				};
			};

			/* Settings for all MMC/SD/SDIO default and sleep states */
			sdi0 {
				/* This is the external SD card slot, 4 bits wide */
				sdi0_default_mode: sdi0_default {
					default_mux {
						ste,function = "mc0";
						ste,pins = "mc0_a_1";
					};
					default_cfg1 {
						ste,pins =
						"GPIO18_AC2", /* CMDDIR */
						"GPIO19_AC1", /* DAT0DIR */
						"GPIO20_AB4"; /* DAT2DIR */
						ste,config = <&out_hi>;
					};
					default_cfg2 {
						ste,pins = "GPIO22_AA3"; /* FBCLK */
						ste,config = <&in_nopull>;
					};
					default_cfg3 {
						ste,pins = "GPIO23_AA4"; /* CLK */
						ste,config = <&out_lo>;
					};
					default_cfg4 {
						ste,pins =
						"GPIO24_AB2", /* CMD */
						"GPIO25_Y4", /* DAT0 */
						"GPIO26_Y2", /* DAT1 */
						"GPIO27_AA2", /* DAT2 */
						"GPIO28_AA1"; /* DAT3 */
						ste,config = <&in_pu>;
					};
				};

				sdi0_sleep_mode: sdi0_sleep {
					sleep_cfg1 {
						ste,pins =
						"GPIO18_AC2", /* CMDDIR */
						"GPIO19_AC1", /* DAT0DIR */
						"GPIO20_AB4"; /* DAT2DIR */
						ste,config = <&slpm_out_hi_wkup_pdis>;
					};
					sleep_cfg2 {
						ste,pins =
						"GPIO22_AA3", /* FBCLK */
						"GPIO24_AB2", /* CMD */
						"GPIO25_Y4", /* DAT0 */
						"GPIO26_Y2", /* DAT1 */
						"GPIO27_AA2", /* DAT2 */
						"GPIO28_AA1"; /* DAT3 */
						ste,config = <&slpm_in_wkup_pdis>;
					};
					sleep_cfg3 {
						ste,pins = "GPIO23_AA4"; /* CLK */
						ste,config = <&slpm_out_lo_wkup_pdis>;
					};
				};
			};

			sdi1 {
				/* This is the WLAN SDIO 4 bits wide */
				sdi1_default_mode: sdi1_default {
					default_mux {
						ste,function = "mc1";
						ste,pins = "mc1_a_1";
					};
					default_cfg1 {
						ste,pins = "GPIO208_AH16"; /* CLK */
						ste,config = <&out_lo>;
					};
					default_cfg2 {
						ste,pins = "GPIO209_AG15"; /* FBCLK */
						ste,config = <&in_nopull>;
					};
					default_cfg3 {
						ste,pins =
						"GPIO210_AJ15", /* CMD */
						"GPIO211_AG14", /* DAT0 */
						"GPIO212_AF13", /* DAT1 */
						"GPIO213_AG13", /* DAT2 */
						"GPIO214_AH15"; /* DAT3 */
						ste,config = <&in_pu>;
					};
				};

				sdi1_sleep_mode: sdi1_sleep {
					sleep_cfg1 {
						ste,pins = "GPIO208_AH16"; /* CLK */
						ste,config = <&slpm_out_lo_wkup_pdis>;
					};
					sleep_cfg2 {
						ste,pins =
						"GPIO209_AG15", /* FBCLK */
						"GPIO210_AJ15", /* CMD */
						"GPIO211_AG14", /* DAT0 */
						"GPIO212_AF13", /* DAT1 */
						"GPIO213_AG13", /* DAT2 */
						"GPIO214_AH15"; /* DAT3 */
						ste,config = <&slpm_in_wkup_pdis>;
					};
				};
			};

			sdi2 {
				/* This is the eMMC 8 bits wide, usually PoP eMMC */
				sdi2_default_mode: sdi2_default {
					default_mux {
						ste,function = "mc2";
						ste,pins = "mc2_a_1";
					};
					default_cfg1 {
						ste,pins = "GPIO128_A5"; /* CLK */
						ste,config = <&out_lo>;
					};
					default_cfg2 {
						ste,pins = "GPIO130_C8"; /* FBCLK */
						ste,config = <&in_nopull>;
					};
					default_cfg3 {
						ste,pins =
						"GPIO129_B4", /* CMD */
						"GPIO131_A12", /* DAT0 */
						"GPIO132_C10", /* DAT1 */
						"GPIO133_B10", /* DAT2 */
						"GPIO134_B9", /* DAT3 */
						"GPIO135_A9", /* DAT4 */
						"GPIO136_C7", /* DAT5 */
						"GPIO137_A7", /* DAT6 */
						"GPIO138_C5"; /* DAT7 */
						ste,config = <&in_pu>;
					};
				};

				sdi2_sleep_mode: sdi2_sleep {
					sleep_cfg1 {
						ste,pins = "GPIO128_A5"; /* CLK */
						ste,config = <&out_lo_wkup_pdis>;
					};
					sleep_cfg2 {
						ste,pins =
						"GPIO130_C8", /* FBCLK */
						"GPIO129_B4"; /* CMD */
						ste,config = <&in_wkup_pdis_en>;
					};
					sleep_cfg3 {
						ste,pins =
						"GPIO131_A12", /* DAT0 */
						"GPIO132_C10", /* DAT1 */
						"GPIO133_B10", /* DAT2 */
						"GPIO134_B9", /* DAT3 */
						"GPIO135_A9", /* DAT4 */
						"GPIO136_C7", /* DAT5 */
						"GPIO137_A7", /* DAT6 */
						"GPIO138_C5"; /* DAT7 */
						ste,config = <&in_wkup_pdis>;
					};
				};
			};

			sdi4 {
				/* This is the eMMC 8 bits wide, usually PCB-mounted eMMC */
				sdi4_default_mode: sdi4_default {
					default_mux {
						ste,function = "mc4";
						ste,pins = "mc4_a_1";
					};
					default_cfg1 {
						ste,pins = "GPIO203_AE23"; /* CLK */
						ste,config = <&out_lo>;
					};
					default_cfg2 {
						ste,pins = "GPIO202_AF25"; /* FBCLK */
						ste,config = <&in_nopull>;
					};
					default_cfg3 {
						ste,pins =
						"GPIO201_AF24", /* CMD */
						"GPIO200_AH26", /* DAT0 */
						"GPIO199_AH23", /* DAT1 */
						"GPIO198_AG25", /* DAT2 */
						"GPIO197_AH24", /* DAT3 */
						"GPIO207_AJ23", /* DAT4 */
						"GPIO206_AG24", /* DAT5 */
						"GPIO205_AG23", /* DAT6 */
						"GPIO204_AF23"; /* DAT7 */
						ste,config = <&in_pu>;
					};
				};

				sdi4_sleep_mode: sdi4_sleep {
					sleep_cfg1 {
						ste,pins = "GPIO203_AE23"; /* CLK */
						ste,config = <&out_lo_wkup_pdis>;
					};
					sleep_cfg2 {
						ste,pins =
						"GPIO202_AF25", /* FBCLK */
						"GPIO201_AF24", /* CMD */
						"GPIO200_AH26", /* DAT0 */
						"GPIO199_AH23", /* DAT1 */
						"GPIO198_AG25", /* DAT2 */
						"GPIO197_AH24", /* DAT3 */
						"GPIO207_AJ23", /* DAT4 */
						"GPIO206_AG24", /* DAT5 */
						"GPIO205_AG23", /* DAT6 */
						"GPIO204_AF23"; /* DAT7 */
						ste,config = <&slpm_in_wkup_pdis>;
					};
				};
			};

			/*
			 * Multi-rate serial ports (MSPs) - MSP3 output is internal and
			 * cannot be muxed onto any pins.
			 */
			msp0 {
				msp0_default_mode: msp0_default {
					default_msp0_mux {
						ste,function = "msp0";
						ste,pins = "msp0txrx_a_1", "msp0tfstck_a_1";
					};
					default_msp0_cfg {
						ste,pins =
						"GPIO12_AC4", /* TXD */
						"GPIO15_AC3", /* RXD */
						"GPIO13_AF3", /* TFS */
						"GPIO14_AE3"; /* TCK */
						ste,config = <&in_nopull>;
					};
				};
			};

			msp1 {
				msp1_default_mode: msp1_default {
					default_mux {
						ste,function = "msp1";
						ste,pins = "msp1txrx_a_1", "msp1_a_1";
					};
					default_cfg1 {
						ste,pins = "GPIO33_AF2";
						ste,config = <&out_lo>;
					};
					default_cfg2 {
						ste,pins =
						"GPIO34_AE1",
						"GPIO35_AE2",
						"GPIO36_AG2";
						ste,config = <&in_nopull>;
					};

				};
			};

			msp2 {
				msp2_default_mode: msp2_default {
					/* MSP2 usually used for HDMI audio */
					default_mux {
						ste,function = "msp2";
						ste,pins = "msp2_a_1";
					};
					default_cfg1 {
						ste,pins =
						"GPIO193_AH27", /* TXD */
						"GPIO194_AF27", /* TCK */
						"GPIO195_AG28"; /* TFS */
						ste,config = <&in_pd>;
					};
					default_cfg2 {
						ste,pins = "GPIO196_AG26"; /* RXD */
						ste,config = <&out_lo>;
					};
				};
			};
		};
	};
};
Commit	Line	Data
3bfdebba LW	1	/*
	2	* Copyright 2013 Linaro Ltd.
	3	*
	4	* The code contained herein is licensed under the GNU General Public
	5	* License. You may obtain a copy of the GNU General Public License
	6	* Version 2 or later at the following locations:
	7	*
	8	* http://www.opensource.org/licenses/gpl-license.html
	9	* http://www.gnu.org/copyleft/gpl.html
	10	*/
	11
	12	#include "ste-nomadik-pinctrl.dtsi"
	13
	14	/ {
	15	soc {
	16	pinctrl {
	17	/* Settings for all UART default and sleep states */
	18	uart0 {
	19	uart0_default_mode: uart0_default {
	20	default_mux {
	21	ste,function = "u0";
	22	ste,pins = "u0_a_1";
	23	};
	24	default_cfg1 {
	25	ste,pins = "GPIO0_AJ5", "GPIO2_AH4"; /* CTS+RXD */
	26	ste,config = <&in_pu>;
	27	};
	28
	29	default_cfg2 {
	30	ste,pins = "GPIO1_AJ3", "GPIO3_AH3"; /* RTS+TXD */
	31	ste,config = <&out_hi>;
	32	};
	33	};
	34
	35	uart0_sleep_mode: uart0_sleep {
	36	sleep_cfg1 {
	37	ste,pins = "GPIO0_AJ5", "GPIO2_AH4"; /* CTS+RXD */
	38	ste,config = <&slpm_in_wkup_pdis>;
	39	};
	40
	41	sleep_cfg2 {
	42	ste,pins = "GPIO1_AJ3"; /* RTS */
	43	ste,config = <&slpm_out_hi_wkup_pdis>;
	44	};
	45
	46	sleep_cfg3 {
	47	ste,pins = "GPIO3_AH3"; /* TXD */
	48	ste,config = <&slpm_out_wkup_pdis>;
	49	};
	50	};
	51	};
	52
	53	uart1 {
	54	uart1_default_mode: uart1_default {
	55	default_mux {
	56	ste,function = "u1";
	57	ste,pins = "u1rxtx_a_1";
	58	};
	59	default_cfg1 {
	60	ste,pins = "GPIO4_AH6"; /* RXD */
	61	ste,config = <&in_pu>;
	62	};
	63
	64	default_cfg2 {
65	ste,pins = "GPIO5_AG6"; /* TXD */
66	ste,config = <&out_hi>;
67	};
68	};
69
70	uart1_sleep_mode: uart1_sleep {
71	sleep_cfg1 {
72	ste,pins = "GPIO4_AH6"; /* RXD */
73	ste,config = <&slpm_in_wkup_pdis>;
74	};
75
76	sleep_cfg2 {
77	ste,pins = "GPIO5_AG6"; /* TXD */
78	ste,config = <&slpm_out_wkup_pdis>;
79	};
80	};
81	};
82
83	uart2 {
84	uart2_default_mode: uart2_default {
85	default_mux {
86	ste,function = "u2";
87	ste,pins = "u2rxtx_c_1";
88	};
89	default_cfg1 {
90	ste,pins = "GPIO29_W2"; /* RXD */
91	ste,config = <&in_pu>;
92	};
93
94	default_cfg2 {
95	ste,pins = "GPIO30_W3"; /* TXD */
96	ste,config = <&out_hi>;
97	};
98	};
99
100	uart2_sleep_mode: uart2_sleep {
101	sleep_cfg1 {
102	ste,pins = "GPIO29_W2"; /* RXD */
103	ste,config = <&in_wkup_pdis>;
104	};
105
106	sleep_cfg2 {
107	ste,pins = "GPIO30_W3"; /* TXD */
108	ste,config = <&out_wkup_pdis>;
109	};
110	};
111	};
96fee13f LW	112
	113	/* Settings for all I2C default and sleep states */
	114	i2c0 {
	115	i2c0_default_mode: i2c_default {
	116	default_mux {
	117	ste,function = "i2c0";
	118	ste,pins = "i2c0_a_1";
	119	};
	120	default_cfg1 {
	121	ste,pins = "GPIO147_C15", "GPIO148_B16"; /* SDA/SCL */
	122	ste,config = <&in_pu>;
	123	};
	124	};
	125
	126	i2c0_sleep_mode: i2c_sleep {
	127	sleep_cfg1 {
	128	ste,pins = "GPIO147_C15", "GPIO148_B16"; /* SDA/SCL */
	129	ste,config = <&slpm_in_wkup_pdis>;
	130	};
	131	};
	132	};
	133
	134	i2c1 {
	135	i2c1_default_mode: i2c_default {
	136	default_mux {
	137	ste,function = "i2c1";
	138	ste,pins = "i2c1_b_2";
	139	};
	140	default_cfg1 {
	141	ste,pins = "GPIO16_AD3", "GPIO17_AD4"; /* SDA/SCL */
	142	ste,config = <&in_pu>;
	143	};
	144	};
	145
	146	i2c1_sleep_mode: i2c_sleep {
	147	sleep_cfg1 {
	148	ste,pins = "GPIO16_AD3", "GPIO17_AD4"; /* SDA/SCL */
	149	ste,config = <&slpm_in_wkup_pdis>;
	150	};
	151	};
	152	};
	153
	154	i2c2 {
	155	i2c2_default_mode: i2c_default {
	156	default_mux {
	157	ste,function = "i2c2";
	158	ste,pins = "i2c2_b_2";
	159	};
	160	default_cfg1 {
	161	ste,pins = "GPIO10_AF5", "GPIO11_AG4"; /* SDA/SCL */
	162	ste,config = <&in_pu>;
	163	};
	164	};
	165
	166	i2c2_sleep_mode: i2c_sleep {
	167	sleep_cfg1 {
	168	ste,pins = "GPIO10_AF5", "GPIO11_AG4"; /* SDA/SCL */
	169	ste,config = <&slpm_in_wkup_pdis>;
	170	};
	171	};
	172	};
	173
	174	i2c3 {
	175	i2c3_default_mode: i2c_default {
176	default_mux {
177	ste,function = "i2c3";
178	ste,pins = "i2c3_c_2";
179	};
180	default_cfg1 {
181	ste,pins = "GPIO229_AG7", "GPIO230_AF7"; /* SDA/SCL */
182	ste,config = <&in_pu>;
183	};
184	};
185
186	i2c3_sleep_mode: i2c_sleep {
187	sleep_cfg1 {
188	ste,pins = "GPIO229_AG7", "GPIO230_AF7"; /* SDA/SCL */
189	ste,config = <&slpm_in_wkup_pdis>;
190	};
191	};
192	};
193
194	/*
195	* Activating I2C4 will conflict with UART1 about the same pins so do not
196	* enable I2C4 and UART1 at the same time.
197	*/
198	i2c4 {
199	i2c4_default_mode: i2c_default {
200	default_mux {
201	ste,function = "i2c4";
202	ste,pins = "i2c4_b_1";
203	};
204	default_cfg1 {
205	ste,pins = "GPIO4_AH6", "GPIO5_AG6"; /* SDA/SCL */
206	ste,config = <&in_pu>;
207	};
208	};
209
210	i2c4_sleep_mode: i2c_sleep {
211	sleep_cfg1 {
212	ste,pins = "GPIO4_AH6", "GPIO5_AG6"; /* SDA/SCL */
213	ste,config = <&slpm_in_wkup_pdis>;
214	};
215	};
216	};
1e662353 LW	217
	218	/* Settings for all MMC/SD/SDIO default and sleep states */
	219	sdi0 {
	220	/* This is the external SD card slot, 4 bits wide */
	221	sdi0_default_mode: sdi0_default {
	222	default_mux {
	223	ste,function = "mc0";
	224	ste,pins = "mc0_a_1";
	225	};
	226	default_cfg1 {
	227	ste,pins =
	228	"GPIO18_AC2", /* CMDDIR */
	229	"GPIO19_AC1", /* DAT0DIR */
	230	"GPIO20_AB4"; /* DAT2DIR */
	231	ste,config = <&out_hi>;
	232	};
	233	default_cfg2 {
	234	ste,pins = "GPIO22_AA3"; /* FBCLK */
	235	ste,config = <&in_nopull>;
	236	};
	237	default_cfg3 {
	238	ste,pins = "GPIO23_AA4"; /* CLK */
	239	ste,config = <&out_lo>;
	240	};
	241	default_cfg4 {
	242	ste,pins =
	243	"GPIO24_AB2", /* CMD */
	244	"GPIO25_Y4", /* DAT0 */
	245	"GPIO26_Y2", /* DAT1 */
	246	"GPIO27_AA2", /* DAT2 */
	247	"GPIO28_AA1"; /* DAT3 */
	248	ste,config = <&in_pu>;
	249	};
	250	};
	251
	252	sdi0_sleep_mode: sdi0_sleep {
	253	sleep_cfg1 {
	254	ste,pins =
	255	"GPIO18_AC2", /* CMDDIR */
	256	"GPIO19_AC1", /* DAT0DIR */
	257	"GPIO20_AB4"; /* DAT2DIR */
	258	ste,config = <&slpm_out_hi_wkup_pdis>;
	259	};
	260	sleep_cfg2 {
	261	ste,pins =
	262	"GPIO22_AA3", /* FBCLK */
	263	"GPIO24_AB2", /* CMD */
	264	"GPIO25_Y4", /* DAT0 */
	265	"GPIO26_Y2", /* DAT1 */
	266	"GPIO27_AA2", /* DAT2 */
	267	"GPIO28_AA1"; /* DAT3 */
	268	ste,config = <&slpm_in_wkup_pdis>;
	269	};
	270	sleep_cfg3 {
	271	ste,pins = "GPIO23_AA4"; /* CLK */
	272	ste,config = <&slpm_out_lo_wkup_pdis>;
	273	};
	274	};
	275	};
	276
	277	sdi1 {
	278	/* This is the WLAN SDIO 4 bits wide */
	279	sdi1_default_mode: sdi1_default {
	280	default_mux {
281	ste,function = "mc1";
282	ste,pins = "mc1_a_1";
283	};
284	default_cfg1 {
285	ste,pins = "GPIO208_AH16"; /* CLK */
286	ste,config = <&out_lo>;
287	};
288	default_cfg2 {
289	ste,pins = "GPIO209_AG15"; /* FBCLK */
290	ste,config = <&in_nopull>;
291	};
292	default_cfg3 {
293	ste,pins =
294	"GPIO210_AJ15", /* CMD */
295	"GPIO211_AG14", /* DAT0 */
296	"GPIO212_AF13", /* DAT1 */
297	"GPIO213_AG13", /* DAT2 */
298	"GPIO214_AH15"; /* DAT3 */
299	ste,config = <&in_pu>;
300	};
301	};
302
303	sdi1_sleep_mode: sdi1_sleep {
304	sleep_cfg1 {
305	ste,pins = "GPIO208_AH16"; /* CLK */
306	ste,config = <&slpm_out_lo_wkup_pdis>;
307	};
308	sleep_cfg2 {
309	ste,pins =
310	"GPIO209_AG15", /* FBCLK */
311	"GPIO210_AJ15", /* CMD */
312	"GPIO211_AG14", /* DAT0 */
313	"GPIO212_AF13", /* DAT1 */
314	"GPIO213_AG13", /* DAT2 */
315	"GPIO214_AH15"; /* DAT3 */
316	ste,config = <&slpm_in_wkup_pdis>;
317	};
318	};
319	};
320
321	sdi2 {
322	/* This is the eMMC 8 bits wide, usually PoP eMMC */
323	sdi2_default_mode: sdi2_default {
324	default_mux {
325	ste,function = "mc2";
326	ste,pins = "mc2_a_1";
327	};
328	default_cfg1 {
329	ste,pins = "GPIO128_A5"; /* CLK */
330	ste,config = <&out_lo>;
331	};
332	default_cfg2 {
333	ste,pins = "GPIO130_C8"; /* FBCLK */
334	ste,config = <&in_nopull>;
335	};
336	default_cfg3 {
337	ste,pins =
338	"GPIO129_B4", /* CMD */
339	"GPIO131_A12", /* DAT0 */
340	"GPIO132_C10", /* DAT1 */
341	"GPIO133_B10", /* DAT2 */
342	"GPIO134_B9", /* DAT3 */
343	"GPIO135_A9", /* DAT4 */
344	"GPIO136_C7", /* DAT5 */
345	"GPIO137_A7", /* DAT6 */
346	"GPIO138_C5"; /* DAT7 */
347	ste,config = <&in_pu>;
348	};
349	};
350
351	sdi2_sleep_mode: sdi2_sleep {
352	sleep_cfg1 {
353	ste,pins = "GPIO128_A5"; /* CLK */
354	ste,config = <&out_lo_wkup_pdis>;
355	};
356	sleep_cfg2 {
357	ste,pins =
358	"GPIO130_C8", /* FBCLK */
359	"GPIO129_B4"; /* CMD */
360	ste,config = <&in_wkup_pdis_en>;
361	};
362	sleep_cfg3 {
363	ste,pins =
364	"GPIO131_A12", /* DAT0 */
365	"GPIO132_C10", /* DAT1 */
366	"GPIO133_B10", /* DAT2 */
367	"GPIO134_B9", /* DAT3 */
368	"GPIO135_A9", /* DAT4 */
369	"GPIO136_C7", /* DAT5 */
370	"GPIO137_A7", /* DAT6 */
371	"GPIO138_C5"; /* DAT7 */
372	ste,config = <&in_wkup_pdis>;
373	};
374	};
375	};
376
377	sdi4 {
378	/* This is the eMMC 8 bits wide, usually PCB-mounted eMMC */
379	sdi4_default_mode: sdi4_default {
380	default_mux {
381	ste,function = "mc4";
382	ste,pins = "mc4_a_1";
383	};
384	default_cfg1 {
385	ste,pins = "GPIO203_AE23"; /* CLK */
386	ste,config = <&out_lo>;
387	};
388	default_cfg2 {
389	ste,pins = "GPIO202_AF25"; /* FBCLK */
390	ste,config = <&in_nopull>;
391	};
392	default_cfg3 {
393	ste,pins =
394	"GPIO201_AF24", /* CMD */
395	"GPIO200_AH26", /* DAT0 */
396	"GPIO199_AH23", /* DAT1 */
397	"GPIO198_AG25", /* DAT2 */
398	"GPIO197_AH24", /* DAT3 */
399	"GPIO207_AJ23", /* DAT4 */
400	"GPIO206_AG24", /* DAT5 */
401	"GPIO205_AG23", /* DAT6 */
402	"GPIO204_AF23"; /* DAT7 */
403	ste,config = <&in_pu>;
404	};
405	};
406
407	sdi4_sleep_mode: sdi4_sleep {
408	sleep_cfg1 {
409	ste,pins = "GPIO203_AE23"; /* CLK */
410	ste,config = <&out_lo_wkup_pdis>;
411	};
412	sleep_cfg2 {
413	ste,pins =
414	"GPIO202_AF25", /* FBCLK */
415	"GPIO201_AF24", /* CMD */
416	"GPIO200_AH26", /* DAT0 */
417	"GPIO199_AH23", /* DAT1 */
418	"GPIO198_AG25", /* DAT2 */
419	"GPIO197_AH24", /* DAT3 */
420	"GPIO207_AJ23", /* DAT4 */
421	"GPIO206_AG24", /* DAT5 */
422	"GPIO205_AG23", /* DAT6 */
423	"GPIO204_AF23"; /* DAT7 */
424	ste,config = <&slpm_in_wkup_pdis>;
425	};
426	};
427	};
70b41abc LW	428
	429	/*
	430	* Multi-rate serial ports (MSPs) - MSP3 output is internal and
	431	* cannot be muxed onto any pins.
	432	*/
	433	msp0 {
	434	msp0_default_mode: msp0_default {
	435	default_msp0_mux {
	436	ste,function = "msp0";
	437	ste,pins = "msp0txrx_a_1", "msp0tfstck_a_1";
	438	};
	439	default_msp0_cfg {
	440	ste,pins =
	441	"GPIO12_AC4", /* TXD */
	442	"GPIO15_AC3", /* RXD */
	443	"GPIO13_AF3", /* TFS */
	444	"GPIO14_AE3"; /* TCK */
	445	ste,config = <&in_nopull>;
	446	};
	447	};
	448	};
	449
	450	msp1 {
	451	msp1_default_mode: msp1_default {
	452	default_mux {
	453	ste,function = "msp1";
	454	ste,pins = "msp1txrx_a_1", "msp1_a_1";
	455	};
	456	default_cfg1 {
	457	ste,pins = "GPIO33_AF2";
	458	ste,config = <&out_lo>;
	459	};
	460	default_cfg2 {
	461	ste,pins =
	462	"GPIO34_AE1",
	463	"GPIO35_AE2",
	464	"GPIO36_AG2";
	465	ste,config = <&in_nopull>;
	466	};
	467
	468	};
	469	};
	470
	471	msp2 {
	472	msp2_default_mode: msp2_default {
	473	/* MSP2 usually used for HDMI audio */
	474	default_mux {
	475	ste,function = "msp2";
	476	ste,pins = "msp2_a_1";
	477	};
	478	default_cfg1 {
	479	ste,pins =
	480	"GPIO193_AH27", /* TXD */
	481	"GPIO194_AF27", /* TCK */
	482	"GPIO195_AG28"; /* TFS */
	483	ste,config = <&in_pd>;
	484	};
	485	default_cfg2 {
	486	ste,pins = "GPIO196_AG26"; /* RXD */
	487	ste,config = <&out_lo>;
	488	};
	489	};
	490	};
3bfdebba LW	491	};
	492	};
	493	};