Commit | Line | Data |
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5d0769f0 AB |
1 | /* |
2 | * Copyright 2012 Linaro Ltd | |
3 | * | |
4 | * The code contained herein is licensed under the GNU General Public | |
5 | * License. You may obtain a copy of the GNU General Public License | |
6 | * Version 2 or later at the following locations: | |
7 | * | |
8 | * http://www.opensource.org/licenses/gpl-license.html | |
9 | * http://www.gnu.org/copyleft/gpl.html | |
10 | */ | |
11 | ||
90c40257 | 12 | #include <dt-bindings/interrupt-controller/irq.h> |
0bfe5167 | 13 | #include <dt-bindings/interrupt-controller/arm-gic.h> |
841cd0c0 | 14 | #include <dt-bindings/mfd/dbx500-prcmu.h> |
067addec | 15 | #include <dt-bindings/arm/ux500_pm_domains.h> |
1b1e8e02 | 16 | #include <dt-bindings/gpio/gpio.h> |
9aea151f | 17 | #include <dt-bindings/clock/ste-ab8500.h> |
807e8838 | 18 | #include "skeleton.dtsi" |
5d0769f0 AB |
19 | |
20 | / { | |
bf64dd26 LW |
21 | cpus { |
22 | #address-cells = <1>; | |
23 | #size-cells = <0>; | |
24 | enable-method = "ste,dbx500-smp"; | |
25 | ||
26 | cpu-map { | |
27 | cluster0 { | |
28 | core0 { | |
29 | cpu = <&CPU0>; | |
30 | }; | |
31 | core1 { | |
32 | cpu = <&CPU1>; | |
33 | }; | |
34 | }; | |
35 | }; | |
36 | CPU0: cpu@300 { | |
37 | device_type = "cpu"; | |
38 | compatible = "arm,cortex-a9"; | |
39 | reg = <0x300>; | |
a435adbe LW |
40 | /* cpufreq controls */ |
41 | operating-points = <998400 0 | |
42 | 800000 0 | |
43 | 400000 0 | |
44 | 200000 0>; | |
45 | clocks = <&prcmu_clk PRCMU_ARMSS>; | |
46 | clock-names = "cpu"; | |
47 | clock-latency = <20000>; | |
bf64dd26 LW |
48 | }; |
49 | CPU1: cpu@301 { | |
50 | device_type = "cpu"; | |
51 | compatible = "arm,cortex-a9"; | |
52 | reg = <0x301>; | |
53 | }; | |
54 | }; | |
55 | ||
b1ba1439 | 56 | soc { |
5d0769f0 AB |
57 | #address-cells = <1>; |
58 | #size-cells = <1>; | |
7e0ce270 | 59 | compatible = "stericsson,db8500"; |
dab6487e | 60 | interrupt-parent = <&intc>; |
5d0769f0 | 61 | ranges; |
7e0ce270 | 62 | |
b557457f LW |
63 | ptm@801ae000 { |
64 | compatible = "arm,coresight-etm3x", "arm,primecell"; | |
65 | reg = <0x801ae000 0x1000>; | |
66 | ||
67 | clocks = <&prcmu_clk PRCMU_APETRACECLK>, <&prcmu_clk PRCMU_APEATCLK>; | |
68 | clock-names = "apb_pclk", "atclk"; | |
69 | cpu = <&CPU0>; | |
70 | port { | |
71 | ptm0_out_port: endpoint { | |
72 | remote-endpoint = <&funnel_in_port0>; | |
73 | }; | |
74 | }; | |
75 | }; | |
76 | ||
77 | ptm@801af000 { | |
78 | compatible = "arm,coresight-etm3x", "arm,primecell"; | |
79 | reg = <0x801af000 0x1000>; | |
80 | ||
81 | clocks = <&prcmu_clk PRCMU_APETRACECLK>, <&prcmu_clk PRCMU_APEATCLK>; | |
82 | clock-names = "apb_pclk", "atclk"; | |
83 | cpu = <&CPU1>; | |
84 | port { | |
85 | ptm1_out_port: endpoint { | |
86 | remote-endpoint = <&funnel_in_port1>; | |
87 | }; | |
88 | }; | |
89 | }; | |
90 | ||
91 | funnel@801a6000 { | |
92 | compatible = "arm,coresight-funnel", "arm,primecell"; | |
93 | reg = <0x801a6000 0x1000>; | |
94 | ||
95 | clocks = <&prcmu_clk PRCMU_APETRACECLK>, <&prcmu_clk PRCMU_APEATCLK>; | |
96 | clock-names = "apb_pclk", "atclk"; | |
97 | ports { | |
98 | #address-cells = <1>; | |
99 | #size-cells = <0>; | |
100 | ||
101 | /* funnel output ports */ | |
102 | port@0 { | |
103 | reg = <0>; | |
104 | funnel_out_port: endpoint { | |
105 | remote-endpoint = | |
106 | <&replicator_in_port0>; | |
107 | }; | |
108 | }; | |
109 | ||
110 | /* funnel input ports */ | |
111 | port@1 { | |
112 | reg = <0>; | |
113 | funnel_in_port0: endpoint { | |
114 | slave-mode; | |
115 | remote-endpoint = <&ptm0_out_port>; | |
116 | }; | |
117 | }; | |
118 | ||
119 | port@2 { | |
120 | reg = <1>; | |
121 | funnel_in_port1: endpoint { | |
122 | slave-mode; | |
123 | remote-endpoint = <&ptm1_out_port>; | |
124 | }; | |
125 | }; | |
126 | }; | |
127 | }; | |
128 | ||
129 | replicator { | |
130 | compatible = "arm,coresight-replicator"; | |
131 | clocks = <&prcmu_clk PRCMU_APEATCLK>; | |
132 | clock-names = "atclk"; | |
133 | ||
134 | ports { | |
135 | #address-cells = <1>; | |
136 | #size-cells = <0>; | |
137 | ||
138 | /* replicator output ports */ | |
139 | port@0 { | |
140 | reg = <0>; | |
141 | replicator_out_port0: endpoint { | |
142 | remote-endpoint = <&tpiu_in_port>; | |
143 | }; | |
144 | }; | |
145 | port@1 { | |
146 | reg = <1>; | |
147 | replicator_out_port1: endpoint { | |
148 | remote-endpoint = <&etb_in_port>; | |
149 | }; | |
150 | }; | |
151 | ||
152 | /* replicator input port */ | |
153 | port@2 { | |
154 | reg = <0>; | |
155 | replicator_in_port0: endpoint { | |
156 | slave-mode; | |
157 | remote-endpoint = <&funnel_out_port>; | |
158 | }; | |
159 | }; | |
160 | }; | |
161 | }; | |
162 | ||
163 | tpiu@80190000 { | |
164 | compatible = "arm,coresight-tpiu", "arm,primecell"; | |
165 | reg = <0x80190000 0x1000>; | |
166 | ||
167 | clocks = <&prcmu_clk PRCMU_APETRACECLK>, <&prcmu_clk PRCMU_APEATCLK>; | |
168 | clock-names = "apb_pclk", "atclk"; | |
169 | port { | |
170 | tpiu_in_port: endpoint { | |
171 | slave-mode; | |
172 | remote-endpoint = <&replicator_out_port0>; | |
173 | }; | |
174 | }; | |
175 | }; | |
176 | ||
177 | etb@801a4000 { | |
178 | compatible = "arm,coresight-etb10", "arm,primecell"; | |
179 | reg = <0x801a4000 0x1000>; | |
180 | ||
181 | clocks = <&prcmu_clk PRCMU_APETRACECLK>, <&prcmu_clk PRCMU_APEATCLK>; | |
182 | clock-names = "apb_pclk", "atclk"; | |
183 | port { | |
184 | etb_in_port: endpoint { | |
185 | slave-mode; | |
186 | remote-endpoint = <&replicator_out_port1>; | |
187 | }; | |
188 | }; | |
189 | }; | |
190 | ||
dab6487e LJ |
191 | intc: interrupt-controller@a0411000 { |
192 | compatible = "arm,cortex-a9-gic"; | |
193 | #interrupt-cells = <3>; | |
194 | #address-cells = <1>; | |
195 | interrupt-controller; | |
dab6487e LJ |
196 | reg = <0xa0411000 0x1000>, |
197 | <0xa0410100 0x100>; | |
198 | }; | |
199 | ||
48793410 LW |
200 | scu@a04100000 { |
201 | compatible = "arm,cortex-a9-scu"; | |
202 | reg = <0xa0410000 0x100>; | |
203 | }; | |
204 | ||
724814b4 LW |
205 | /* |
206 | * The backup RAM is used for retention during sleep | |
207 | * and various things like spin tables | |
208 | */ | |
209 | backupram@80150000 { | |
210 | compatible = "ste,dbx500-backupram"; | |
211 | reg = <0x80150000 0x2000>; | |
212 | }; | |
213 | ||
f1949ea0 LJ |
214 | L2: l2-cache { |
215 | compatible = "arm,pl310-cache"; | |
216 | reg = <0xa0412000 0x1000>; | |
0bfe5167 | 217 | interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>; |
f1949ea0 LJ |
218 | cache-unified; |
219 | cache-level = <2>; | |
220 | }; | |
221 | ||
7e0ce270 LJ |
222 | pmu { |
223 | compatible = "arm,cortex-a9-pmu"; | |
0bfe5167 | 224 | interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>; |
7e0ce270 LJ |
225 | }; |
226 | ||
6c669359 UH |
227 | pm_domains: pm_domains0 { |
228 | compatible = "stericsson,ux500-pm-domains"; | |
229 | #power-domain-cells = <1>; | |
230 | }; | |
8132ed1b | 231 | |
841cd0c0 LJ |
232 | clocks { |
233 | compatible = "stericsson,u8500-clks"; | |
5dc0fe19 LW |
234 | /* |
235 | * Registers for the CLKRST block on peripheral | |
236 | * groups 1, 2, 3, 5, 6, | |
237 | */ | |
238 | reg = <0x8012f000 0x1000>, <0x8011f000 0x1000>, | |
239 | <0x8000f000 0x1000>, <0xa03ff000 0x1000>, | |
240 | <0xa03cf000 0x1000>; | |
841cd0c0 LJ |
241 | |
242 | prcmu_clk: prcmu-clock { | |
243 | #clock-cells = <1>; | |
244 | }; | |
fcbe5e90 LJ |
245 | |
246 | prcc_pclk: prcc-periph-clock { | |
247 | #clock-cells = <2>; | |
248 | }; | |
2588fea6 LJ |
249 | |
250 | prcc_kclk: prcc-kernel-clock { | |
251 | #clock-cells = <2>; | |
252 | }; | |
589d9839 LJ |
253 | |
254 | rtc_clk: rtc32k-clock { | |
255 | #clock-cells = <0>; | |
256 | }; | |
309012d7 LJ |
257 | |
258 | smp_twd_clk: smp-twd-clock { | |
259 | #clock-cells = <0>; | |
260 | }; | |
841cd0c0 LJ |
261 | }; |
262 | ||
8132ed1b LJ |
263 | mtu@a03c6000 { |
264 | /* Nomadik System Timer */ | |
265 | compatible = "st,nomadik-mtu"; | |
266 | reg = <0xa03c6000 0x1000>; | |
0bfe5167 | 267 | interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>; |
8132ed1b LJ |
268 | |
269 | clocks = <&prcmu_clk PRCMU_TIMCLK>, <&prcc_pclk 6 6>; | |
270 | clock-names = "timclk", "apb_pclk"; | |
271 | }; | |
272 | ||
71de5c46 LJ |
273 | timer@a0410600 { |
274 | compatible = "arm,cortex-a9-twd-timer"; | |
275 | reg = <0xa0410600 0x20>; | |
0bfe5167 | 276 | interrupts = <GIC_PPI 13 (GIC_CPU_MASK_RAW(3) | IRQ_TYPE_LEVEL_HIGH)>; |
a8acb1ec LJ |
277 | |
278 | clocks = <&smp_twd_clk>; | |
71de5c46 LJ |
279 | }; |
280 | ||
48793410 LW |
281 | watchdog@a0410620 { |
282 | compatible = "arm,cortex-a9-twd-wdt"; | |
283 | reg = <0xa0410620 0x20>; | |
0bfe5167 | 284 | interrupts = <GIC_PPI 14 (GIC_CPU_MASK_RAW(3) | IRQ_TYPE_LEVEL_HIGH)>; |
48793410 LW |
285 | clocks = <&smp_twd_clk>; |
286 | }; | |
287 | ||
7e0ce270 | 288 | rtc@80154000 { |
ddb3b99c | 289 | compatible = "arm,rtc-pl031", "arm,primecell"; |
7e0ce270 | 290 | reg = <0x80154000 0x1000>; |
0bfe5167 | 291 | interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>; |
d299b5a5 LJ |
292 | |
293 | clocks = <&rtc_clk>; | |
294 | clock-names = "apb_pclk"; | |
7e0ce270 LJ |
295 | }; |
296 | ||
297 | gpio0: gpio@8012e000 { | |
298 | compatible = "stericsson,db8500-gpio", | |
fd9a80b2 | 299 | "st,nomadik-gpio"; |
7e0ce270 | 300 | reg = <0x8012e000 0x80>; |
0bfe5167 | 301 | interrupts = <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>; |
93b5698a LJ |
302 | interrupt-controller; |
303 | #interrupt-cells = <2>; | |
61be4981 | 304 | st,supports-sleepmode; |
7e0ce270 | 305 | gpio-controller; |
c0b133bd LJ |
306 | #gpio-cells = <2>; |
307 | gpio-bank = <0>; | |
ee04139d | 308 | gpio-ranges = <&pinctrl 0 0 32>; |
9d891073 | 309 | clocks = <&prcc_pclk 1 9>; |
7e0ce270 LJ |
310 | }; |
311 | ||
312 | gpio1: gpio@8012e080 { | |
313 | compatible = "stericsson,db8500-gpio", | |
fd9a80b2 | 314 | "st,nomadik-gpio"; |
7e0ce270 | 315 | reg = <0x8012e080 0x80>; |
0bfe5167 | 316 | interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>; |
93b5698a LJ |
317 | interrupt-controller; |
318 | #interrupt-cells = <2>; | |
61be4981 | 319 | st,supports-sleepmode; |
7e0ce270 | 320 | gpio-controller; |
c0b133bd LJ |
321 | #gpio-cells = <2>; |
322 | gpio-bank = <1>; | |
ee04139d | 323 | gpio-ranges = <&pinctrl 0 32 5>; |
9d891073 | 324 | clocks = <&prcc_pclk 1 9>; |
7e0ce270 LJ |
325 | }; |
326 | ||
327 | gpio2: gpio@8000e000 { | |
328 | compatible = "stericsson,db8500-gpio", | |
fd9a80b2 | 329 | "st,nomadik-gpio"; |
7e0ce270 | 330 | reg = <0x8000e000 0x80>; |
0bfe5167 | 331 | interrupts = <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>; |
93b5698a LJ |
332 | interrupt-controller; |
333 | #interrupt-cells = <2>; | |
61be4981 | 334 | st,supports-sleepmode; |
7e0ce270 | 335 | gpio-controller; |
c0b133bd LJ |
336 | #gpio-cells = <2>; |
337 | gpio-bank = <2>; | |
ee04139d | 338 | gpio-ranges = <&pinctrl 0 64 32>; |
9d891073 | 339 | clocks = <&prcc_pclk 3 8>; |
7e0ce270 LJ |
340 | }; |
341 | ||
342 | gpio3: gpio@8000e080 { | |
343 | compatible = "stericsson,db8500-gpio", | |
fd9a80b2 | 344 | "st,nomadik-gpio"; |
7e0ce270 | 345 | reg = <0x8000e080 0x80>; |
0bfe5167 | 346 | interrupts = <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>; |
93b5698a LJ |
347 | interrupt-controller; |
348 | #interrupt-cells = <2>; | |
61be4981 | 349 | st,supports-sleepmode; |
7e0ce270 | 350 | gpio-controller; |
c0b133bd LJ |
351 | #gpio-cells = <2>; |
352 | gpio-bank = <3>; | |
ee04139d | 353 | gpio-ranges = <&pinctrl 0 96 2>; |
9d891073 | 354 | clocks = <&prcc_pclk 3 8>; |
7e0ce270 LJ |
355 | }; |
356 | ||
357 | gpio4: gpio@8000e100 { | |
358 | compatible = "stericsson,db8500-gpio", | |
fd9a80b2 | 359 | "st,nomadik-gpio"; |
7e0ce270 | 360 | reg = <0x8000e100 0x80>; |
0bfe5167 | 361 | interrupts = <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>; |
93b5698a LJ |
362 | interrupt-controller; |
363 | #interrupt-cells = <2>; | |
61be4981 | 364 | st,supports-sleepmode; |
7e0ce270 | 365 | gpio-controller; |
c0b133bd LJ |
366 | #gpio-cells = <2>; |
367 | gpio-bank = <4>; | |
ee04139d | 368 | gpio-ranges = <&pinctrl 0 128 32>; |
9d891073 | 369 | clocks = <&prcc_pclk 3 8>; |
7e0ce270 LJ |
370 | }; |
371 | ||
372 | gpio5: gpio@8000e180 { | |
373 | compatible = "stericsson,db8500-gpio", | |
fd9a80b2 | 374 | "st,nomadik-gpio"; |
7e0ce270 | 375 | reg = <0x8000e180 0x80>; |
0bfe5167 | 376 | interrupts = <GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>; |
93b5698a LJ |
377 | interrupt-controller; |
378 | #interrupt-cells = <2>; | |
61be4981 | 379 | st,supports-sleepmode; |
7e0ce270 | 380 | gpio-controller; |
c0b133bd LJ |
381 | #gpio-cells = <2>; |
382 | gpio-bank = <5>; | |
ee04139d | 383 | gpio-ranges = <&pinctrl 0 160 12>; |
9d891073 | 384 | clocks = <&prcc_pclk 3 8>; |
7e0ce270 LJ |
385 | }; |
386 | ||
387 | gpio6: gpio@8011e000 { | |
388 | compatible = "stericsson,db8500-gpio", | |
fd9a80b2 | 389 | "st,nomadik-gpio"; |
7e0ce270 | 390 | reg = <0x8011e000 0x80>; |
0bfe5167 | 391 | interrupts = <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>; |
93b5698a LJ |
392 | interrupt-controller; |
393 | #interrupt-cells = <2>; | |
61be4981 | 394 | st,supports-sleepmode; |
7e0ce270 | 395 | gpio-controller; |
c0b133bd LJ |
396 | #gpio-cells = <2>; |
397 | gpio-bank = <6>; | |
ee04139d | 398 | gpio-ranges = <&pinctrl 0 192 32>; |
d591640a | 399 | clocks = <&prcc_pclk 2 11>; |
7e0ce270 LJ |
400 | }; |
401 | ||
402 | gpio7: gpio@8011e080 { | |
403 | compatible = "stericsson,db8500-gpio", | |
fd9a80b2 | 404 | "st,nomadik-gpio"; |
7e0ce270 | 405 | reg = <0x8011e080 0x80>; |
0bfe5167 | 406 | interrupts = <GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>; |
93b5698a LJ |
407 | interrupt-controller; |
408 | #interrupt-cells = <2>; | |
61be4981 | 409 | st,supports-sleepmode; |
7e0ce270 | 410 | gpio-controller; |
c0b133bd LJ |
411 | #gpio-cells = <2>; |
412 | gpio-bank = <7>; | |
ee04139d | 413 | gpio-ranges = <&pinctrl 0 224 7>; |
d591640a | 414 | clocks = <&prcc_pclk 2 11>; |
7e0ce270 LJ |
415 | }; |
416 | ||
417 | gpio8: gpio@a03fe000 { | |
418 | compatible = "stericsson,db8500-gpio", | |
fd9a80b2 | 419 | "st,nomadik-gpio"; |
7e0ce270 | 420 | reg = <0xa03fe000 0x80>; |
0bfe5167 | 421 | interrupts = <GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>; |
93b5698a LJ |
422 | interrupt-controller; |
423 | #interrupt-cells = <2>; | |
61be4981 | 424 | st,supports-sleepmode; |
7e0ce270 | 425 | gpio-controller; |
c0b133bd LJ |
426 | #gpio-cells = <2>; |
427 | gpio-bank = <8>; | |
ee04139d | 428 | gpio-ranges = <&pinctrl 0 256 12>; |
84873cb7 | 429 | clocks = <&prcc_pclk 5 1>; |
7e0ce270 LJ |
430 | }; |
431 | ||
ee04139d | 432 | pinctrl: pinctrl { |
818d99a9 | 433 | compatible = "stericsson,db8500-pinctrl"; |
ee04139d LW |
434 | nomadik-gpio-chips = <&gpio0>, <&gpio1>, <&gpio2>, <&gpio3>, |
435 | <&gpio4>, <&gpio5>, <&gpio6>, <&gpio7>, | |
436 | <&gpio8>; | |
8979cfef | 437 | prcm = <&prcmu>; |
5910de9e LJ |
438 | }; |
439 | ||
b32dc865 | 440 | usb_per5@a03e0000 { |
4a6cd43f | 441 | compatible = "stericsson,db8500-musb"; |
7e0ce270 | 442 | reg = <0xa03e0000 0x10000>; |
0bfe5167 | 443 | interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>; |
b32dc865 LJ |
444 | interrupt-names = "mc"; |
445 | ||
446 | dr_mode = "otg"; | |
447 | ||
448 | dmas = <&dma 38 0 0x2>, /* Logical - DevToMem */ | |
449 | <&dma 38 0 0x0>, /* Logical - MemToDev */ | |
450 | <&dma 37 0 0x2>, /* Logical - DevToMem */ | |
451 | <&dma 37 0 0x0>, /* Logical - MemToDev */ | |
452 | <&dma 36 0 0x2>, /* Logical - DevToMem */ | |
453 | <&dma 36 0 0x0>, /* Logical - MemToDev */ | |
454 | <&dma 19 0 0x2>, /* Logical - DevToMem */ | |
455 | <&dma 19 0 0x0>, /* Logical - MemToDev */ | |
456 | <&dma 18 0 0x2>, /* Logical - DevToMem */ | |
457 | <&dma 18 0 0x0>, /* Logical - MemToDev */ | |
458 | <&dma 17 0 0x2>, /* Logical - DevToMem */ | |
459 | <&dma 17 0 0x0>, /* Logical - MemToDev */ | |
460 | <&dma 16 0 0x2>, /* Logical - DevToMem */ | |
461 | <&dma 16 0 0x0>, /* Logical - MemToDev */ | |
462 | <&dma 39 0 0x2>, /* Logical - DevToMem */ | |
463 | <&dma 39 0 0x0>; /* Logical - MemToDev */ | |
464 | ||
465 | dma-names = "iep_1_9", "oep_1_9", | |
466 | "iep_2_10", "oep_2_10", | |
467 | "iep_3_11", "oep_3_11", | |
468 | "iep_4_12", "oep_4_12", | |
469 | "iep_5_13", "oep_5_13", | |
470 | "iep_6_14", "oep_6_14", | |
471 | "iep_7_15", "oep_7_15", | |
472 | "iep_8", "oep_8"; | |
e47339ff LJ |
473 | |
474 | clocks = <&prcc_pclk 5 0>; | |
7e0ce270 LJ |
475 | }; |
476 | ||
ba074aec LJ |
477 | dma: dma-controller@801C0000 { |
478 | compatible = "stericsson,db8500-dma40", "stericsson,dma40"; | |
7e0ce270 | 479 | reg = <0x801C0000 0x1000 0x40010000 0x800>; |
70d39a8d | 480 | reg-names = "base", "lcpa"; |
0bfe5167 | 481 | interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>; |
ba074aec LJ |
482 | |
483 | #dma-cells = <3>; | |
d37fcdb6 | 484 | memcpy-channels = <56 57 58 59 60>; |
e064cb24 LJ |
485 | |
486 | clocks = <&prcmu_clk PRCMU_DMACLK>; | |
7e0ce270 LJ |
487 | }; |
488 | ||
8979cfef | 489 | prcmu: prcmu@80157000 { |
7e0ce270 | 490 | compatible = "stericsson,db8500-prcmu"; |
4d26aa30 | 491 | reg = <0x80157000 0x2000>, <0x801b0000 0x8000>, <0x801b8000 0x1000>; |
e73081d9 | 492 | reg-names = "prcmu", "prcmu-tcpm", "prcmu-tcdm"; |
0bfe5167 | 493 | interrupts = <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>; |
7e0ce270 | 494 | #address-cells = <1>; |
3de3d749 | 495 | #size-cells = <1>; |
c09090bb LJ |
496 | interrupt-controller; |
497 | #interrupt-cells = <2>; | |
3de3d749 LJ |
498 | ranges; |
499 | ||
ccf74f76 | 500 | prcmu-timer-4@80157450 { |
3de3d749 LJ |
501 | compatible = "stericsson,db8500-prcmu-timer-4"; |
502 | reg = <0x80157450 0xC>; | |
503 | }; | |
7e0ce270 | 504 | |
dc1956b5 | 505 | thermal@801573c0 { |
506 | compatible = "stericsson,db8500-thermal"; | |
507 | reg = <0x801573c0 0x40>; | |
90c40257 LW |
508 | interrupts = <21 IRQ_TYPE_LEVEL_HIGH>, |
509 | <22 IRQ_TYPE_LEVEL_HIGH>; | |
dc1956b5 | 510 | interrupt-names = "IRQ_HOTMON_LOW", "IRQ_HOTMON_HIGH"; |
511 | status = "disabled"; | |
1d3f99f5 | 512 | }; |
dc1956b5 | 513 | |
e5999f28 LJ |
514 | db8500-prcmu-regulators { |
515 | compatible = "stericsson,db8500-prcmu-regulator"; | |
516 | ||
517 | // DB8500_REGULATOR_VAPE | |
518 | db8500_vape_reg: db8500_vape { | |
e5999f28 LJ |
519 | regulator-always-on; |
520 | }; | |
521 | ||
522 | // DB8500_REGULATOR_VARM | |
523 | db8500_varm_reg: db8500_varm { | |
e5999f28 LJ |
524 | }; |
525 | ||
526 | // DB8500_REGULATOR_VMODEM | |
527 | db8500_vmodem_reg: db8500_vmodem { | |
e5999f28 LJ |
528 | }; |
529 | ||
530 | // DB8500_REGULATOR_VPLL | |
531 | db8500_vpll_reg: db8500_vpll { | |
e5999f28 LJ |
532 | }; |
533 | ||
534 | // DB8500_REGULATOR_VSMPS1 | |
535 | db8500_vsmps1_reg: db8500_vsmps1 { | |
e5999f28 LJ |
536 | }; |
537 | ||
538 | // DB8500_REGULATOR_VSMPS2 | |
539 | db8500_vsmps2_reg: db8500_vsmps2 { | |
e5999f28 LJ |
540 | }; |
541 | ||
542 | // DB8500_REGULATOR_VSMPS3 | |
543 | db8500_vsmps3_reg: db8500_vsmps3 { | |
e5999f28 LJ |
544 | }; |
545 | ||
546 | // DB8500_REGULATOR_VRF1 | |
547 | db8500_vrf1_reg: db8500_vrf1 { | |
e5999f28 LJ |
548 | }; |
549 | ||
550 | // DB8500_REGULATOR_SWITCH_SVAMMDSP | |
551 | db8500_sva_mmdsp_reg: db8500_sva_mmdsp { | |
e5999f28 LJ |
552 | }; |
553 | ||
554 | // DB8500_REGULATOR_SWITCH_SVAMMDSPRET | |
555 | db8500_sva_mmdsp_ret_reg: db8500_sva_mmdsp_ret { | |
e5999f28 LJ |
556 | }; |
557 | ||
558 | // DB8500_REGULATOR_SWITCH_SVAPIPE | |
559 | db8500_sva_pipe_reg: db8500_sva_pipe { | |
e5999f28 LJ |
560 | }; |
561 | ||
562 | // DB8500_REGULATOR_SWITCH_SIAMMDSP | |
563 | db8500_sia_mmdsp_reg: db8500_sia_mmdsp { | |
e5999f28 LJ |
564 | }; |
565 | ||
566 | // DB8500_REGULATOR_SWITCH_SIAMMDSPRET | |
567 | db8500_sia_mmdsp_ret_reg: db8500_sia_mmdsp_ret { | |
e5999f28 LJ |
568 | }; |
569 | ||
570 | // DB8500_REGULATOR_SWITCH_SIAPIPE | |
571 | db8500_sia_pipe_reg: db8500_sia_pipe { | |
e5999f28 LJ |
572 | }; |
573 | ||
574 | // DB8500_REGULATOR_SWITCH_SGA | |
575 | db8500_sga_reg: db8500_sga { | |
e5999f28 LJ |
576 | vin-supply = <&db8500_vape_reg>; |
577 | }; | |
578 | ||
579 | // DB8500_REGULATOR_SWITCH_B2R2_MCDE | |
580 | db8500_b2r2_mcde_reg: db8500_b2r2_mcde { | |
e5999f28 LJ |
581 | vin-supply = <&db8500_vape_reg>; |
582 | }; | |
583 | ||
584 | // DB8500_REGULATOR_SWITCH_ESRAM12 | |
585 | db8500_esram12_reg: db8500_esram12 { | |
e5999f28 LJ |
586 | }; |
587 | ||
588 | // DB8500_REGULATOR_SWITCH_ESRAM12RET | |
589 | db8500_esram12_ret_reg: db8500_esram12_ret { | |
e5999f28 LJ |
590 | }; |
591 | ||
592 | // DB8500_REGULATOR_SWITCH_ESRAM34 | |
593 | db8500_esram34_reg: db8500_esram34 { | |
e5999f28 LJ |
594 | }; |
595 | ||
596 | // DB8500_REGULATOR_SWITCH_ESRAM34RET | |
597 | db8500_esram34_ret_reg: db8500_esram34_ret { | |
e5999f28 LJ |
598 | }; |
599 | }; | |
600 | ||
d52701d3 | 601 | ab8500 { |
7e0ce270 | 602 | compatible = "stericsson,ab8500"; |
8d4c6d45 | 603 | interrupt-parent = <&intc>; |
0bfe5167 | 604 | interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>; |
732973c8 LJ |
605 | interrupt-controller; |
606 | #interrupt-cells = <2>; | |
4a85c7fa | 607 | |
9aea151f LW |
608 | ab8500_clock: clock-controller { |
609 | compatible = "stericsson,ab8500-clk"; | |
610 | #clock-cells = <1>; | |
611 | }; | |
612 | ||
348f3bc6 | 613 | ab8500_gpio: ab8500-gpio { |
ba3fb047 | 614 | compatible = "stericsson,ab8500-gpio"; |
348f3bc6 LJ |
615 | gpio-controller; |
616 | #gpio-cells = <2>; | |
617 | }; | |
618 | ||
d4b29ac1 LJ |
619 | ab8500-rtc { |
620 | compatible = "stericsson,ab8500-rtc"; | |
90c40257 LW |
621 | interrupts = <17 IRQ_TYPE_LEVEL_HIGH |
622 | 18 IRQ_TYPE_LEVEL_HIGH>; | |
d4b29ac1 LJ |
623 | interrupt-names = "60S", "ALARM"; |
624 | }; | |
625 | ||
4eda9129 LJ |
626 | ab8500-gpadc { |
627 | compatible = "stericsson,ab8500-gpadc"; | |
90c40257 LW |
628 | interrupts = <32 IRQ_TYPE_LEVEL_HIGH |
629 | 39 IRQ_TYPE_LEVEL_HIGH>; | |
4eda9129 LJ |
630 | interrupt-names = "HW_CONV_END", "SW_CONV_END"; |
631 | vddadc-supply = <&ab8500_ldo_tvout_reg>; | |
632 | }; | |
633 | ||
e0f1abeb R |
634 | ab8500_battery: ab8500_battery { |
635 | stericsson,battery-type = "LIPO"; | |
636 | thermistor-on-batctrl; | |
637 | }; | |
638 | ||
639 | ab8500_fg { | |
640 | compatible = "stericsson,ab8500-fg"; | |
641 | battery = <&ab8500_battery>; | |
642 | }; | |
643 | ||
bd9e8ab2 R |
644 | ab8500_btemp { |
645 | compatible = "stericsson,ab8500-btemp"; | |
646 | battery = <&ab8500_battery>; | |
647 | }; | |
648 | ||
4aef72db R |
649 | ab8500_charger { |
650 | compatible = "stericsson,ab8500-charger"; | |
651 | battery = <&ab8500_battery>; | |
652 | vddadc-supply = <&ab8500_ldo_tvout_reg>; | |
653 | }; | |
654 | ||
a12810ab R |
655 | ab8500_chargalg { |
656 | compatible = "stericsson,ab8500-chargalg"; | |
657 | battery = <&ab8500_battery>; | |
658 | }; | |
659 | ||
e0f1abeb | 660 | ab8500_usb { |
ee189cef | 661 | compatible = "stericsson,ab8500-usb"; |
90c40257 LW |
662 | interrupts = < 90 IRQ_TYPE_LEVEL_HIGH |
663 | 96 IRQ_TYPE_LEVEL_HIGH | |
664 | 14 IRQ_TYPE_LEVEL_HIGH | |
665 | 15 IRQ_TYPE_LEVEL_HIGH | |
666 | 79 IRQ_TYPE_LEVEL_HIGH | |
667 | 74 IRQ_TYPE_LEVEL_HIGH | |
668 | 75 IRQ_TYPE_LEVEL_HIGH>; | |
ee189cef LJ |
669 | interrupt-names = "ID_WAKEUP_R", |
670 | "ID_WAKEUP_F", | |
671 | "VBUS_DET_F", | |
672 | "VBUS_DET_R", | |
673 | "USB_LINK_STATUS", | |
674 | "USB_ADP_PROBE_PLUG", | |
675 | "USB_ADP_PROBE_UNPLUG"; | |
99b38eef | 676 | vddulpivio18-supply = <&ab8500_ldo_intcore_reg>; |
ee189cef LJ |
677 | v-ape-supply = <&db8500_vape_reg>; |
678 | musb_1v8-supply = <&db8500_vsmps2_reg>; | |
3015d3b0 LW |
679 | clocks = <&prcmu_clk PRCMU_SYSCLK>; |
680 | clock-names = "sysclk"; | |
ee189cef LJ |
681 | }; |
682 | ||
12cb7bd4 | 683 | ab8500-ponkey { |
74630706 | 684 | compatible = "stericsson,ab8500-poweron-key"; |
90c40257 LW |
685 | interrupts = <6 IRQ_TYPE_LEVEL_HIGH |
686 | 7 IRQ_TYPE_LEVEL_HIGH>; | |
12cb7bd4 LJ |
687 | interrupt-names = "ONKEY_DBF", "ONKEY_DBR"; |
688 | }; | |
689 | ||
401cd1b8 LJ |
690 | ab8500-sysctrl { |
691 | compatible = "stericsson,ab8500-sysctrl"; | |
692 | }; | |
693 | ||
78451de7 LJ |
694 | ab8500-pwm { |
695 | compatible = "stericsson,ab8500-pwm"; | |
9aea151f LW |
696 | clocks = <&ab8500_clock AB8500_SYSCLK_INT>; |
697 | clock-names = "intclk"; | |
78451de7 LJ |
698 | }; |
699 | ||
215891ec LJ |
700 | ab8500-debugfs { |
701 | compatible = "stericsson,ab8500-debug"; | |
702 | }; | |
4a85c7fa | 703 | |
9c06af30 LJ |
704 | codec: ab8500-codec { |
705 | compatible = "stericsson,ab8500-codec"; | |
706 | ||
f99808a6 FB |
707 | V-AUD-supply = <&ab8500_ldo_audio_reg>; |
708 | V-AMIC1-supply = <&ab8500_ldo_anamic1_reg>; | |
709 | V-AMIC2-supply = <&ab8500_ldo_anamic2_reg>; | |
710 | V-DMIC-supply = <&ab8500_ldo_dmic_reg>; | |
711 | ||
9aea151f LW |
712 | clocks = <&ab8500_clock AB8500_SYSCLK_AUDIO>; |
713 | clock-names = "audioclk"; | |
714 | ||
9c06af30 LJ |
715 | stericsson,earpeice-cmv = <950>; /* Units in mV. */ |
716 | }; | |
717 | ||
62ebfe6b LJ |
718 | ext_regulators: ab8500-ext-regulators { |
719 | compatible = "stericsson,ab8500-ext-regulator"; | |
720 | ||
721 | ab8500_ext1_reg: ab8500_ext1 { | |
62ebfe6b LJ |
722 | regulator-min-microvolt = <1800000>; |
723 | regulator-max-microvolt = <1800000>; | |
724 | regulator-boot-on; | |
725 | regulator-always-on; | |
726 | }; | |
727 | ||
728 | ab8500_ext2_reg: ab8500_ext2 { | |
62ebfe6b LJ |
729 | regulator-min-microvolt = <1360000>; |
730 | regulator-max-microvolt = <1360000>; | |
731 | regulator-boot-on; | |
732 | regulator-always-on; | |
733 | }; | |
734 | ||
735 | ab8500_ext3_reg: ab8500_ext3 { | |
62ebfe6b LJ |
736 | regulator-min-microvolt = <3400000>; |
737 | regulator-max-microvolt = <3400000>; | |
738 | regulator-boot-on; | |
739 | }; | |
740 | }; | |
741 | ||
4a85c7fa LJ |
742 | ab8500-regulators { |
743 | compatible = "stericsson,ab8500-regulator"; | |
75f0999a | 744 | vin-supply = <&ab8500_ext3_reg>; |
4a85c7fa LJ |
745 | |
746 | // supplies to the display/camera | |
747 | ab8500_ldo_aux1_reg: ab8500_ldo_aux1 { | |
4a85c7fa LJ |
748 | regulator-min-microvolt = <2500000>; |
749 | regulator-max-microvolt = <2900000>; | |
750 | regulator-boot-on; | |
751 | /* BUG: If turned off MMC will be affected. */ | |
752 | regulator-always-on; | |
753 | }; | |
754 | ||
755 | // supplies to the on-board eMMC | |
756 | ab8500_ldo_aux2_reg: ab8500_ldo_aux2 { | |
4a85c7fa LJ |
757 | regulator-min-microvolt = <1100000>; |
758 | regulator-max-microvolt = <3300000>; | |
759 | }; | |
760 | ||
761 | // supply for VAUX3; SDcard slots | |
762 | ab8500_ldo_aux3_reg: ab8500_ldo_aux3 { | |
4a85c7fa LJ |
763 | regulator-min-microvolt = <1100000>; |
764 | regulator-max-microvolt = <3300000>; | |
765 | }; | |
766 | ||
767 | // supply for v-intcore12; VINTCORE12 LDO | |
99b38eef | 768 | ab8500_ldo_intcore_reg: ab8500_ldo_intcore { |
4a85c7fa LJ |
769 | }; |
770 | ||
771 | // supply for tvout; gpadc; TVOUT LDO | |
772 | ab8500_ldo_tvout_reg: ab8500_ldo_tvout { | |
4a85c7fa LJ |
773 | }; |
774 | ||
775 | // supply for ab8500-usb; USB LDO | |
776 | ab8500_ldo_usb_reg: ab8500_ldo_usb { | |
4a85c7fa LJ |
777 | }; |
778 | ||
779 | // supply for ab8500-vaudio; VAUDIO LDO | |
780 | ab8500_ldo_audio_reg: ab8500_ldo_audio { | |
4a85c7fa LJ |
781 | }; |
782 | ||
4aa44874 | 783 | // supply for v-anamic1 VAMIC1 LDO |
4a85c7fa | 784 | ab8500_ldo_anamic1_reg: ab8500_ldo_anamic1 { |
4a85c7fa LJ |
785 | }; |
786 | ||
787 | // supply for v-amic2; VAMIC2 LDO; reuse constants for AMIC1 | |
5510ed9f | 788 | ab8500_ldo_anamic2_reg: ab8500_ldo_anamic2 { |
4a85c7fa LJ |
789 | }; |
790 | ||
791 | // supply for v-dmic; VDMIC LDO | |
792 | ab8500_ldo_dmic_reg: ab8500_ldo_dmic { | |
4a85c7fa LJ |
793 | }; |
794 | ||
795 | // supply for U8500 CSI/DSI; VANA LDO | |
796 | ab8500_ldo_ana_reg: ab8500_ldo_ana { | |
4a85c7fa LJ |
797 | }; |
798 | }; | |
7e0ce270 LJ |
799 | }; |
800 | }; | |
801 | ||
802 | i2c@80004000 { | |
d524fa7f | 803 | compatible = "stericsson,db8500-i2c", "st,nomadik-i2c", "arm,primecell"; |
7e0ce270 | 804 | reg = <0x80004000 0x1000>; |
0bfe5167 | 805 | interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>; |
35b33d23 | 806 | |
7e0ce270 LJ |
807 | #address-cells = <1>; |
808 | #size-cells = <0>; | |
d524fa7f LJ |
809 | v-i2c-supply = <&db8500_vape_reg>; |
810 | ||
811 | clock-frequency = <400000>; | |
afd653e9 LJ |
812 | clocks = <&prcc_kclk 3 3>, <&prcc_pclk 3 3>; |
813 | clock-names = "i2cclk", "apb_pclk"; | |
29417fe8 | 814 | power-domains = <&pm_domains DOMAIN_VAPE>; |
7e0ce270 LJ |
815 | }; |
816 | ||
817 | i2c@80122000 { | |
d524fa7f | 818 | compatible = "stericsson,db8500-i2c", "st,nomadik-i2c", "arm,primecell"; |
7e0ce270 | 819 | reg = <0x80122000 0x1000>; |
0bfe5167 | 820 | interrupts = <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>; |
35b33d23 | 821 | |
7e0ce270 LJ |
822 | #address-cells = <1>; |
823 | #size-cells = <0>; | |
d524fa7f LJ |
824 | v-i2c-supply = <&db8500_vape_reg>; |
825 | ||
826 | clock-frequency = <400000>; | |
afd653e9 LJ |
827 | |
828 | clocks = <&prcc_kclk 1 2>, <&prcc_pclk 1 2>; | |
829 | clock-names = "i2cclk", "apb_pclk"; | |
29417fe8 | 830 | power-domains = <&pm_domains DOMAIN_VAPE>; |
7e0ce270 LJ |
831 | }; |
832 | ||
833 | i2c@80128000 { | |
d524fa7f | 834 | compatible = "stericsson,db8500-i2c", "st,nomadik-i2c", "arm,primecell"; |
7e0ce270 | 835 | reg = <0x80128000 0x1000>; |
0bfe5167 | 836 | interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>; |
35b33d23 | 837 | |
7e0ce270 LJ |
838 | #address-cells = <1>; |
839 | #size-cells = <0>; | |
d524fa7f LJ |
840 | v-i2c-supply = <&db8500_vape_reg>; |
841 | ||
842 | clock-frequency = <400000>; | |
afd653e9 LJ |
843 | |
844 | clocks = <&prcc_kclk 1 6>, <&prcc_pclk 1 6>; | |
845 | clock-names = "i2cclk", "apb_pclk"; | |
29417fe8 | 846 | power-domains = <&pm_domains DOMAIN_VAPE>; |
7e0ce270 LJ |
847 | }; |
848 | ||
849 | i2c@80110000 { | |
d524fa7f | 850 | compatible = "stericsson,db8500-i2c", "st,nomadik-i2c", "arm,primecell"; |
7e0ce270 | 851 | reg = <0x80110000 0x1000>; |
0bfe5167 | 852 | interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>; |
35b33d23 | 853 | |
7e0ce270 LJ |
854 | #address-cells = <1>; |
855 | #size-cells = <0>; | |
d524fa7f LJ |
856 | v-i2c-supply = <&db8500_vape_reg>; |
857 | ||
858 | clock-frequency = <400000>; | |
afd653e9 LJ |
859 | |
860 | clocks = <&prcc_kclk 2 0>, <&prcc_pclk 2 0>; | |
861 | clock-names = "i2cclk", "apb_pclk"; | |
29417fe8 | 862 | power-domains = <&pm_domains DOMAIN_VAPE>; |
7e0ce270 LJ |
863 | }; |
864 | ||
865 | i2c@8012a000 { | |
d524fa7f | 866 | compatible = "stericsson,db8500-i2c", "st,nomadik-i2c", "arm,primecell"; |
7e0ce270 | 867 | reg = <0x8012a000 0x1000>; |
0bfe5167 | 868 | interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>; |
35b33d23 | 869 | |
7e0ce270 LJ |
870 | #address-cells = <1>; |
871 | #size-cells = <0>; | |
d524fa7f LJ |
872 | v-i2c-supply = <&db8500_vape_reg>; |
873 | ||
874 | clock-frequency = <400000>; | |
afd653e9 | 875 | |
72b3e249 | 876 | clocks = <&prcc_kclk 1 9>, <&prcc_pclk 1 10>; |
afd653e9 | 877 | clock-names = "i2cclk", "apb_pclk"; |
29417fe8 | 878 | power-domains = <&pm_domains DOMAIN_VAPE>; |
7e0ce270 LJ |
879 | }; |
880 | ||
881 | ssp@80002000 { | |
882 | compatible = "arm,pl022", "arm,primecell"; | |
c164fa62 | 883 | reg = <0x80002000 0x1000>; |
0bfe5167 | 884 | interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>; |
7e0ce270 LJ |
885 | #address-cells = <1>; |
886 | #size-cells = <0>; | |
6e1484c2 | 887 | clocks = <&prcc_kclk 3 1>, <&prcc_pclk 3 1>; |
80fbe30f | 888 | clock-names = "SSPCLK", "apb_pclk"; |
6e1484c2 LW |
889 | dmas = <&dma 8 0 0x2>, /* Logical - DevToMem */ |
890 | <&dma 8 0 0x0>; /* Logical - MemToDev */ | |
891 | dma-names = "rx", "tx"; | |
770e2f6b | 892 | power-domains = <&pm_domains DOMAIN_VAPE>; |
6e1484c2 LW |
893 | }; |
894 | ||
895 | ssp@80003000 { | |
896 | compatible = "arm,pl022", "arm,primecell"; | |
897 | reg = <0x80003000 0x1000>; | |
0bfe5167 | 898 | interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>; |
6e1484c2 LW |
899 | #address-cells = <1>; |
900 | #size-cells = <0>; | |
901 | clocks = <&prcc_kclk 3 2>, <&prcc_pclk 3 2>; | |
80fbe30f | 902 | clock-names = "SSPCLK", "apb_pclk"; |
6e1484c2 LW |
903 | dmas = <&dma 9 0 0x2>, /* Logical - DevToMem */ |
904 | <&dma 9 0 0x0>; /* Logical - MemToDev */ | |
905 | dma-names = "rx", "tx"; | |
770e2f6b | 906 | power-domains = <&pm_domains DOMAIN_VAPE>; |
6e1484c2 LW |
907 | }; |
908 | ||
909 | spi@8011a000 { | |
910 | compatible = "arm,pl022", "arm,primecell"; | |
911 | reg = <0x8011a000 0x1000>; | |
0bfe5167 | 912 | interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>; |
6e1484c2 LW |
913 | #address-cells = <1>; |
914 | #size-cells = <0>; | |
915 | /* Same clock wired to kernel and pclk */ | |
916 | clocks = <&prcc_pclk 2 8>, <&prcc_pclk 2 8>; | |
80fbe30f | 917 | clock-names = "SSPCLK", "apb_pclk"; |
6e1484c2 LW |
918 | dmas = <&dma 0 0 0x2>, /* Logical - DevToMem */ |
919 | <&dma 0 0 0x0>; /* Logical - MemToDev */ | |
920 | dma-names = "rx", "tx"; | |
770e2f6b | 921 | power-domains = <&pm_domains DOMAIN_VAPE>; |
6e1484c2 LW |
922 | }; |
923 | ||
924 | spi@80112000 { | |
925 | compatible = "arm,pl022", "arm,primecell"; | |
926 | reg = <0x80112000 0x1000>; | |
0bfe5167 | 927 | interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>; |
6e1484c2 LW |
928 | #address-cells = <1>; |
929 | #size-cells = <0>; | |
930 | /* Same clock wired to kernel and pclk */ | |
931 | clocks = <&prcc_pclk 2 2>, <&prcc_pclk 2 2>; | |
80fbe30f | 932 | clock-names = "SSPCLK", "apb_pclk"; |
6e1484c2 LW |
933 | dmas = <&dma 35 0 0x2>, /* Logical - DevToMem */ |
934 | <&dma 35 0 0x0>; /* Logical - MemToDev */ | |
935 | dma-names = "rx", "tx"; | |
770e2f6b | 936 | power-domains = <&pm_domains DOMAIN_VAPE>; |
6e1484c2 LW |
937 | }; |
938 | ||
939 | spi@80111000 { | |
940 | compatible = "arm,pl022", "arm,primecell"; | |
941 | reg = <0x80111000 0x1000>; | |
0bfe5167 | 942 | interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>; |
6e1484c2 LW |
943 | #address-cells = <1>; |
944 | #size-cells = <0>; | |
945 | /* Same clock wired to kernel and pclk */ | |
946 | clocks = <&prcc_pclk 2 1>, <&prcc_pclk 2 1>; | |
80fbe30f | 947 | clock-names = "SSPCLK", "apb_pclk"; |
6e1484c2 LW |
948 | dmas = <&dma 33 0 0x2>, /* Logical - DevToMem */ |
949 | <&dma 33 0 0x0>; /* Logical - MemToDev */ | |
950 | dma-names = "rx", "tx"; | |
770e2f6b | 951 | power-domains = <&pm_domains DOMAIN_VAPE>; |
6e1484c2 LW |
952 | }; |
953 | ||
954 | spi@80129000 { | |
955 | compatible = "arm,pl022", "arm,primecell"; | |
956 | reg = <0x80129000 0x1000>; | |
0bfe5167 | 957 | interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>; |
6e1484c2 LW |
958 | #address-cells = <1>; |
959 | #size-cells = <0>; | |
960 | /* Same clock wired to kernel and pclk */ | |
961 | clocks = <&prcc_pclk 1 7>, <&prcc_pclk 1 7>; | |
80fbe30f | 962 | clock-names = "SSPCLK", "apb_pclk"; |
6e1484c2 LW |
963 | dmas = <&dma 40 0 0x2>, /* Logical - DevToMem */ |
964 | <&dma 40 0 0x0>; /* Logical - MemToDev */ | |
965 | dma-names = "rx", "tx"; | |
770e2f6b | 966 | power-domains = <&pm_domains DOMAIN_VAPE>; |
7e0ce270 LJ |
967 | }; |
968 | ||
109978de | 969 | ux500_serial0: uart@80120000 { |
7e0ce270 LJ |
970 | compatible = "arm,pl011", "arm,primecell"; |
971 | reg = <0x80120000 0x1000>; | |
0bfe5167 | 972 | interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>; |
fbff01cc LJ |
973 | |
974 | dmas = <&dma 13 0 0x2>, /* Logical - DevToMem */ | |
975 | <&dma 13 0 0x0>; /* Logical - MemToDev */ | |
976 | dma-names = "rx", "tx"; | |
977 | ||
5a323fb4 LJ |
978 | clocks = <&prcc_kclk 1 0>, <&prcc_pclk 1 0>; |
979 | clock-names = "uart", "apb_pclk"; | |
980 | ||
7e0ce270 LJ |
981 | status = "disabled"; |
982 | }; | |
fbff01cc | 983 | |
109978de | 984 | ux500_serial1: uart@80121000 { |
7e0ce270 LJ |
985 | compatible = "arm,pl011", "arm,primecell"; |
986 | reg = <0x80121000 0x1000>; | |
0bfe5167 | 987 | interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>; |
fbff01cc LJ |
988 | |
989 | dmas = <&dma 12 0 0x2>, /* Logical - DevToMem */ | |
990 | <&dma 12 0 0x0>; /* Logical - MemToDev */ | |
991 | dma-names = "rx", "tx"; | |
992 | ||
5a323fb4 LJ |
993 | clocks = <&prcc_kclk 1 1>, <&prcc_pclk 1 1>; |
994 | clock-names = "uart", "apb_pclk"; | |
995 | ||
7e0ce270 LJ |
996 | status = "disabled"; |
997 | }; | |
fbff01cc | 998 | |
109978de | 999 | ux500_serial2: uart@80007000 { |
7e0ce270 LJ |
1000 | compatible = "arm,pl011", "arm,primecell"; |
1001 | reg = <0x80007000 0x1000>; | |
0bfe5167 | 1002 | interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>; |
fbff01cc LJ |
1003 | |
1004 | dmas = <&dma 11 0 0x2>, /* Logical - DevToMem */ | |
1005 | <&dma 11 0 0x0>; /* Logical - MemToDev */ | |
1006 | dma-names = "rx", "tx"; | |
1007 | ||
5a323fb4 LJ |
1008 | clocks = <&prcc_kclk 3 6>, <&prcc_pclk 3 6>; |
1009 | clock-names = "uart", "apb_pclk"; | |
1010 | ||
7e0ce270 LJ |
1011 | status = "disabled"; |
1012 | }; | |
1013 | ||
81bf8c2e | 1014 | sdi0_per1@80126000 { |
7e0ce270 LJ |
1015 | compatible = "arm,pl18x", "arm,primecell"; |
1016 | reg = <0x80126000 0x1000>; | |
0bfe5167 | 1017 | interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>; |
498315b9 LJ |
1018 | |
1019 | dmas = <&dma 29 0 0x2>, /* Logical - DevToMem */ | |
1020 | <&dma 29 0 0x0>; /* Logical - MemToDev */ | |
1021 | dma-names = "rx", "tx"; | |
1022 | ||
604be898 LJ |
1023 | clocks = <&prcc_kclk 1 5>, <&prcc_pclk 1 5>; |
1024 | clock-names = "sdi", "apb_pclk"; | |
067addec | 1025 | power-domains = <&pm_domains DOMAIN_VAPE>; |
604be898 | 1026 | |
7e0ce270 LJ |
1027 | status = "disabled"; |
1028 | }; | |
76ff4e43 | 1029 | |
81bf8c2e | 1030 | sdi1_per2@80118000 { |
7e0ce270 LJ |
1031 | compatible = "arm,pl18x", "arm,primecell"; |
1032 | reg = <0x80118000 0x1000>; | |
0bfe5167 | 1033 | interrupts = <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>; |
498315b9 LJ |
1034 | |
1035 | dmas = <&dma 32 0 0x2>, /* Logical - DevToMem */ | |
1036 | <&dma 32 0 0x0>; /* Logical - MemToDev */ | |
1037 | dma-names = "rx", "tx"; | |
1038 | ||
604be898 LJ |
1039 | clocks = <&prcc_kclk 2 4>, <&prcc_pclk 2 6>; |
1040 | clock-names = "sdi", "apb_pclk"; | |
067addec | 1041 | power-domains = <&pm_domains DOMAIN_VAPE>; |
604be898 | 1042 | |
7e0ce270 LJ |
1043 | status = "disabled"; |
1044 | }; | |
76ff4e43 | 1045 | |
81bf8c2e | 1046 | sdi2_per3@80005000 { |
7e0ce270 LJ |
1047 | compatible = "arm,pl18x", "arm,primecell"; |
1048 | reg = <0x80005000 0x1000>; | |
0bfe5167 | 1049 | interrupts = <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>; |
498315b9 LJ |
1050 | |
1051 | dmas = <&dma 28 0 0x2>, /* Logical - DevToMem */ | |
1052 | <&dma 28 0 0x0>; /* Logical - MemToDev */ | |
1053 | dma-names = "rx", "tx"; | |
1054 | ||
604be898 LJ |
1055 | clocks = <&prcc_kclk 3 4>, <&prcc_pclk 3 4>; |
1056 | clock-names = "sdi", "apb_pclk"; | |
067addec | 1057 | power-domains = <&pm_domains DOMAIN_VAPE>; |
604be898 | 1058 | |
7e0ce270 LJ |
1059 | status = "disabled"; |
1060 | }; | |
76ff4e43 | 1061 | |
81bf8c2e | 1062 | sdi3_per2@80119000 { |
7e0ce270 LJ |
1063 | compatible = "arm,pl18x", "arm,primecell"; |
1064 | reg = <0x80119000 0x1000>; | |
0bfe5167 | 1065 | interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>; |
604be898 | 1066 | |
14cdf8cb LW |
1067 | dmas = <&dma 41 0 0x2>, /* Logical - DevToMem */ |
1068 | <&dma 41 0 0x0>; /* Logical - MemToDev */ | |
1069 | dma-names = "rx", "tx"; | |
1070 | ||
604be898 LJ |
1071 | clocks = <&prcc_kclk 2 5>, <&prcc_pclk 2 7>; |
1072 | clock-names = "sdi", "apb_pclk"; | |
067addec | 1073 | power-domains = <&pm_domains DOMAIN_VAPE>; |
604be898 | 1074 | |
7e0ce270 LJ |
1075 | status = "disabled"; |
1076 | }; | |
76ff4e43 | 1077 | |
81bf8c2e | 1078 | sdi4_per2@80114000 { |
7e0ce270 LJ |
1079 | compatible = "arm,pl18x", "arm,primecell"; |
1080 | reg = <0x80114000 0x1000>; | |
0bfe5167 | 1081 | interrupts = <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>; |
498315b9 LJ |
1082 | |
1083 | dmas = <&dma 42 0 0x2>, /* Logical - DevToMem */ | |
1084 | <&dma 42 0 0x0>; /* Logical - MemToDev */ | |
1085 | dma-names = "rx", "tx"; | |
1086 | ||
604be898 LJ |
1087 | clocks = <&prcc_kclk 2 2>, <&prcc_pclk 2 4>; |
1088 | clock-names = "sdi", "apb_pclk"; | |
067addec | 1089 | power-domains = <&pm_domains DOMAIN_VAPE>; |
604be898 | 1090 | |
7e0ce270 LJ |
1091 | status = "disabled"; |
1092 | }; | |
76ff4e43 | 1093 | |
81bf8c2e | 1094 | sdi5_per3@80008000 { |
7e0ce270 | 1095 | compatible = "arm,pl18x", "arm,primecell"; |
76ff4e43 | 1096 | reg = <0x80008000 0x1000>; |
0bfe5167 | 1097 | interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>; |
604be898 | 1098 | |
14cdf8cb LW |
1099 | dmas = <&dma 43 0 0x2>, /* Logical - DevToMem */ |
1100 | <&dma 43 0 0x0>; /* Logical - MemToDev */ | |
1101 | dma-names = "rx", "tx"; | |
1102 | ||
604be898 LJ |
1103 | clocks = <&prcc_kclk 3 7>, <&prcc_pclk 3 7>; |
1104 | clock-names = "sdi", "apb_pclk"; | |
067addec | 1105 | power-domains = <&pm_domains DOMAIN_VAPE>; |
604be898 | 1106 | |
7e0ce270 LJ |
1107 | status = "disabled"; |
1108 | }; | |
bf76e062 | 1109 | |
9aea151f LW |
1110 | sound { |
1111 | compatible = "stericsson,snd-soc-mop500"; | |
1112 | stericsson,cpu-dai = <&msp1 &msp3>; | |
1113 | stericsson,audio-codec = <&codec>; | |
1114 | clocks = <&prcmu_clk PRCMU_SYSCLK>, <&ab8500_clock AB8500_SYSCLK_ULP>, <&ab8500_clock AB8500_SYSCLK_INT>; | |
1115 | clock-names = "sysclk", "ulpclk", "intclk"; | |
1116 | }; | |
1117 | ||
fe164529 LJ |
1118 | msp0: msp@80123000 { |
1119 | compatible = "stericsson,ux500-msp-i2s"; | |
1120 | reg = <0x80123000 0x1000>; | |
0bfe5167 | 1121 | interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>; |
fe164529 | 1122 | v-ape-supply = <&db8500_vape_reg>; |
133e6027 | 1123 | |
618111ca LJ |
1124 | dmas = <&dma 31 0 0x12>, /* Logical - DevToMem - HighPrio */ |
1125 | <&dma 31 0 0x10>; /* Logical - MemToDev - HighPrio */ | |
1126 | dma-names = "rx", "tx"; | |
1127 | ||
133e6027 LJ |
1128 | clocks = <&prcc_kclk 1 3>, <&prcc_pclk 1 3>; |
1129 | clock-names = "msp", "apb_pclk"; | |
1130 | ||
fe164529 LJ |
1131 | status = "disabled"; |
1132 | }; | |
1133 | ||
1134 | msp1: msp@80124000 { | |
1135 | compatible = "stericsson,ux500-msp-i2s"; | |
1136 | reg = <0x80124000 0x1000>; | |
0bfe5167 | 1137 | interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>; |
fe164529 | 1138 | v-ape-supply = <&db8500_vape_reg>; |
133e6027 | 1139 | |
14cdf8cb | 1140 | /* This DMA channel only exist on DB8500 v1 */ |
618111ca LJ |
1141 | dmas = <&dma 30 0 0x10>; /* Logical - MemToDev - HighPrio */ |
1142 | dma-names = "tx"; | |
1143 | ||
133e6027 LJ |
1144 | clocks = <&prcc_kclk 1 4>, <&prcc_pclk 1 4>; |
1145 | clock-names = "msp", "apb_pclk"; | |
1146 | ||
fe164529 LJ |
1147 | status = "disabled"; |
1148 | }; | |
1149 | ||
1150 | // HDMI sound | |
1151 | msp2: msp@80117000 { | |
1152 | compatible = "stericsson,ux500-msp-i2s"; | |
1153 | reg = <0x80117000 0x1000>; | |
0bfe5167 | 1154 | interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>; |
fe164529 | 1155 | v-ape-supply = <&db8500_vape_reg>; |
133e6027 | 1156 | |
618111ca LJ |
1157 | dmas = <&dma 14 0 0x12>, /* Logical - DevToMem - HighPrio */ |
1158 | <&dma 14 1 0x19>; /* Physical Chan 1 - MemToDev | |
1159 | HighPrio - Fixed */ | |
1160 | dma-names = "rx", "tx"; | |
1161 | ||
133e6027 LJ |
1162 | clocks = <&prcc_kclk 2 3>, <&prcc_pclk 2 5>; |
1163 | clock-names = "msp", "apb_pclk"; | |
1164 | ||
fe164529 LJ |
1165 | status = "disabled"; |
1166 | }; | |
1167 | ||
1168 | msp3: msp@80125000 { | |
1169 | compatible = "stericsson,ux500-msp-i2s"; | |
1170 | reg = <0x80125000 0x1000>; | |
0bfe5167 | 1171 | interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>; |
fe164529 | 1172 | v-ape-supply = <&db8500_vape_reg>; |
133e6027 | 1173 | |
14cdf8cb | 1174 | /* This DMA channel only exist on DB8500 v2 */ |
618111ca LJ |
1175 | dmas = <&dma 30 0 0x12>; /* Logical - DevToMem - HighPrio */ |
1176 | dma-names = "rx"; | |
1177 | ||
133e6027 LJ |
1178 | clocks = <&prcc_kclk 1 10>, <&prcc_pclk 1 11>; |
1179 | clock-names = "msp", "apb_pclk"; | |
1180 | ||
fe164529 LJ |
1181 | status = "disabled"; |
1182 | }; | |
1183 | ||
bf76e062 LJ |
1184 | external-bus@50000000 { |
1185 | compatible = "simple-bus"; | |
1186 | reg = <0x50000000 0x4000000>; | |
1187 | #address-cells = <1>; | |
1188 | #size-cells = <1>; | |
1189 | ranges = <0 0x50000000 0x4000000>; | |
1190 | status = "disabled"; | |
1191 | }; | |
dc1956b5 | 1192 | |
6e9a88a0 LW |
1193 | mcde@a0350000 { |
1194 | compatible = "stericsson,mcde"; | |
1195 | reg = <0xa0350000 0x1000>, /* MCDE */ | |
1196 | <0xa0351000 0x1000>, /* DSI link 1 */ | |
1197 | <0xa0352000 0x1000>, /* DSI link 2 */ | |
1198 | <0xa0353000 0x1000>; /* DSI link 3 */ | |
0bfe5167 | 1199 | interrupts = <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>; |
6e9a88a0 LW |
1200 | clocks = <&prcmu_clk PRCMU_MCDECLK>, /* Main MCDE clock */ |
1201 | <&prcmu_clk PRCMU_LCDCLK>, /* LCD clock */ | |
1202 | <&prcmu_clk PRCMU_PLLDSI>, /* HDMI clock */ | |
1203 | <&prcmu_clk PRCMU_DSI0CLK>, /* DSI 0 */ | |
1204 | <&prcmu_clk PRCMU_DSI1CLK>, /* DSI 1 */ | |
1205 | <&prcmu_clk PRCMU_DSI0ESCCLK>, /* TVout clock 0 */ | |
1206 | <&prcmu_clk PRCMU_DSI1ESCCLK>, /* TVout clock 1 */ | |
1207 | <&prcmu_clk PRCMU_DSI2ESCCLK>; /* TVout clock 2 */ | |
1208 | }; | |
1209 | ||
fe2e9f92 LJ |
1210 | cryp@a03cb000 { |
1211 | compatible = "stericsson,ux500-cryp"; | |
1212 | reg = <0xa03cb000 0x1000>; | |
0bfe5167 | 1213 | interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>; |
fe2e9f92 LJ |
1214 | |
1215 | v-ape-supply = <&db8500_vape_reg>; | |
d2f898ce | 1216 | clocks = <&prcc_pclk 6 1>; |
fe2e9f92 | 1217 | }; |
61122cf2 LJ |
1218 | |
1219 | hash@a03c2000 { | |
1220 | compatible = "stericsson,ux500-hash"; | |
1221 | reg = <0xa03c2000 0x1000>; | |
1222 | ||
1223 | v-ape-supply = <&db8500_vape_reg>; | |
024cfe88 | 1224 | clocks = <&prcc_pclk 6 2>; |
61122cf2 | 1225 | }; |
5d0769f0 AB |
1226 | }; |
1227 | }; |