Commit | Line | Data |
---|---|---|
66314223 DN |
1 | /* |
2 | * Copyright (C) 2012 Altera <www.altera.com> | |
3 | * | |
4 | * This program is free software; you can redistribute it and/or modify | |
5 | * it under the terms of the GNU General Public License as published by | |
6 | * the Free Software Foundation; either version 2 of the License, or | |
7 | * (at your option) any later version. | |
8 | * | |
9 | * This program is distributed in the hope that it will be useful, | |
10 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
11 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
12 | * GNU General Public License for more details. | |
13 | * | |
14 | * You should have received a copy of the GNU General Public License | |
15 | * along with this program. If not, see <http://www.gnu.org/licenses/>. | |
16 | */ | |
17 | ||
7da9b436 | 18 | #include "skeleton.dtsi" |
16fb4f8b | 19 | #include <dt-bindings/reset/altr,rst-mgr.h> |
66314223 DN |
20 | |
21 | / { | |
22 | #address-cells = <1>; | |
23 | #size-cells = <1>; | |
24 | ||
25 | aliases { | |
26 | ethernet0 = &gmac0; | |
3d954cf1 | 27 | ethernet1 = &gmac1; |
66314223 DN |
28 | serial0 = &uart0; |
29 | serial1 = &uart1; | |
c2ad2844 DN |
30 | timer0 = &timer0; |
31 | timer1 = &timer1; | |
32 | timer2 = &timer2; | |
33 | timer3 = &timer3; | |
66314223 DN |
34 | }; |
35 | ||
36 | cpus { | |
37 | #address-cells = <1>; | |
38 | #size-cells = <0>; | |
ebbce1bb | 39 | enable-method = "altr,socfpga-smp"; |
66314223 DN |
40 | |
41 | cpu@0 { | |
42 | compatible = "arm,cortex-a9"; | |
43 | device_type = "cpu"; | |
44 | reg = <0>; | |
45 | next-level-cache = <&L2>; | |
46 | }; | |
47 | cpu@1 { | |
48 | compatible = "arm,cortex-a9"; | |
49 | device_type = "cpu"; | |
50 | reg = <1>; | |
51 | next-level-cache = <&L2>; | |
52 | }; | |
53 | }; | |
54 | ||
55 | intc: intc@fffed000 { | |
56 | compatible = "arm,cortex-a9-gic"; | |
57 | #interrupt-cells = <3>; | |
58 | interrupt-controller; | |
59 | reg = <0xfffed000 0x1000>, | |
60 | <0xfffec100 0x100>; | |
61 | }; | |
62 | ||
63 | soc { | |
64 | #address-cells = <1>; | |
65 | #size-cells = <1>; | |
66 | compatible = "simple-bus"; | |
67 | device_type = "soc"; | |
68 | interrupt-parent = <&intc>; | |
69 | ranges; | |
70 | ||
71 | amba { | |
72 | compatible = "arm,amba-bus"; | |
73 | #address-cells = <1>; | |
74 | #size-cells = <1>; | |
75 | ranges; | |
76 | ||
77 | pdma: pdma@ffe01000 { | |
78 | compatible = "arm,pl330", "arm,primecell"; | |
79 | reg = <0xffe01000 0x1000>; | |
18d56199 ST |
80 | interrupts = <0 104 4>, |
81 | <0 105 4>, | |
82 | <0 106 4>, | |
83 | <0 107 4>, | |
84 | <0 108 4>, | |
85 | <0 109 4>, | |
86 | <0 110 4>, | |
87 | <0 111 4>; | |
0d8abbfd PV |
88 | #dma-cells = <1>; |
89 | #dma-channels = <8>; | |
90 | #dma-requests = <32>; | |
672ef909 ST |
91 | clocks = <&l4_main_clk>; |
92 | clock-names = "apb_pclk"; | |
66314223 DN |
93 | }; |
94 | }; | |
95 | ||
36fe3f54 ST |
96 | can0: can@ffc00000 { |
97 | compatible = "bosch,d_can"; | |
98 | reg = <0xffc00000 0x1000>; | |
99 | interrupts = <0 131 4>, <0 132 4>, <0 133 4>, <0 134 4>; | |
100 | clocks = <&can0_clk>; | |
101 | status = "disabled"; | |
102 | }; | |
103 | ||
104 | can1: can@ffc01000 { | |
105 | compatible = "bosch,d_can"; | |
106 | reg = <0xffc01000 0x1000>; | |
107 | interrupts = <0 135 4>, <0 136 4>, <0 137 4>, <0 138 4>; | |
108 | clocks = <&can1_clk>; | |
109 | status = "disabled"; | |
110 | }; | |
111 | ||
042000b0 DN |
112 | clkmgr@ffd04000 { |
113 | compatible = "altr,clk-mgr"; | |
114 | reg = <0xffd04000 0x1000>; | |
115 | ||
116 | clocks { | |
117 | #address-cells = <1>; | |
118 | #size-cells = <0>; | |
119 | ||
f1ce1a99 DN |
120 | osc1: osc1 { |
121 | #clock-cells = <0>; | |
122 | compatible = "fixed-clock"; | |
123 | }; | |
124 | ||
125 | osc2: osc2 { | |
042000b0 DN |
126 | #clock-cells = <0>; |
127 | compatible = "fixed-clock"; | |
128 | }; | |
129 | ||
a92b83af DN |
130 | f2s_periph_ref_clk: f2s_periph_ref_clk { |
131 | #clock-cells = <0>; | |
132 | compatible = "fixed-clock"; | |
f1ce1a99 DN |
133 | }; |
134 | ||
135 | f2s_sdram_ref_clk: f2s_sdram_ref_clk { | |
136 | #clock-cells = <0>; | |
137 | compatible = "fixed-clock"; | |
a92b83af DN |
138 | }; |
139 | ||
042000b0 DN |
140 | main_pll: main_pll { |
141 | #address-cells = <1>; | |
142 | #size-cells = <0>; | |
143 | #clock-cells = <0>; | |
144 | compatible = "altr,socfpga-pll-clock"; | |
f1ce1a99 | 145 | clocks = <&osc1>; |
042000b0 DN |
146 | reg = <0x40>; |
147 | ||
148 | mpuclk: mpuclk { | |
149 | #clock-cells = <0>; | |
150 | compatible = "altr,socfpga-perip-clk"; | |
151 | clocks = <&main_pll>; | |
8cb289ed | 152 | div-reg = <0xe0 0 9>; |
042000b0 DN |
153 | reg = <0x48>; |
154 | }; | |
155 | ||
156 | mainclk: mainclk { | |
157 | #clock-cells = <0>; | |
158 | compatible = "altr,socfpga-perip-clk"; | |
159 | clocks = <&main_pll>; | |
8cb289ed | 160 | div-reg = <0xe4 0 9>; |
042000b0 DN |
161 | reg = <0x4C>; |
162 | }; | |
163 | ||
164 | dbg_base_clk: dbg_base_clk { | |
165 | #clock-cells = <0>; | |
166 | compatible = "altr,socfpga-perip-clk"; | |
167 | clocks = <&main_pll>; | |
8cb289ed | 168 | div-reg = <0xe8 0 9>; |
042000b0 DN |
169 | reg = <0x50>; |
170 | }; | |
171 | ||
172 | main_qspi_clk: main_qspi_clk { | |
173 | #clock-cells = <0>; | |
174 | compatible = "altr,socfpga-perip-clk"; | |
175 | clocks = <&main_pll>; | |
176 | reg = <0x54>; | |
177 | }; | |
178 | ||
179 | main_nand_sdmmc_clk: main_nand_sdmmc_clk { | |
180 | #clock-cells = <0>; | |
181 | compatible = "altr,socfpga-perip-clk"; | |
182 | clocks = <&main_pll>; | |
183 | reg = <0x58>; | |
184 | }; | |
185 | ||
01ed80b0 | 186 | cfg_h2f_usr0_clk: cfg_h2f_usr0_clk { |
042000b0 DN |
187 | #clock-cells = <0>; |
188 | compatible = "altr,socfpga-perip-clk"; | |
189 | clocks = <&main_pll>; | |
190 | reg = <0x5C>; | |
191 | }; | |
192 | }; | |
193 | ||
194 | periph_pll: periph_pll { | |
195 | #address-cells = <1>; | |
196 | #size-cells = <0>; | |
197 | #clock-cells = <0>; | |
198 | compatible = "altr,socfpga-pll-clock"; | |
f1ce1a99 | 199 | clocks = <&osc1>, <&osc2>, <&f2s_periph_ref_clk>; |
042000b0 DN |
200 | reg = <0x80>; |
201 | ||
202 | emac0_clk: emac0_clk { | |
203 | #clock-cells = <0>; | |
204 | compatible = "altr,socfpga-perip-clk"; | |
205 | clocks = <&periph_pll>; | |
206 | reg = <0x88>; | |
207 | }; | |
208 | ||
209 | emac1_clk: emac1_clk { | |
210 | #clock-cells = <0>; | |
211 | compatible = "altr,socfpga-perip-clk"; | |
212 | clocks = <&periph_pll>; | |
213 | reg = <0x8C>; | |
214 | }; | |
215 | ||
216 | per_qspi_clk: per_qsi_clk { | |
217 | #clock-cells = <0>; | |
218 | compatible = "altr,socfpga-perip-clk"; | |
219 | clocks = <&periph_pll>; | |
220 | reg = <0x90>; | |
221 | }; | |
222 | ||
223 | per_nand_mmc_clk: per_nand_mmc_clk { | |
224 | #clock-cells = <0>; | |
225 | compatible = "altr,socfpga-perip-clk"; | |
226 | clocks = <&periph_pll>; | |
227 | reg = <0x94>; | |
228 | }; | |
229 | ||
230 | per_base_clk: per_base_clk { | |
231 | #clock-cells = <0>; | |
232 | compatible = "altr,socfpga-perip-clk"; | |
233 | clocks = <&periph_pll>; | |
234 | reg = <0x98>; | |
235 | }; | |
236 | ||
01ed80b0 | 237 | h2f_usr1_clk: h2f_usr1_clk { |
042000b0 DN |
238 | #clock-cells = <0>; |
239 | compatible = "altr,socfpga-perip-clk"; | |
240 | clocks = <&periph_pll>; | |
241 | reg = <0x9C>; | |
242 | }; | |
243 | }; | |
244 | ||
245 | sdram_pll: sdram_pll { | |
246 | #address-cells = <1>; | |
247 | #size-cells = <0>; | |
248 | #clock-cells = <0>; | |
249 | compatible = "altr,socfpga-pll-clock"; | |
f1ce1a99 | 250 | clocks = <&osc1>, <&osc2>, <&f2s_sdram_ref_clk>; |
042000b0 DN |
251 | reg = <0xC0>; |
252 | ||
253 | ddr_dqs_clk: ddr_dqs_clk { | |
254 | #clock-cells = <0>; | |
255 | compatible = "altr,socfpga-perip-clk"; | |
256 | clocks = <&sdram_pll>; | |
257 | reg = <0xC8>; | |
258 | }; | |
259 | ||
260 | ddr_2x_dqs_clk: ddr_2x_dqs_clk { | |
261 | #clock-cells = <0>; | |
262 | compatible = "altr,socfpga-perip-clk"; | |
263 | clocks = <&sdram_pll>; | |
264 | reg = <0xCC>; | |
265 | }; | |
266 | ||
267 | ddr_dq_clk: ddr_dq_clk { | |
268 | #clock-cells = <0>; | |
269 | compatible = "altr,socfpga-perip-clk"; | |
270 | clocks = <&sdram_pll>; | |
271 | reg = <0xD0>; | |
272 | }; | |
273 | ||
01ed80b0 | 274 | h2f_usr2_clk: h2f_usr2_clk { |
042000b0 DN |
275 | #clock-cells = <0>; |
276 | compatible = "altr,socfpga-perip-clk"; | |
277 | clocks = <&sdram_pll>; | |
278 | reg = <0xD4>; | |
279 | }; | |
280 | }; | |
a92b83af | 281 | |
7857d560 ST |
282 | mpu_periph_clk: mpu_periph_clk { |
283 | #clock-cells = <0>; | |
a5c6e87a | 284 | compatible = "altr,socfpga-perip-clk"; |
7857d560 ST |
285 | clocks = <&mpuclk>; |
286 | fixed-divider = <4>; | |
a92b83af DN |
287 | }; |
288 | ||
7857d560 ST |
289 | mpu_l2_ram_clk: mpu_l2_ram_clk { |
290 | #clock-cells = <0>; | |
a5c6e87a | 291 | compatible = "altr,socfpga-perip-clk"; |
7857d560 ST |
292 | clocks = <&mpuclk>; |
293 | fixed-divider = <2>; | |
a92b83af DN |
294 | }; |
295 | ||
7857d560 ST |
296 | l4_main_clk: l4_main_clk { |
297 | #clock-cells = <0>; | |
298 | compatible = "altr,socfpga-gate-clk"; | |
299 | clocks = <&mainclk>; | |
300 | clk-gate = <0x60 0>; | |
a92b83af DN |
301 | }; |
302 | ||
7857d560 ST |
303 | l3_main_clk: l3_main_clk { |
304 | #clock-cells = <0>; | |
a5c6e87a | 305 | compatible = "altr,socfpga-perip-clk"; |
7857d560 | 306 | clocks = <&mainclk>; |
a5c6e87a | 307 | fixed-divider = <1>; |
a92b83af DN |
308 | }; |
309 | ||
7857d560 ST |
310 | l3_mp_clk: l3_mp_clk { |
311 | #clock-cells = <0>; | |
312 | compatible = "altr,socfpga-gate-clk"; | |
313 | clocks = <&mainclk>; | |
314 | div-reg = <0x64 0 2>; | |
315 | clk-gate = <0x60 1>; | |
a92b83af DN |
316 | }; |
317 | ||
7857d560 ST |
318 | l3_sp_clk: l3_sp_clk { |
319 | #clock-cells = <0>; | |
320 | compatible = "altr,socfpga-gate-clk"; | |
321 | clocks = <&mainclk>; | |
322 | div-reg = <0x64 2 2>; | |
323 | }; | |
a92b83af | 324 | |
7857d560 ST |
325 | l4_mp_clk: l4_mp_clk { |
326 | #clock-cells = <0>; | |
327 | compatible = "altr,socfpga-gate-clk"; | |
328 | clocks = <&mainclk>, <&per_base_clk>; | |
329 | div-reg = <0x64 4 3>; | |
330 | clk-gate = <0x60 2>; | |
a92b83af DN |
331 | }; |
332 | ||
7857d560 ST |
333 | l4_sp_clk: l4_sp_clk { |
334 | #clock-cells = <0>; | |
335 | compatible = "altr,socfpga-gate-clk"; | |
336 | clocks = <&mainclk>, <&per_base_clk>; | |
337 | div-reg = <0x64 7 3>; | |
338 | clk-gate = <0x60 3>; | |
a92b83af DN |
339 | }; |
340 | ||
7857d560 ST |
341 | dbg_at_clk: dbg_at_clk { |
342 | #clock-cells = <0>; | |
343 | compatible = "altr,socfpga-gate-clk"; | |
344 | clocks = <&dbg_base_clk>; | |
345 | div-reg = <0x68 0 2>; | |
346 | clk-gate = <0x60 4>; | |
a92b83af DN |
347 | }; |
348 | ||
7857d560 ST |
349 | dbg_clk: dbg_clk { |
350 | #clock-cells = <0>; | |
351 | compatible = "altr,socfpga-gate-clk"; | |
352 | clocks = <&dbg_base_clk>; | |
353 | div-reg = <0x68 2 2>; | |
354 | clk-gate = <0x60 5>; | |
a92b83af DN |
355 | }; |
356 | ||
7857d560 ST |
357 | dbg_trace_clk: dbg_trace_clk { |
358 | #clock-cells = <0>; | |
359 | compatible = "altr,socfpga-gate-clk"; | |
360 | clocks = <&dbg_base_clk>; | |
361 | div-reg = <0x6C 0 3>; | |
362 | clk-gate = <0x60 6>; | |
a92b83af DN |
363 | }; |
364 | ||
7857d560 ST |
365 | dbg_timer_clk: dbg_timer_clk { |
366 | #clock-cells = <0>; | |
367 | compatible = "altr,socfpga-gate-clk"; | |
368 | clocks = <&dbg_base_clk>; | |
369 | clk-gate = <0x60 7>; | |
a92b83af DN |
370 | }; |
371 | ||
7857d560 ST |
372 | cfg_clk: cfg_clk { |
373 | #clock-cells = <0>; | |
374 | compatible = "altr,socfpga-gate-clk"; | |
01ed80b0 | 375 | clocks = <&cfg_h2f_usr0_clk>; |
7857d560 | 376 | clk-gate = <0x60 8>; |
a92b83af DN |
377 | }; |
378 | ||
01ed80b0 | 379 | h2f_user0_clk: h2f_user0_clk { |
7857d560 ST |
380 | #clock-cells = <0>; |
381 | compatible = "altr,socfpga-gate-clk"; | |
01ed80b0 | 382 | clocks = <&cfg_h2f_usr0_clk>; |
7857d560 | 383 | clk-gate = <0x60 9>; |
a92b83af DN |
384 | }; |
385 | ||
7857d560 ST |
386 | emac_0_clk: emac_0_clk { |
387 | #clock-cells = <0>; | |
388 | compatible = "altr,socfpga-gate-clk"; | |
389 | clocks = <&emac0_clk>; | |
390 | clk-gate = <0xa0 0>; | |
a92b83af DN |
391 | }; |
392 | ||
7857d560 ST |
393 | emac_1_clk: emac_1_clk { |
394 | #clock-cells = <0>; | |
395 | compatible = "altr,socfpga-gate-clk"; | |
396 | clocks = <&emac1_clk>; | |
397 | clk-gate = <0xa0 1>; | |
a92b83af DN |
398 | }; |
399 | ||
7857d560 ST |
400 | usb_mp_clk: usb_mp_clk { |
401 | #clock-cells = <0>; | |
402 | compatible = "altr,socfpga-gate-clk"; | |
403 | clocks = <&per_base_clk>; | |
404 | clk-gate = <0xa0 2>; | |
405 | div-reg = <0xa4 0 3>; | |
a92b83af DN |
406 | }; |
407 | ||
7857d560 ST |
408 | spi_m_clk: spi_m_clk { |
409 | #clock-cells = <0>; | |
410 | compatible = "altr,socfpga-gate-clk"; | |
411 | clocks = <&per_base_clk>; | |
412 | clk-gate = <0xa0 3>; | |
413 | div-reg = <0xa4 3 3>; | |
a92b83af DN |
414 | }; |
415 | ||
7857d560 ST |
416 | can0_clk: can0_clk { |
417 | #clock-cells = <0>; | |
418 | compatible = "altr,socfpga-gate-clk"; | |
419 | clocks = <&per_base_clk>; | |
420 | clk-gate = <0xa0 4>; | |
421 | div-reg = <0xa4 6 3>; | |
a92b83af DN |
422 | }; |
423 | ||
7857d560 ST |
424 | can1_clk: can1_clk { |
425 | #clock-cells = <0>; | |
426 | compatible = "altr,socfpga-gate-clk"; | |
427 | clocks = <&per_base_clk>; | |
428 | clk-gate = <0xa0 5>; | |
429 | div-reg = <0xa4 9 3>; | |
a92b83af DN |
430 | }; |
431 | ||
7857d560 ST |
432 | gpio_db_clk: gpio_db_clk { |
433 | #clock-cells = <0>; | |
434 | compatible = "altr,socfpga-gate-clk"; | |
435 | clocks = <&per_base_clk>; | |
436 | clk-gate = <0xa0 6>; | |
437 | div-reg = <0xa8 0 24>; | |
a92b83af DN |
438 | }; |
439 | ||
01ed80b0 | 440 | h2f_user1_clk: h2f_user1_clk { |
7857d560 ST |
441 | #clock-cells = <0>; |
442 | compatible = "altr,socfpga-gate-clk"; | |
01ed80b0 | 443 | clocks = <&h2f_usr1_clk>; |
7857d560 | 444 | clk-gate = <0xa0 7>; |
a92b83af DN |
445 | }; |
446 | ||
7857d560 ST |
447 | sdmmc_clk: sdmmc_clk { |
448 | #clock-cells = <0>; | |
449 | compatible = "altr,socfpga-gate-clk"; | |
450 | clocks = <&f2s_periph_ref_clk>, <&main_nand_sdmmc_clk>, <&per_nand_mmc_clk>; | |
451 | clk-gate = <0xa0 8>; | |
044abbde | 452 | clk-phase = <0 135>; |
a92b83af DN |
453 | }; |
454 | ||
5459f9ab DN |
455 | sdmmc_clk_divided: sdmmc_clk_divided { |
456 | #clock-cells = <0>; | |
457 | compatible = "altr,socfpga-gate-clk"; | |
458 | clocks = <&sdmmc_clk>; | |
459 | clk-gate = <0xa0 8>; | |
460 | fixed-divider = <4>; | |
461 | }; | |
462 | ||
7857d560 ST |
463 | nand_x_clk: nand_x_clk { |
464 | #clock-cells = <0>; | |
465 | compatible = "altr,socfpga-gate-clk"; | |
466 | clocks = <&f2s_periph_ref_clk>, <&main_nand_sdmmc_clk>, <&per_nand_mmc_clk>; | |
467 | clk-gate = <0xa0 9>; | |
a92b83af DN |
468 | }; |
469 | ||
7857d560 ST |
470 | nand_clk: nand_clk { |
471 | #clock-cells = <0>; | |
472 | compatible = "altr,socfpga-gate-clk"; | |
473 | clocks = <&f2s_periph_ref_clk>, <&main_nand_sdmmc_clk>, <&per_nand_mmc_clk>; | |
474 | clk-gate = <0xa0 10>; | |
475 | fixed-divider = <4>; | |
a92b83af DN |
476 | }; |
477 | ||
7857d560 ST |
478 | qspi_clk: qspi_clk { |
479 | #clock-cells = <0>; | |
480 | compatible = "altr,socfpga-gate-clk"; | |
481 | clocks = <&f2s_periph_ref_clk>, <&main_qspi_clk>, <&per_qspi_clk>; | |
482 | clk-gate = <0xa0 11>; | |
a92b83af | 483 | }; |
042000b0 DN |
484 | }; |
485 | }; | |
486 | ||
3d954cf1 | 487 | gmac0: ethernet@ff700000 { |
66314223 | 488 | compatible = "altr,socfpga-stmmac", "snps,dwmac-3.70a", "snps,dwmac"; |
2755e187 | 489 | altr,sysmgr-syscon = <&sysmgr 0x60 0>; |
66314223 DN |
490 | reg = <0xff700000 0x2000>; |
491 | interrupts = <0 115 4>; | |
492 | interrupt-names = "macirq"; | |
493 | mac-address = [00 00 00 00 00 00];/* Filled in by U-Boot */ | |
3d954cf1 DN |
494 | clocks = <&emac0_clk>; |
495 | clock-names = "stmmaceth"; | |
16fb4f8b ST |
496 | resets = <&rst EMAC0_RESET>; |
497 | reset-names = "stmmaceth"; | |
ea6856e3 VB |
498 | snps,multicast-filter-bins = <256>; |
499 | snps,perfect-filter-entries = <128>; | |
c01e8cdb VB |
500 | tx-fifo-depth = <4096>; |
501 | rx-fifo-depth = <4096>; | |
3d954cf1 DN |
502 | status = "disabled"; |
503 | }; | |
504 | ||
505 | gmac1: ethernet@ff702000 { | |
506 | compatible = "altr,socfpga-stmmac", "snps,dwmac-3.70a", "snps,dwmac"; | |
2755e187 | 507 | altr,sysmgr-syscon = <&sysmgr 0x60 2>; |
3d954cf1 DN |
508 | reg = <0xff702000 0x2000>; |
509 | interrupts = <0 120 4>; | |
510 | interrupt-names = "macirq"; | |
511 | mac-address = [00 00 00 00 00 00];/* Filled in by U-Boot */ | |
512 | clocks = <&emac1_clk>; | |
513 | clock-names = "stmmaceth"; | |
16fb4f8b ST |
514 | resets = <&rst EMAC1_RESET>; |
515 | reset-names = "stmmaceth"; | |
ea6856e3 VB |
516 | snps,multicast-filter-bins = <256>; |
517 | snps,perfect-filter-entries = <128>; | |
c01e8cdb VB |
518 | tx-fifo-depth = <4096>; |
519 | rx-fifo-depth = <4096>; | |
3d954cf1 | 520 | status = "disabled"; |
66314223 DN |
521 | }; |
522 | ||
fdeda156 ST |
523 | i2c0: i2c@ffc04000 { |
524 | #address-cells = <1>; | |
525 | #size-cells = <0>; | |
526 | compatible = "snps,designware-i2c"; | |
527 | reg = <0xffc04000 0x1000>; | |
528 | clocks = <&l4_sp_clk>; | |
529 | interrupts = <0 158 0x4>; | |
530 | status = "disabled"; | |
531 | }; | |
532 | ||
533 | i2c1: i2c@ffc05000 { | |
534 | #address-cells = <1>; | |
535 | #size-cells = <0>; | |
536 | compatible = "snps,designware-i2c"; | |
537 | reg = <0xffc05000 0x1000>; | |
538 | clocks = <&l4_sp_clk>; | |
539 | interrupts = <0 159 0x4>; | |
540 | status = "disabled"; | |
541 | }; | |
542 | ||
543 | i2c2: i2c@ffc06000 { | |
544 | #address-cells = <1>; | |
545 | #size-cells = <0>; | |
546 | compatible = "snps,designware-i2c"; | |
547 | reg = <0xffc06000 0x1000>; | |
548 | clocks = <&l4_sp_clk>; | |
549 | interrupts = <0 160 0x4>; | |
550 | status = "disabled"; | |
551 | }; | |
552 | ||
553 | i2c3: i2c@ffc07000 { | |
554 | #address-cells = <1>; | |
555 | #size-cells = <0>; | |
556 | compatible = "snps,designware-i2c"; | |
557 | reg = <0xffc07000 0x1000>; | |
558 | clocks = <&l4_sp_clk>; | |
559 | interrupts = <0 161 0x4>; | |
560 | status = "disabled"; | |
561 | }; | |
562 | ||
d11ac1d2 | 563 | gpio0: gpio@ff708000 { |
6ec08c71 SAS |
564 | #address-cells = <1>; |
565 | #size-cells = <0>; | |
566 | compatible = "snps,dw-apb-gpio"; | |
567 | reg = <0xff708000 0x1000>; | |
568 | clocks = <&per_base_clk>; | |
569 | status = "disabled"; | |
570 | ||
d11ac1d2 | 571 | porta: gpio-controller@0 { |
6ec08c71 SAS |
572 | compatible = "snps,dw-apb-gpio-port"; |
573 | gpio-controller; | |
574 | #gpio-cells = <2>; | |
575 | snps,nr-gpios = <29>; | |
576 | reg = <0>; | |
577 | interrupt-controller; | |
578 | #interrupt-cells = <2>; | |
579 | interrupts = <0 164 4>; | |
580 | }; | |
581 | }; | |
582 | ||
d11ac1d2 | 583 | gpio1: gpio@ff709000 { |
6ec08c71 SAS |
584 | #address-cells = <1>; |
585 | #size-cells = <0>; | |
586 | compatible = "snps,dw-apb-gpio"; | |
587 | reg = <0xff709000 0x1000>; | |
588 | clocks = <&per_base_clk>; | |
589 | status = "disabled"; | |
590 | ||
d11ac1d2 | 591 | portb: gpio-controller@0 { |
6ec08c71 SAS |
592 | compatible = "snps,dw-apb-gpio-port"; |
593 | gpio-controller; | |
594 | #gpio-cells = <2>; | |
595 | snps,nr-gpios = <29>; | |
596 | reg = <0>; | |
597 | interrupt-controller; | |
598 | #interrupt-cells = <2>; | |
599 | interrupts = <0 165 4>; | |
600 | }; | |
601 | }; | |
602 | ||
d11ac1d2 | 603 | gpio2: gpio@ff70a000 { |
6ec08c71 SAS |
604 | #address-cells = <1>; |
605 | #size-cells = <0>; | |
606 | compatible = "snps,dw-apb-gpio"; | |
607 | reg = <0xff70a000 0x1000>; | |
608 | clocks = <&per_base_clk>; | |
609 | status = "disabled"; | |
610 | ||
d11ac1d2 | 611 | portc: gpio-controller@0 { |
6ec08c71 SAS |
612 | compatible = "snps,dw-apb-gpio-port"; |
613 | gpio-controller; | |
614 | #gpio-cells = <2>; | |
615 | snps,nr-gpios = <27>; | |
616 | reg = <0>; | |
617 | interrupt-controller; | |
618 | #interrupt-cells = <2>; | |
619 | interrupts = <0 166 4>; | |
620 | }; | |
621 | }; | |
622 | ||
75a41826 TT |
623 | sdr: sdr@ffc25000 { |
624 | compatible = "syscon"; | |
625 | reg = <0xffc25000 0x1000>; | |
626 | }; | |
627 | ||
628 | sdramedac { | |
629 | compatible = "altr,sdram-edac"; | |
630 | altr,sdr-syscon = <&sdr>; | |
631 | interrupts = <0 39 4>; | |
632 | }; | |
633 | ||
66314223 DN |
634 | L2: l2-cache@fffef000 { |
635 | compatible = "arm,pl310-cache"; | |
636 | reg = <0xfffef000 0x1000>; | |
637 | interrupts = <0 38 0x04>; | |
638 | cache-unified; | |
639 | cache-level = <2>; | |
9a21e55d DN |
640 | arm,tag-latency = <1 1 1>; |
641 | arm,data-latency = <2 1 1>; | |
66314223 DN |
642 | }; |
643 | ||
9b931361 DN |
644 | mmc: dwmmc0@ff704000 { |
645 | compatible = "altr,socfpga-dw-mshc"; | |
646 | reg = <0xff704000 0x1000>; | |
647 | interrupts = <0 139 4>; | |
648 | fifo-depth = <0x400>; | |
649 | #address-cells = <1>; | |
650 | #size-cells = <0>; | |
5459f9ab | 651 | clocks = <&l4_mp_clk>, <&sdmmc_clk_divided>; |
9b931361 DN |
652 | clock-names = "biu", "ciu"; |
653 | }; | |
654 | ||
8b907c8b DN |
655 | ocram: sram@ffff0000 { |
656 | compatible = "mmio-sram"; | |
657 | reg = <0xffff0000 0x10000>; | |
658 | }; | |
659 | ||
ba6b96b3 TT |
660 | spi0: spi@fff00000 { |
661 | compatible = "snps,dw-apb-ssi"; | |
662 | #address-cells = <1>; | |
663 | #size-cells = <0>; | |
664 | reg = <0xfff00000 0x1000>; | |
665 | interrupts = <0 154 4>; | |
666 | num-cs = <4>; | |
667 | clocks = <&spi_m_clk>; | |
668 | status = "disabled"; | |
669 | }; | |
670 | ||
8508452e DN |
671 | scu: snoop-control-unit@fffec000 { |
672 | compatible = "arm,cortex-a9-scu"; | |
673 | reg = <0xfffec000 0x100>; | |
674 | }; | |
675 | ||
ba6b96b3 TT |
676 | spi1: spi@fff01000 { |
677 | compatible = "snps,dw-apb-ssi"; | |
678 | #address-cells = <1>; | |
679 | #size-cells = <0>; | |
680 | reg = <0xfff01000 0x1000>; | |
1ac31de7 | 681 | interrupts = <0 155 4>; |
ba6b96b3 TT |
682 | num-cs = <4>; |
683 | clocks = <&spi_m_clk>; | |
684 | status = "disabled"; | |
685 | }; | |
686 | ||
66314223 DN |
687 | /* Local timer */ |
688 | timer@fffec600 { | |
689 | compatible = "arm,cortex-a9-twd-timer"; | |
690 | reg = <0xfffec600 0x100>; | |
691 | interrupts = <1 13 0xf04>; | |
159c7f89 | 692 | clocks = <&mpu_periph_clk>; |
66314223 DN |
693 | }; |
694 | ||
c2ad2844 | 695 | timer0: timer0@ffc08000 { |
620f5e1c | 696 | compatible = "snps,dw-apb-timer"; |
66314223 | 697 | interrupts = <0 167 4>; |
66314223 | 698 | reg = <0xffc08000 0x1000>; |
bd785efd DN |
699 | clocks = <&l4_sp_clk>; |
700 | clock-names = "timer"; | |
66314223 DN |
701 | }; |
702 | ||
c2ad2844 | 703 | timer1: timer1@ffc09000 { |
620f5e1c | 704 | compatible = "snps,dw-apb-timer"; |
66314223 | 705 | interrupts = <0 168 4>; |
66314223 | 706 | reg = <0xffc09000 0x1000>; |
bd785efd DN |
707 | clocks = <&l4_sp_clk>; |
708 | clock-names = "timer"; | |
66314223 DN |
709 | }; |
710 | ||
c2ad2844 | 711 | timer2: timer2@ffd00000 { |
620f5e1c | 712 | compatible = "snps,dw-apb-timer"; |
66314223 | 713 | interrupts = <0 169 4>; |
66314223 | 714 | reg = <0xffd00000 0x1000>; |
bd785efd DN |
715 | clocks = <&osc1>; |
716 | clock-names = "timer"; | |
66314223 DN |
717 | }; |
718 | ||
c2ad2844 | 719 | timer3: timer3@ffd01000 { |
620f5e1c | 720 | compatible = "snps,dw-apb-timer"; |
66314223 | 721 | interrupts = <0 170 4>; |
66314223 | 722 | reg = <0xffd01000 0x1000>; |
bd785efd DN |
723 | clocks = <&osc1>; |
724 | clock-names = "timer"; | |
66314223 DN |
725 | }; |
726 | ||
c2ad2844 | 727 | uart0: serial0@ffc02000 { |
66314223 DN |
728 | compatible = "snps,dw-apb-uart"; |
729 | reg = <0xffc02000 0x1000>; | |
66314223 DN |
730 | interrupts = <0 162 4>; |
731 | reg-shift = <2>; | |
732 | reg-io-width = <4>; | |
bd785efd | 733 | clocks = <&l4_sp_clk>; |
78c03c7a ST |
734 | dmas = <&pdma 28>, |
735 | <&pdma 29>; | |
736 | dma-names = "tx", "rx"; | |
66314223 DN |
737 | }; |
738 | ||
c2ad2844 | 739 | uart1: serial1@ffc03000 { |
66314223 DN |
740 | compatible = "snps,dw-apb-uart"; |
741 | reg = <0xffc03000 0x1000>; | |
66314223 DN |
742 | interrupts = <0 163 4>; |
743 | reg-shift = <2>; | |
744 | reg-io-width = <4>; | |
bd785efd | 745 | clocks = <&l4_sp_clk>; |
78c03c7a ST |
746 | dmas = <&pdma 30>, |
747 | <&pdma 31>; | |
748 | dma-names = "tx", "rx"; | |
66314223 | 749 | }; |
9c4566a1 | 750 | |
16fb4f8b | 751 | rst: rstmgr@ffd05000 { |
dc8fbed5 | 752 | #reset-cells = <1>; |
7857d560 ST |
753 | compatible = "altr,rst-mgr"; |
754 | reg = <0xffd05000 0x1000>; | |
755 | }; | |
9c4566a1 | 756 | |
1403250b DN |
757 | usbphy0: usbphy@0 { |
758 | #phy-cells = <0>; | |
759 | compatible = "usb-nop-xceiv"; | |
760 | status = "okay"; | |
761 | }; | |
762 | ||
763 | usb0: usb@ffb00000 { | |
764 | compatible = "snps,dwc2"; | |
765 | reg = <0xffb00000 0xffff>; | |
766 | interrupts = <0 125 4>; | |
767 | clocks = <&usb_mp_clk>; | |
768 | clock-names = "otg"; | |
769 | phys = <&usbphy0>; | |
770 | phy-names = "usb2-phy"; | |
771 | status = "disabled"; | |
772 | }; | |
773 | ||
774 | usb1: usb@ffb40000 { | |
775 | compatible = "snps,dwc2"; | |
776 | reg = <0xffb40000 0xffff>; | |
777 | interrupts = <0 128 4>; | |
778 | clocks = <&usb_mp_clk>; | |
779 | clock-names = "otg"; | |
780 | phys = <&usbphy0>; | |
781 | phy-names = "usb2-phy"; | |
782 | status = "disabled"; | |
783 | }; | |
784 | ||
a98b6057 ST |
785 | watchdog0: watchdog@ffd02000 { |
786 | compatible = "snps,dw-wdt"; | |
787 | reg = <0xffd02000 0x1000>; | |
788 | interrupts = <0 171 4>; | |
789 | clocks = <&osc1>; | |
790 | status = "disabled"; | |
791 | }; | |
792 | ||
793 | watchdog1: watchdog@ffd03000 { | |
794 | compatible = "snps,dw-wdt"; | |
795 | reg = <0xffd03000 0x1000>; | |
796 | interrupts = <0 172 4>; | |
797 | clocks = <&osc1>; | |
798 | status = "disabled"; | |
799 | }; | |
800 | ||
a5d6ac2a | 801 | sysmgr: sysmgr@ffd08000 { |
9b931361 DN |
802 | compatible = "altr,sys-mgr", "syscon"; |
803 | reg = <0xffd08000 0x4000>; | |
804 | }; | |
66314223 DN |
805 | }; |
806 | }; |