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ARM: at91/dt: sama5d4: add aes, sha and tdes nodes
[linux-2.6-block.git] / arch / arm / boot / dts / sama5d4.dtsi
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7c661394
NF		 1/*
2 * sama5d4.dtsi - Device Tree Include file for SAMA5D4 family SoC
3 *
4 * Copyright (C) 2014 Atmel,
5 * 2014 Nicolas Ferre <nicolas.ferre@atmel.com>
6 *
7 * This file is dual-licensed: you can use it either under the terms
8 * of the GPL or the X11 license, at your option. Note that this dual
9 * licensing only applies to this file, and not this project as a
10 * whole.
11 *
1d2a0563 12 * a) This file is free software; you can redistribute it and/or
7c661394
NF		 13 * modify it under the terms of the GNU General Public License as
14 * published by the Free Software Foundation; either version 2 of the
15 * License, or (at your option) any later version.
16 *
1d2a0563 17 * This file is distributed in the hope that it will be useful,
7c661394
NF		 18 * but WITHOUT ANY WARRANTY; without even the implied warranty of
19 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
20 * GNU General Public License for more details.
21 *
22 * Or, alternatively,
23 *
24 * b) Permission is hereby granted, free of charge, to any person
25 * obtaining a copy of this software and associated documentation
26 * files (the "Software"), to deal in the Software without
27 * restriction, including without limitation the rights to use,
28 * copy, modify, merge, publish, distribute, sublicense, and/or
29 * sell copies of the Software, and to permit persons to whom the
30 * Software is furnished to do so, subject to the following
31 * conditions:
32 *
33 * The above copyright notice and this permission notice shall be
34 * included in all copies or substantial portions of the Software.
35 *
36 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
37 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
38 * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
39 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
40 * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
41 * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
42 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
43 * OTHER DEALINGS IN THE SOFTWARE.
44 */
45
46#include "skeleton.dtsi"
47#include <dt-bindings/clock/at91.h>
b3c7a497 48#include <dt-bindings/dma/at91.h>
7c661394
NF		 49#include <dt-bindings/pinctrl/at91.h>
50#include <dt-bindings/interrupt-controller/irq.h>
51#include <dt-bindings/gpio/gpio.h>
52
53/ {
54 model = "Atmel SAMA5D4 family SoC";
55 compatible = "atmel,sama5d4";
56 interrupt-parent = <&aic>;
57
58 aliases {
59 serial0 = &usart3;
60 serial1 = &usart4;
61 serial2 = &usart2;
62 gpio0 = &pioA;
63 gpio1 = &pioB;
64 gpio2 = &pioC;
1de77b7f 65 gpio3 = &pioD;
7c661394 66 gpio4 = &pioE;
0697edd7
BS		 67 ssc0 = &ssc0;
68 ssc1 = &ssc1;
7c661394
NF		 69 tcb0 = &tcb0;
70 tcb1 = &tcb1;
a547f60a 71 i2c0 = &i2c0;
4cc7cdf3 72 i2c1 = &i2c1;
7c661394
NF		 73 i2c2 = &i2c2;
74 };
75 cpus {
76 #address-cells = <1>;
77 #size-cells = <0>;
78
79 cpu@0 {
80 device_type = "cpu";
81 compatible = "arm,cortex-a5";
82 reg = <0>;
83 next-level-cache = <&L2>;
84 };
85 };
86
87 memory {
88 reg = <0x20000000 0x20000000>;
89 };
90
91 clocks {
92 slow_xtal: slow_xtal {
93 compatible = "fixed-clock";
94 #clock-cells = <0>;
95 clock-frequency = <0>;
96 };
97
98 main_xtal: main_xtal {
99 compatible = "fixed-clock";
100 #clock-cells = <0>;
101 clock-frequency = <0>;
102 };
103
104 adc_op_clk: adc_op_clk{
105 compatible = "fixed-clock";
106 #clock-cells = <0>;
107 clock-frequency = <1000000>;
108 };
109 };
110
f04660e4
AB		 111 ns_sram: sram@00210000 {
112 compatible = "mmio-sram";
113 reg = <0x00210000 0x10000>;
114 };
115
7c661394
NF		 116 ahb {
117 compatible = "simple-bus";
118 #address-cells = <1>;
119 #size-cells = <1>;
120 ranges;
121
122 usb0: gadget@00400000 {
123 #address-cells = <1>;
124 #size-cells = <0>;
125 compatible = "atmel,at91sam9rl-udc";
126 reg = <0x00400000 0x100000
127 0xfc02c000 0x4000>;
128 interrupts = <47 IRQ_TYPE_LEVEL_HIGH 2>;
129 clocks = <&udphs_clk>, <&utmi>;
130 clock-names = "pclk", "hclk";
131 status = "disabled";
132
133 ep0 {
134 reg = <0>;
135 atmel,fifo-size = <64>;
136 atmel,nb-banks = <1>;
137 };
138
139 ep1 {
140 reg = <1>;
141 atmel,fifo-size = <1024>;
142 atmel,nb-banks = <3>;
143 atmel,can-dma;
144 atmel,can-isoc;
145 };
146
147 ep2 {
148 reg = <2>;
149 atmel,fifo-size = <1024>;
150 atmel,nb-banks = <3>;
151 atmel,can-dma;
152 atmel,can-isoc;
153 };
154
155 ep3 {
156 reg = <3>;
157 atmel,fifo-size = <1024>;
158 atmel,nb-banks = <2>;
159 atmel,can-dma;
160 atmel,can-isoc;
161 };
162
163 ep4 {
164 reg = <4>;
165 atmel,fifo-size = <1024>;
166 atmel,nb-banks = <2>;
167 atmel,can-dma;
168 atmel,can-isoc;
169 };
170
171 ep5 {
172 reg = <5>;
173 atmel,fifo-size = <1024>;
174 atmel,nb-banks = <2>;
175 atmel,can-dma;
176 atmel,can-isoc;
177 };
178
179 ep6 {
180 reg = <6>;
181 atmel,fifo-size = <1024>;
182 atmel,nb-banks = <2>;
183 atmel,can-dma;
184 atmel,can-isoc;
185 };
186
187 ep7 {
188 reg = <7>;
189 atmel,fifo-size = <1024>;
190 atmel,nb-banks = <2>;
191 atmel,can-dma;
192 atmel,can-isoc;
193 };
194
195 ep8 {
196 reg = <8>;
197 atmel,fifo-size = <1024>;
198 atmel,nb-banks = <2>;
199 atmel,can-isoc;
200 };
201
202 ep9 {
203 reg = <9>;
204 atmel,fifo-size = <1024>;
205 atmel,nb-banks = <2>;
206 atmel,can-isoc;
207 };
208
209 ep10 {
210 reg = <10>;
211 atmel,fifo-size = <1024>;
212 atmel,nb-banks = <2>;
213 atmel,can-isoc;
214 };
215
216 ep11 {
217 reg = <11>;
218 atmel,fifo-size = <1024>;
219 atmel,nb-banks = <2>;
220 atmel,can-isoc;
221 };
222
223 ep12 {
224 reg = <12>;
225 atmel,fifo-size = <1024>;
226 atmel,nb-banks = <2>;
227 atmel,can-isoc;
228 };
229
230 ep13 {
231 reg = <13>;
232 atmel,fifo-size = <1024>;
233 atmel,nb-banks = <2>;
234 atmel,can-isoc;
235 };
236
237 ep14 {
238 reg = <14>;
239 atmel,fifo-size = <1024>;
240 atmel,nb-banks = <2>;
241 atmel,can-isoc;
242 };
243
244 ep15 {
245 reg = <15>;
246 atmel,fifo-size = <1024>;
247 atmel,nb-banks = <2>;
248 atmel,can-isoc;
249 };
250 };
251
252 usb1: ohci@00500000 {
253 compatible = "atmel,at91rm9200-ohci", "usb-ohci";
254 reg = <0x00500000 0x100000>;
255 interrupts = <46 IRQ_TYPE_LEVEL_HIGH 2>;
256 clocks = <&usb>, <&uhphs_clk>, <&uhphs_clk>,
257 <&uhpck>;
258 clock-names = "usb_clk", "ohci_clk", "hclk", "uhpck";
259 status = "disabled";
260 };
261
262 usb2: ehci@00600000 {
263 compatible = "atmel,at91sam9g45-ehci", "usb-ehci";
264 reg = <0x00600000 0x100000>;
265 interrupts = <46 IRQ_TYPE_LEVEL_HIGH 2>;
266 clocks = <&usb>, <&uhphs_clk>, <&uhpck>;
267 clock-names = "usb_clk", "ehci_clk", "uhpck";
268 status = "disabled";
269 };
270
271 L2: cache-controller@00a00000 {
272 compatible = "arm,pl310-cache";
273 reg = <0x00a00000 0x1000>;
274 interrupts = <67 IRQ_TYPE_LEVEL_HIGH 4>;
275 cache-unified;
276 cache-level = <2>;
277 };
278
279 nand0: nand@80000000 {
fda077c0 280 compatible = "atmel,sama5d4-nand", "atmel,at91rm9200-nand";
7c661394
NF		 281 #address-cells = <1>;
282 #size-cells = <1>;
283 ranges;
284 reg = < 0x80000000 0x08000000 /* EBI CS3 */
285 0xfc05c070 0x00000490 /* SMC PMECC regs */
286 0xfc05c500 0x00000100 /* SMC PMECC Error Location regs */
287 >;
288 interrupts = <22 IRQ_TYPE_LEVEL_HIGH 6>;
289 atmel,nand-addr-offset = <21>;
290 atmel,nand-cmd-offset = <22>;
291 atmel,nand-has-dma;
292 pinctrl-names = "default";
293 pinctrl-0 = <&pinctrl_nand>;
294 status = "disabled";
295
296 nfc@90000000 {
297 compatible = "atmel,sama5d3-nfc";
298 #address-cells = <1>;
299 #size-cells = <1>;
300 reg = <
301 0x90000000 0x10000000 /* NFC Command Registers */
302 0xfc05c000 0x00000070 /* NFC HSMC regs */
303 0x00100000 0x00100000 /* NFC SRAM banks */
304 >;
305 clocks = <&hsmc_clk>;
306 atmel,write-by-sram;
307 };
308 };
309
310 apb {
311 compatible = "simple-bus";
312 #address-cells = <1>;
313 #size-cells = <1>;
314 ranges;
315
b3c7a497
LD		 316 dma1: dma-controller@f0004000 {
317 compatible = "atmel,sama5d4-dma";
318 reg = <0xf0004000 0x200>;
319 interrupts = <50 IRQ_TYPE_LEVEL_HIGH 0>;
320 #dma-cells = <1>;
321 clocks = <&dma1_clk>;
322 clock-names = "dma_clk";
323 };
324
7c661394
NF		 325 ramc0: ramc@f0010000 {
326 compatible = "atmel,sama5d3-ddramc";
327 reg = <0xf0010000 0x200>;
328 clocks = <&ddrck>, <&mpddr_clk>;
329 clock-names = "ddrck", "mpddr";
330 };
331
b3c7a497
LD		 332 dma0: dma-controller@f0014000 {
333 compatible = "atmel,sama5d4-dma";
334 reg = <0xf0014000 0x200>;
335 interrupts = <8 IRQ_TYPE_LEVEL_HIGH 0>;
336 #dma-cells = <1>;
337 clocks = <&dma0_clk>;
338 clock-names = "dma_clk";
339 };
340
7c661394
NF		 341 pmc: pmc@f0018000 {
342 compatible = "atmel,sama5d3-pmc";
343 reg = <0xf0018000 0x120>;
344 interrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>;
345 interrupt-controller;
346 #address-cells = <1>;
347 #size-cells = <0>;
348 #interrupt-cells = <1>;
349
350 main_rc_osc: main_rc_osc {
351 compatible = "atmel,at91sam9x5-clk-main-rc-osc";
352 #clock-cells = <0>;
353 interrupt-parent = <&pmc>;
354 interrupts = <AT91_PMC_MOSCRCS>;
355 clock-frequency = <12000000>;
356 clock-accuracy = <100000000>;
357 };
358
359 main_osc: main_osc {
360 compatible = "atmel,at91rm9200-clk-main-osc";
361 #clock-cells = <0>;
362 interrupt-parent = <&pmc>;
363 interrupts = <AT91_PMC_MOSCS>;
364 clocks = <&main_xtal>;
365 };
366
367 main: mainck {
368 compatible = "atmel,at91sam9x5-clk-main";
369 #clock-cells = <0>;
370 interrupt-parent = <&pmc>;
371 interrupts = <AT91_PMC_MOSCSELS>;
372 clocks = <&main_rc_osc &main_osc>;
373 };
374
375 plla: pllack {
376 compatible = "atmel,sama5d3-clk-pll";
377 #clock-cells = <0>;
378 interrupt-parent = <&pmc>;
379 interrupts = <AT91_PMC_LOCKA>;
380 clocks = <&main>;
381 reg = <0>;
382 atmel,clk-input-range = <12000000 12000000>;
383 #atmel,pll-clk-output-range-cells = <4>;
384 atmel,pll-clk-output-ranges = <600000000 1200000000 0 0>;
385 };
386
387 plladiv: plladivck {
388 compatible = "atmel,at91sam9x5-clk-plldiv";
389 #clock-cells = <0>;
390 clocks = <&plla>;
391 };
392
393 utmi: utmick {
394 compatible = "atmel,at91sam9x5-clk-utmi";
395 #clock-cells = <0>;
396 interrupt-parent = <&pmc>;
397 interrupts = <AT91_PMC_LOCKU>;
398 clocks = <&main>;
399 };
400
401 mck: masterck {
402 compatible = "atmel,at91sam9x5-clk-master";
403 #clock-cells = <0>;
404 interrupt-parent = <&pmc>;
405 interrupts = <AT91_PMC_MCKRDY>;
406 clocks = <&clk32k>, <&main>, <&plladiv>, <&utmi>;
407 atmel,clk-output-range = <125000000 177000000>;
408 atmel,clk-divisors = <1 2 4 3>;
409 };
410
411 h32ck: h32mxck {
412 #clock-cells = <0>;
413 compatible = "atmel,sama5d4-clk-h32mx";
414 clocks = <&mck>;
415 };
416
417 usb: usbck {
418 compatible = "atmel,at91sam9x5-clk-usb";
419 #clock-cells = <0>;
420 clocks = <&plladiv>, <&utmi>;
421 };
422
423 prog: progck {
424 compatible = "atmel,at91sam9x5-clk-programmable";
425 #address-cells = <1>;
426 #size-cells = <0>;
427 interrupt-parent = <&pmc>;
428 clocks = <&clk32k>, <&main>, <&plladiv>, <&utmi>, <&mck>;
429
430 prog0: prog0 {
431 #clock-cells = <0>;
432 reg = <0>;
433 interrupts = <AT91_PMC_PCKRDY(0)>;
434 };
435
436 prog1: prog1 {
437 #clock-cells = <0>;
438 reg = <1>;
439 interrupts = <AT91_PMC_PCKRDY(1)>;
440 };
441
442 prog2: prog2 {
443 #clock-cells = <0>;
444 reg = <2>;
445 interrupts = <AT91_PMC_PCKRDY(2)>;
446 };
447 };
448
449 smd: smdclk {
450 compatible = "atmel,at91sam9x5-clk-smd";
451 #clock-cells = <0>;
452 clocks = <&plladiv>, <&utmi>;
453 };
454
455 systemck {
456 compatible = "atmel,at91rm9200-clk-system";
457 #address-cells = <1>;
458 #size-cells = <0>;
459
460 ddrck: ddrck {
461 #clock-cells = <0>;
462 reg = <2>;
463 clocks = <&mck>;
464 };
465
466 lcdck: lcdck {
467 #clock-cells = <0>;
468 reg = <4>;
469 clocks = <&smd>;
470 };
471
472 smdck: smdck {
473 #clock-cells = <0>;
474 reg = <4>;
475 clocks = <&smd>;
476 };
477
478 uhpck: uhpck {
479 #clock-cells = <0>;
480 reg = <6>;
481 clocks = <&usb>;
482 };
483
484 udpck: udpck {
485 #clock-cells = <0>;
486 reg = <7>;
487 clocks = <&usb>;
488 };
489
490 pck0: pck0 {
491 #clock-cells = <0>;
492 reg = <8>;
493 clocks = <&prog0>;
494 };
495
496 pck1: pck1 {
497 #clock-cells = <0>;
498 reg = <9>;
499 clocks = <&prog1>;
500 };
501
502 pck2: pck2 {
503 #clock-cells = <0>;
504 reg = <10>;
505 clocks = <&prog2>;
506 };
507 };
508
509 periph32ck {
510 compatible = "atmel,at91sam9x5-clk-peripheral";
511 #address-cells = <1>;
512 #size-cells = <0>;
513 clocks = <&h32ck>;
514
515 pioD_clk: pioD_clk {
516 #clock-cells = <0>;
517 reg = <5>;
518 };
519
520 usart0_clk: usart0_clk {
521 #clock-cells = <0>;
522 reg = <6>;
523 };
524
525 usart1_clk: usart1_clk {
526 #clock-cells = <0>;
527 reg = <7>;
528 };
529
530 icm_clk: icm_clk {
531 #clock-cells = <0>;
532 reg = <9>;
533 };
534
535 aes_clk: aes_clk {
536 #clock-cells = <0>;
537 reg = <12>;
538 };
539
540 tdes_clk: tdes_clk {
541 #clock-cells = <0>;
542 reg = <14>;
543 };
544
545 sha_clk: sha_clk {
546 #clock-cells = <0>;
547 reg = <15>;
548 };
549
550 matrix1_clk: matrix1_clk {
551 #clock-cells = <0>;
552 reg = <17>;
553 };
554
555 hsmc_clk: hsmc_clk {
556 #clock-cells = <0>;
557 reg = <22>;
558 };
559
560 pioA_clk: pioA_clk {
561 #clock-cells = <0>;
562 reg = <23>;
563 };
564
565 pioB_clk: pioB_clk {
566 #clock-cells = <0>;
567 reg = <24>;
568 };
569
570 pioC_clk: pioC_clk {
571 #clock-cells = <0>;
572 reg = <25>;
573 };
574
575 pioE_clk: pioE_clk {
576 #clock-cells = <0>;
577 reg = <26>;
578 };
579
580 uart0_clk: uart0_clk {
581 #clock-cells = <0>;
582 reg = <27>;
583 };
584
585 uart1_clk: uart1_clk {
586 #clock-cells = <0>;
587 reg = <28>;
588 };
589
590 usart2_clk: usart2_clk {
591 #clock-cells = <0>;
592 reg = <29>;
593 };
594
595 usart3_clk: usart3_clk {
596 #clock-cells = <0>;
597 reg = <30>;
598 };
599
600 usart4_clk: usart4_clk {
601 #clock-cells = <0>;
602 reg = <31>;
603 };
604
605 twi0_clk: twi0_clk {
606 reg = <32>;
607 #clock-cells = <0>;
608 };
609
610 twi1_clk: twi1_clk {
611 #clock-cells = <0>;
612 reg = <33>;
613 };
614
615 twi2_clk: twi2_clk {
616 #clock-cells = <0>;
617 reg = <34>;
618 };
619
620 mci0_clk: mci0_clk {
621 #clock-cells = <0>;
622 reg = <35>;
623 };
624
625 mci1_clk: mci1_clk {
626 #clock-cells = <0>;
627 reg = <36>;
628 };
629
630 spi0_clk: spi0_clk {
631 #clock-cells = <0>;
632 reg = <37>;
633 };
634
635 spi1_clk: spi1_clk {
636 #clock-cells = <0>;
637 reg = <38>;
638 };
639
640 spi2_clk: spi2_clk {
641 #clock-cells = <0>;
642 reg = <39>;
643 };
644
645 tcb0_clk: tcb0_clk {
646 #clock-cells = <0>;
647 reg = <40>;
648 };
649
650 tcb1_clk: tcb1_clk {
651 #clock-cells = <0>;
652 reg = <41>;
653 };
654
655 tcb2_clk: tcb2_clk {
656 #clock-cells = <0>;
657 reg = <42>;
658 };
659
660 pwm_clk: pwm_clk {
661 #clock-cells = <0>;
662 reg = <43>;
663 };
664
665 adc_clk: adc_clk {
666 #clock-cells = <0>;
667 reg = <44>;
668 };
669
670 dbgu_clk: dbgu_clk {
671 #clock-cells = <0>;
672 reg = <45>;
673 };
674
675 uhphs_clk: uhphs_clk {
676 #clock-cells = <0>;
677 reg = <46>;
678 };
679
680 udphs_clk: udphs_clk {
681 #clock-cells = <0>;
682 reg = <47>;
683 };
684
685 ssc0_clk: ssc0_clk {
686 #clock-cells = <0>;
687 reg = <48>;
688 };
689
690 ssc1_clk: ssc1_clk {
691 #clock-cells = <0>;
692 reg = <49>;
693 };
694
695 trng_clk: trng_clk {
696 #clock-cells = <0>;
697 reg = <53>;
698 };
699
700 macb0_clk: macb0_clk {
701 #clock-cells = <0>;
702 reg = <54>;
703 };
704
705 macb1_clk: macb1_clk {
706 #clock-cells = <0>;
707 reg = <55>;
708 };
709
710 fuse_clk: fuse_clk {
711 #clock-cells = <0>;
712 reg = <57>;
713 };
714
715 securam_clk: securam_clk {
716 #clock-cells = <0>;
717 reg = <59>;
718 };
719
720 smd_clk: smd_clk {
721 #clock-cells = <0>;
722 reg = <61>;
723 };
724
725 twi3_clk: twi3_clk {
726 #clock-cells = <0>;
727 reg = <62>;
728 };
729
730 catb_clk: catb_clk {
731 #clock-cells = <0>;
732 reg = <63>;
733 };
734 };
735
736 periph64ck {
737 compatible = "atmel,at91sam9x5-clk-peripheral";
738 #address-cells = <1>;
739 #size-cells = <0>;
740 clocks = <&mck>;
741
742 dma0_clk: dma0_clk {
743 #clock-cells = <0>;
744 reg = <8>;
745 };
746
747 cpkcc_clk: cpkcc_clk {
748 #clock-cells = <0>;
749 reg = <10>;
750 };
751
752 aesb_clk: aesb_clk {
753 #clock-cells = <0>;
754 reg = <13>;
755 };
756
757 mpddr_clk: mpddr_clk {
758 #clock-cells = <0>;
759 reg = <16>;
760 };
761
762 matrix0_clk: matrix0_clk {
763 #clock-cells = <0>;
764 reg = <18>;
765 };
766
767 vdec_clk: vdec_clk {
768 #clock-cells = <0>;
769 reg = <19>;
770 };
771
772 dma1_clk: dma1_clk {
773 #clock-cells = <0>;
774 reg = <50>;
775 };
776
777 lcd_clk: lcd_clk {
778 #clock-cells = <0>;
779 reg = <51>;
780 };
781
782 isi_clk: isi_clk {
783 #clock-cells = <0>;
784 reg = <52>;
785 };
786 };
787 };
788
789 mmc0: mmc@f8000000 {
790 compatible = "atmel,hsmci";
791 reg = <0xf8000000 0x600>;
792 interrupts = <35 IRQ_TYPE_LEVEL_HIGH 0>;
b3c7a497
LD		 793 dmas = <&dma1
794 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1)
795 | AT91_XDMAC_DT_PERID(0))>;
796 dma-names = "rxtx";
7c661394
NF		 797 pinctrl-names = "default";
798 pinctrl-0 = <&pinctrl_mmc0_clk_cmd_dat0 &pinctrl_mmc0_dat1_3>;
799 status = "disabled";
800 #address-cells = <1>;
801 #size-cells = <0>;
802 clocks = <&mci0_clk>;
803 clock-names = "mci_clk";
804 };
805
0697edd7
BS		 806 ssc0: ssc@f8008000 {
807 compatible = "atmel,at91sam9g45-ssc";
808 reg = <0xf8008000 0x4000>;
809 interrupts = <48 IRQ_TYPE_LEVEL_HIGH 0>;
810 pinctrl-names = "default";
811 pinctrl-0 = <&pinctrl_ssc0_tx &pinctrl_ssc0_rx>;
812 dmas = <&dma1
813 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1)
814 | AT91_XDMAC_DT_PERID(26))>,
815 <&dma1
816 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1)
817 | AT91_XDMAC_DT_PERID(27))>;
818 dma-names = "tx", "rx";
819 clocks = <&ssc0_clk>;
820 clock-names = "pclk";
821 status = "disabled";
822 };
823
7c661394
NF		 824 spi0: spi@f8010000 {
825 #address-cells = <1>;
826 #size-cells = <0>;
827 compatible = "atmel,at91rm9200-spi";
828 reg = <0xf8010000 0x100>;
829 interrupts = <37 IRQ_TYPE_LEVEL_HIGH 3>;
b3c7a497
LD		 830 dmas = <&dma1
831 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1)
832 | AT91_XDMAC_DT_PERID(10))>,
833 <&dma1
834 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1)
835 | AT91_XDMAC_DT_PERID(11))>;
836 dma-names = "tx", "rx";
7c661394
NF		 837 pinctrl-names = "default";
838 pinctrl-0 = <&pinctrl_spi0>;
839 clocks = <&spi0_clk>;
840 clock-names = "spi_clk";
841 status = "disabled";
842 };
843
844 i2c0: i2c@f8014000 {
845 compatible = "atmel,at91sam9x5-i2c";
846 reg = <0xf8014000 0x4000>;
847 interrupts = <32 IRQ_TYPE_LEVEL_HIGH 6>;
b3c7a497
LD		 848 dmas = <&dma1
849 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1)
850 | AT91_XDMAC_DT_PERID(2))>,
851 <&dma1
852 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1)
853 | AT91_XDMAC_DT_PERID(3))>;
854 dma-names = "tx", "rx";
7c661394
NF		 855 pinctrl-names = "default";
856 pinctrl-0 = <&pinctrl_i2c0>;
857 #address-cells = <1>;
858 #size-cells = <0>;
859 clocks = <&twi0_clk>;
860 status = "disabled";
861 };
862
4cc7cdf3
PA		 863 i2c1: i2c@f8018000 {
864 compatible = "atmel,at91sam9x5-i2c";
865 reg = <0xf8018000 0x4000>;
866 interrupts = <33 IRQ_TYPE_LEVEL_HIGH 6>;
867 dmas = <&dma1
868 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1))
869 AT91_XDMAC_DT_PERID(4)>,
870 <&dma1
871 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1))
872 AT91_XDMAC_DT_PERID(5)>;
873 dma-names = "tx", "rx";
874 pinctrl-names = "default";
875 pinctrl-0 = <&pinctrl_i2c1>;
876 #address-cells = <1>;
877 #size-cells = <0>;
878 clocks = <&twi1_clk>;
879 status = "disabled";
880 };
881
7c661394
NF		 882 tcb0: timer@f801c000 {
883 compatible = "atmel,at91sam9x5-tcb";
884 reg = <0xf801c000 0x100>;
885 interrupts = <40 IRQ_TYPE_LEVEL_HIGH 0>;
886 clocks = <&tcb0_clk>;
887 clock-names = "t0_clk";
888 };
889
890 macb0: ethernet@f8020000 {
891 compatible = "atmel,sama5d4-gem";
892 reg = <0xf8020000 0x100>;
893 interrupts = <54 IRQ_TYPE_LEVEL_HIGH 3>;
894 pinctrl-names = "default";
895 pinctrl-0 = <&pinctrl_macb0_rmii>;
9917defd
JW		 896 #address-cells = <1>;
897 #size-cells = <0>;
7c661394
NF		 898 clocks = <&macb0_clk>, <&macb0_clk>;
899 clock-names = "hclk", "pclk";
900 status = "disabled";
901 };
902
903 i2c2: i2c@f8024000 {
904 compatible = "atmel,at91sam9x5-i2c";
905 reg = <0xf8024000 0x4000>;
84f017a7 906 interrupts = <34 IRQ_TYPE_LEVEL_HIGH 6>;
b3c7a497
LD		 907 dmas = <&dma1
908 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1)
909 | AT91_XDMAC_DT_PERID(6))>,
910 <&dma1
911 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1)
912 | AT91_XDMAC_DT_PERID(7))>;
913 dma-names = "tx", "rx";
7c661394
NF		 914 pinctrl-names = "default";
915 pinctrl-0 = <&pinctrl_i2c2>;
916 #address-cells = <1>;
917 #size-cells = <0>;
918 clocks = <&twi2_clk>;
919 status = "disabled";
920 };
921
c3ef0b0c
AB		 922 sfr: sfr@f8028000 {
923 compatible = "atmel,sama5d4-sfr", "syscon";
924 reg = <0xf8028000 0x60>;
925 };
926
7c661394
NF		 927 mmc1: mmc@fc000000 {
928 compatible = "atmel,hsmci";
929 reg = <0xfc000000 0x600>;
930 interrupts = <36 IRQ_TYPE_LEVEL_HIGH 0>;
b3c7a497
LD		 931 dmas = <&dma1
932 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1)
933 | AT91_XDMAC_DT_PERID(1))>;
934 dma-names = "rxtx";
7c661394
NF		 935 pinctrl-names = "default";
936 pinctrl-0 = <&pinctrl_mmc1_clk_cmd_dat0 &pinctrl_mmc1_dat1_3>;
937 status = "disabled";
938 #address-cells = <1>;
939 #size-cells = <0>;
940 clocks = <&mci1_clk>;
941 clock-names = "mci_clk";
942 };
943
944 usart2: serial@fc008000 {
945 compatible = "atmel,at91sam9260-usart";
946 reg = <0xfc008000 0x100>;
947 interrupts = <29 IRQ_TYPE_LEVEL_HIGH 5>;
b3c7a497
LD		 948 dmas = <&dma1
949 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1)
950 | AT91_XDMAC_DT_PERID(16))>,
951 <&dma1
952 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1)
953 | AT91_XDMAC_DT_PERID(17))>;
954 dma-names = "tx", "rx";
7c661394
NF		 955 pinctrl-names = "default";
956 pinctrl-0 = <&pinctrl_usart2 &pinctrl_usart2_rts &pinctrl_usart2_cts>;
957 clocks = <&usart2_clk>;
958 clock-names = "usart";
959 status = "disabled";
960 };
961
962 usart3: serial@fc00c000 {
963 compatible = "atmel,at91sam9260-usart";
964 reg = <0xfc00c000 0x100>;
965 interrupts = <30 IRQ_TYPE_LEVEL_HIGH 5>;
b3c7a497
LD		 966 dmas = <&dma1
967 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1)
968 | AT91_XDMAC_DT_PERID(18))>,
969 <&dma1
970 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1)
971 | AT91_XDMAC_DT_PERID(19))>;
972 dma-names = "tx", "rx";
7c661394
NF		 973 pinctrl-names = "default";
974 pinctrl-0 = <&pinctrl_usart3>;
975 clocks = <&usart3_clk>;
976 clock-names = "usart";
977 status = "disabled";
978 };
979
980 usart4: serial@fc010000 {
981 compatible = "atmel,at91sam9260-usart";
982 reg = <0xfc010000 0x100>;
983 interrupts = <31 IRQ_TYPE_LEVEL_HIGH 5>;
b3c7a497
LD		 984 dmas = <&dma1
985 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1)
986 | AT91_XDMAC_DT_PERID(20))>,
987 <&dma1
988 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1)
989 | AT91_XDMAC_DT_PERID(21))>;
990 dma-names = "tx", "rx";
7c661394
NF		 991 pinctrl-names = "default";
992 pinctrl-0 = <&pinctrl_usart4>;
993 clocks = <&usart4_clk>;
994 clock-names = "usart";
995 status = "disabled";
996 };
997
0697edd7
BS		 998 ssc1: ssc@fc014000 {
999 compatible = "atmel,at91sam9g45-ssc";
1000 reg = <0xfc014000 0x4000>;
1001 interrupts = <49 IRQ_TYPE_LEVEL_HIGH 0>;
1002 pinctrl-names = "default";
1003 pinctrl-0 = <&pinctrl_ssc1_tx &pinctrl_ssc1_rx>;
1004 dmas = <&dma1
1005 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1)
1006 | AT91_XDMAC_DT_PERID(28))>,
1007 <&dma1
1008 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1)
1009 | AT91_XDMAC_DT_PERID(29))>;
1010 dma-names = "tx", "rx";
1011 clocks = <&ssc1_clk>;
1012 clock-names = "pclk";
1013 status = "disabled";
1014 };
1015
7c661394
NF		 1016 tcb1: timer@fc020000 {
1017 compatible = "atmel,at91sam9x5-tcb";
1018 reg = <0xfc020000 0x100>;
1019 interrupts = <41 IRQ_TYPE_LEVEL_HIGH 0>;
1020 clocks = <&tcb1_clk>;
1021 clock-names = "t0_clk";
1022 };
1023
1024 adc0: adc@fc034000 {
1025 compatible = "atmel,at91sam9x5-adc";
1026 reg = <0xfc034000 0x100>;
1027 interrupts = <44 IRQ_TYPE_LEVEL_HIGH 5>;
1028 pinctrl-names = "default";
1029 pinctrl-0 = <
1030 /* external trigger is conflict with USBA_VBUS */
1031 &pinctrl_adc0_ad0
1032 &pinctrl_adc0_ad1
1033 &pinctrl_adc0_ad2
1034 &pinctrl_adc0_ad3
1035 &pinctrl_adc0_ad4
1036 >;
1037 clocks = <&adc_clk>,
1038 <&adc_op_clk>;
1039 clock-names = "adc_clk", "adc_op_clk";
1040 atmel,adc-channels-used = <0x01f>;
1041 atmel,adc-startup-time = <40>;
1042 atmel,adc-use-external;
1043 atmel,adc-vref = <3000>;
1044 atmel,adc-res = <8 10>;
1045 atmel,adc-sample-hold-time = <11>;
1046 atmel,adc-res-names = "lowres", "highres";
1047 atmel,adc-ts-pressure-threshold = <10000>;
1048 status = "disabled";
1049
1050 trigger@0 {
1051 trigger-name = "external-rising";
1052 trigger-value = <0x1>;
1053 trigger-external;
1054 };
1055 trigger@1 {
1056 trigger-name = "external-falling";
1057 trigger-value = <0x2>;
1058 trigger-external;
1059 };
1060 trigger@2 {
1061 trigger-name = "external-any";
1062 trigger-value = <0x3>;
1063 trigger-external;
1064 };
1065 trigger@3 {
1066 trigger-name = "continuous";
1067 trigger-value = <0x6>;
1068 };
1069 };
1070
83906783
LZ		 1071 aes@fc044000 {
1072 compatible = "atmel,at91sam9g46-aes";
1073 reg = <0xfc044000 0x100>;
1074 interrupts = <12 IRQ_TYPE_LEVEL_HIGH 0>;
1075 dmas = <&dma0 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1))
1076 AT91_XDMAC_DT_PERID(41)>,
1077 <&dma0 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1))
1078 AT91_XDMAC_DT_PERID(40)>;
1079 dma-names = "tx", "rx";
1080 clocks = <&aes_clk>;
1081 clock-names = "aes_clk";
1082 status = "disabled";
1083 };
1084
1085 tdes@fc04c000 {
1086 compatible = "atmel,at91sam9g46-tdes";
1087 reg = <0xfc04c000 0x100>;
1088 interrupts = <14 IRQ_TYPE_LEVEL_HIGH 0>;
1089 dmas = <&dma0 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1))
1090 AT91_XDMAC_DT_PERID(42)>,
1091 <&dma0 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1))
1092 AT91_XDMAC_DT_PERID(43)>;
1093 dma-names = "tx", "rx";
1094 clocks = <&tdes_clk>;
1095 clock-names = "tdes_clk";
1096 status = "disabled";
1097 };
1098
1099 sha@fc050000 {
1100 compatible = "atmel,at91sam9g46-sha";
1101 reg = <0xfc050000 0x100>;
1102 interrupts = <15 IRQ_TYPE_LEVEL_HIGH 0>;
1103 dmas = <&dma0 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1))
1104 AT91_XDMAC_DT_PERID(44)>;
1105 dma-names = "tx";
1106 clocks = <&sha_clk>;
1107 clock-names = "sha_clk";
1108 status = "disabled";
1109 };
1110
7c661394
NF		 1111 rstc@fc068600 {
1112 compatible = "atmel,at91sam9g45-rstc";
1113 reg = <0xfc068600 0x10>;
1114 };
1115
1116 shdwc@fc068610 {
1117 compatible = "atmel,at91sam9x5-shdwc";
1118 reg = <0xfc068610 0x10>;
1119 };
1120
1121 pit: timer@fc068630 {
1122 compatible = "atmel,at91sam9260-pit";
0068b2e1 1123 reg = <0xfc068630 0x10>;
7c661394
NF		 1124 interrupts = <3 IRQ_TYPE_LEVEL_HIGH 5>;
1125 clocks = <&h32ck>;
1126 };
1127
1128 watchdog@fc068640 {
1129 compatible = "atmel,at91sam9260-wdt";
1130 reg = <0xfc068640 0x10>;
1131 status = "disabled";
1132 };
1133
1134 sckc@fc068650 {
1135 compatible = "atmel,at91sam9x5-sckc";
1136 reg = <0xfc068650 0x4>;
1137
1138 slow_rc_osc: slow_rc_osc {
1139 compatible = "atmel,at91sam9x5-clk-slow-rc-osc";
1140 #clock-cells = <0>;
1141 clock-frequency = <32768>;
1142 clock-accuracy = <250000000>;
1143 atmel,startup-time-usec = <75>;
1144 };
1145
1146 slow_osc: slow_osc {
1147 compatible = "atmel,at91sam9x5-clk-slow-osc";
1148 #clock-cells = <0>;
1149 clocks = <&slow_xtal>;
1150 atmel,startup-time-usec = <1200000>;
1151 };
1152
1153 clk32k: slowck {
1154 compatible = "atmel,at91sam9x5-clk-slow";
1155 #clock-cells = <0>;
1156 clocks = <&slow_rc_osc &slow_osc>;
1157 };
1158 };
1159
1160 rtc@fc0686b0 {
1161 compatible = "atmel,at91rm9200-rtc";
1162 reg = <0xfc0686b0 0x30>;
1163 interrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>;
1164 };
1165
1166 dbgu: serial@fc069000 {
1167 compatible = "atmel,at91sam9260-usart";
1168 reg = <0xfc069000 0x200>;
1169 interrupts = <2 IRQ_TYPE_LEVEL_HIGH 7>;
1170 pinctrl-names = "default";
1171 pinctrl-0 = <&pinctrl_dbgu>;
1172 clocks = <&dbgu_clk>;
1173 clock-names = "usart";
1174 status = "disabled";
1175 };
1176
1177
1178 pinctrl@fc06a000 {
1179 #address-cells = <1>;
1180 #size-cells = <1>;
1181 compatible = "atmel,at91sam9x5-pinctrl", "atmel,at91rm9200-pinctrl", "simple-bus";
1182 ranges = <0xfc06a000 0xfc06a000 0x4000>;
1183 /* WARNING: revisit as pin spec has changed */
1184 atmel,mux-mask = <
1185 /* A B C */
1186 0xffffffff 0x3ffcfe7c 0x1c010101 /* pioA */
1187 0x7fffffff 0xfffccc3a 0x3f00cc3a /* pioB */
1188 0xffffffff 0x3ff83fff 0xff00ffff /* pioC */
1189 0x00000000 0x00000000 0x00000000 /* pioD */
1190 0xffffffff 0x7fffffff 0x76fff1bf /* pioE */
1191 >;
1192
1193 pioA: gpio@fc06a000 {
1194 compatible = "atmel,at91sam9x5-gpio", "atmel,at91rm9200-gpio";
1195 reg = <0xfc06a000 0x100>;
1196 interrupts = <23 IRQ_TYPE_LEVEL_HIGH 1>;
1197 #gpio-cells = <2>;
1198 gpio-controller;
1199 interrupt-controller;
1200 #interrupt-cells = <2>;
1201 clocks = <&pioA_clk>;
1202 };
1203
1204 pioB: gpio@fc06b000 {
1205 compatible = "atmel,at91sam9x5-gpio", "atmel,at91rm9200-gpio";
1206 reg = <0xfc06b000 0x100>;
1207 interrupts = <24 IRQ_TYPE_LEVEL_HIGH 1>;
1208 #gpio-cells = <2>;
1209 gpio-controller;
1210 interrupt-controller;
1211 #interrupt-cells = <2>;
1212 clocks = <&pioB_clk>;
1213 };
1214
1215 pioC: gpio@fc06c000 {
1216 compatible = "atmel,at91sam9x5-gpio", "atmel,at91rm9200-gpio";
1217 reg = <0xfc06c000 0x100>;
1218 interrupts = <25 IRQ_TYPE_LEVEL_HIGH 1>;
1219 #gpio-cells = <2>;
1220 gpio-controller;
1221 interrupt-controller;
1222 #interrupt-cells = <2>;
1223 clocks = <&pioC_clk>;
1224 };
1225
1de77b7f
LD		 1226 pioD: gpio@fc068000 {
1227 compatible = "atmel,at91sam9x5-gpio", "atmel,at91rm9200-gpio";
1228 reg = <0xfc068000 0x100>;
1229 interrupts = <5 IRQ_TYPE_LEVEL_HIGH 1>;
1230 #gpio-cells = <2>;
1231 gpio-controller;
1232 interrupt-controller;
1233 #interrupt-cells = <2>;
1234 clocks = <&pioD_clk>;
1235 status = "disabled";
1236 };
1237
7c661394
NF		 1238 pioE: gpio@fc06d000 {
1239 compatible = "atmel,at91sam9x5-gpio", "atmel,at91rm9200-gpio";
1240 reg = <0xfc06d000 0x100>;
1241 interrupts = <26 IRQ_TYPE_LEVEL_HIGH 1>;
1242 #gpio-cells = <2>;
1243 gpio-controller;
1244 interrupt-controller;
1245 #interrupt-cells = <2>;
1246 clocks = <&pioE_clk>;
1247 };
1248
1249 /* pinctrl pin settings */
1250 adc0 {
1251 pinctrl_adc0_adtrg: adc0_adtrg {
1252 atmel,pins =
1253 <AT91_PIOE 31 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* conflicts with USBA_VBUS */
1254 };
1255 pinctrl_adc0_ad0: adc0_ad0 {
1256 atmel,pins =
1257 <AT91_PIOC 27 AT91_PERIPH_A AT91_PINCTRL_NONE>;
1258 };
1259 pinctrl_adc0_ad1: adc0_ad1 {
1260 atmel,pins =
1261 <AT91_PIOC 28 AT91_PERIPH_A AT91_PINCTRL_NONE>;
1262 };
1263 pinctrl_adc0_ad2: adc0_ad2 {
1264 atmel,pins =
1265 <AT91_PIOC 29 AT91_PERIPH_A AT91_PINCTRL_NONE>;
1266 };
1267 pinctrl_adc0_ad3: adc0_ad3 {
1268 atmel,pins =
1269 <AT91_PIOC 30 AT91_PERIPH_A AT91_PINCTRL_NONE>;
1270 };
1271 pinctrl_adc0_ad4: adc0_ad4 {
1272 atmel,pins =
1273 <AT91_PIOC 31 AT91_PERIPH_A AT91_PINCTRL_NONE>;
1274 };
1275 };
1276
1277 dbgu {
1278 pinctrl_dbgu: dbgu-0 {
1279 atmel,pins =
1280 <AT91_PIOB 24 AT91_PERIPH_A AT91_PINCTRL_NONE>, /* conflicts with D14 and TDI */
1281 <AT91_PIOB 25 AT91_PERIPH_A AT91_PINCTRL_PULL_UP>; /* conflicts with D15 and TDO */
1282 };
1283 };
1284
1285 i2c0 {
1286 pinctrl_i2c0: i2c0-0 {
1287 atmel,pins =
1288 <AT91_PIOA 30 AT91_PERIPH_A AT91_PINCTRL_NONE
1289 AT91_PIOA 31 AT91_PERIPH_A AT91_PINCTRL_NONE>;
1290 };
1291 };
1292
4cc7cdf3
PA		 1293 i2c1 {
1294 pinctrl_i2c1: i2c1-0 {
1295 atmel,pins =
1296 <AT91_PIOE 29 AT91_PERIPH_C AT91_PINCTRL_NONE /* TWD1, conflicts with UART0 RX and DIBP */
1297 AT91_PIOE 30 AT91_PERIPH_C AT91_PINCTRL_NONE>; /* TWCK1, conflicts with UART0 TX and DIBN */
1298 };
1299 };
1300
7c661394
NF		 1301 i2c2 {
1302 pinctrl_i2c2: i2c2-0 {
1303 atmel,pins =
1304 <AT91_PIOB 29 AT91_PERIPH_A AT91_PINCTRL_NONE /* TWD2, conflicts with RD0 and PWML1 */
1305 AT91_PIOB 30 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* TWCK2, conflicts with RF0 */
1306 };
1307 };
1308
1309 macb0 {
1310 pinctrl_macb0_rmii: macb0_rmii-0 {
1311 atmel,pins =
1312 <AT91_PIOB 12 AT91_PERIPH_A AT91_PINCTRL_NONE /* G0_TX0 */
1313 AT91_PIOB 13 AT91_PERIPH_A AT91_PINCTRL_NONE /* G0_TX1 */
1314 AT91_PIOB 8 AT91_PERIPH_A AT91_PINCTRL_NONE /* G0_RX0 */
1315 AT91_PIOB 9 AT91_PERIPH_A AT91_PINCTRL_NONE /* G0_RX1 */
1316 AT91_PIOB 6 AT91_PERIPH_A AT91_PINCTRL_NONE /* G0_RXDV */
1317 AT91_PIOB 7 AT91_PERIPH_A AT91_PINCTRL_NONE /* G0_RXER */
1318 AT91_PIOB 2 AT91_PERIPH_A AT91_PINCTRL_NONE /* G0_TXEN */
1319 AT91_PIOB 0 AT91_PERIPH_A AT91_PINCTRL_NONE /* G0_TXCK */
1320 AT91_PIOB 16 AT91_PERIPH_A AT91_PINCTRL_NONE /* G0_MDC */
1321 AT91_PIOB 17 AT91_PERIPH_A AT91_PINCTRL_NONE /* G0_MDIO */
1322 >;
1323 };
1324 };
1325
1326 mmc0 {
1327 pinctrl_mmc0_clk_cmd_dat0: mmc0_clk_cmd_dat0 {
1328 atmel,pins =
1329 <AT91_PIOC 4 AT91_PERIPH_B AT91_PINCTRL_NONE /* MCI0_CK, conflict with PCK1(ISI_MCK) */
1330 AT91_PIOC 5 AT91_PERIPH_B AT91_PINCTRL_PULL_UP /* MCI0_CDB, conflict with NAND_D0 */
1331 AT91_PIOC 6 AT91_PERIPH_B AT91_PINCTRL_PULL_UP /* MCI0_DB0, conflict with NAND_D1 */
1332 >;
1333 };
1334 pinctrl_mmc0_dat1_3: mmc0_dat1_3 {
1335 atmel,pins =
1336 <AT91_PIOC 7 AT91_PERIPH_B AT91_PINCTRL_PULL_UP /* MCI0_DB1, conflict with NAND_D2 */
1337 AT91_PIOC 8 AT91_PERIPH_B AT91_PINCTRL_PULL_UP /* MCI0_DB2, conflict with NAND_D3 */
1338 AT91_PIOC 9 AT91_PERIPH_B AT91_PINCTRL_PULL_UP /* MCI0_DB3, conflict with NAND_D4 */
1339 >;
1340 };
1341 };
1342
1343 mmc1 {
1344 pinctrl_mmc1_clk_cmd_dat0: mmc1_clk_cmd_dat0 {
1345 atmel,pins =
1346 <AT91_PIOE 18 AT91_PERIPH_C AT91_PINCTRL_NONE /* MCI1_CK */
1347 AT91_PIOE 19 AT91_PERIPH_C AT91_PINCTRL_PULL_UP /* MCI1_CDA */
1348 AT91_PIOE 20 AT91_PERIPH_C AT91_PINCTRL_PULL_UP /* MCI1_DA0 */
1349 >;
1350 };
1351 pinctrl_mmc1_dat1_3: mmc1_dat1_3 {
1352 atmel,pins =
1353 <AT91_PIOE 21 AT91_PERIPH_C AT91_PINCTRL_PULL_UP /* MCI1_DA1 */
1354 AT91_PIOE 22 AT91_PERIPH_C AT91_PINCTRL_PULL_UP /* MCI1_DA2 */
1355 AT91_PIOE 23 AT91_PERIPH_C AT91_PINCTRL_PULL_UP /* MCI1_DA3 */
1356 >;
1357 };
1358 };
1359
1360 nand0 {
1361 pinctrl_nand: nand-0 {
1362 atmel,pins =
1363 <AT91_PIOC 13 AT91_PERIPH_A AT91_PINCTRL_NONE /* PC13 periph A Read Enable */
1364 AT91_PIOC 14 AT91_PERIPH_A AT91_PINCTRL_NONE /* PC14 periph A Write Enable */
1365
1366 AT91_PIOC 17 AT91_PERIPH_A AT91_PINCTRL_PULL_UP /* PC17 ALE */
1367 AT91_PIOC 18 AT91_PERIPH_A AT91_PINCTRL_PULL_UP /* PC18 CLE */
1368
1369 AT91_PIOC 15 AT91_PERIPH_A AT91_PINCTRL_PULL_UP /* PC15 NCS3/Chip Enable */
1370 AT91_PIOC 16 AT91_PERIPH_A AT91_PINCTRL_PULL_UP /* PC16 NANDRDY */
1371 AT91_PIOC 5 AT91_PERIPH_A AT91_PINCTRL_NONE /* PC5 Data bit 0 */
1372 AT91_PIOC 6 AT91_PERIPH_A AT91_PINCTRL_NONE /* PC6 Data bit 1 */
1373 AT91_PIOC 7 AT91_PERIPH_A AT91_PINCTRL_NONE /* PC7 Data bit 2 */
1374 AT91_PIOC 8 AT91_PERIPH_A AT91_PINCTRL_NONE /* PC8 Data bit 3 */
1375 AT91_PIOC 9 AT91_PERIPH_A AT91_PINCTRL_NONE /* PC9 Data bit 4 */
1376 AT91_PIOC 10 AT91_PERIPH_A AT91_PINCTRL_NONE /* PC10 Data bit 5 */
1377 AT91_PIOC 11 AT91_PERIPH_A AT91_PINCTRL_NONE /* PC11 periph A Data bit 6 */
1378 AT91_PIOC 12 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PC12 periph A Data bit 7 */
1379 };
1380 };
1381
1382 spi0 {
1383 pinctrl_spi0: spi0-0 {
1384 atmel,pins =
1385 <AT91_PIOC 0 AT91_PERIPH_A AT91_PINCTRL_NONE /* SPI0_MISO */
1386 AT91_PIOC 1 AT91_PERIPH_A AT91_PINCTRL_NONE /* SPI0_MOSI */
1387 AT91_PIOC 2 AT91_PERIPH_A AT91_PINCTRL_NONE /* SPI0_SPCK */
1388 >;
1389 };
1390 };
1391
0697edd7
BS		 1392 ssc0 {
1393 pinctrl_ssc0_tx: ssc0_tx {
1394 atmel,pins =
1395 <AT91_PIOB 27 AT91_PERIPH_B AT91_PINCTRL_NONE /* TK0 */
1396 AT91_PIOB 31 AT91_PERIPH_B AT91_PINCTRL_NONE /* TF0 */
1397 AT91_PIOB 28 AT91_PERIPH_B AT91_PINCTRL_NONE>; /* TD0 */
1398 };
1399
1400 pinctrl_ssc0_rx: ssc0_rx {
1401 atmel,pins =
1402 <AT91_PIOB 26 AT91_PERIPH_B AT91_PINCTRL_NONE /* RK0 */
1403 AT91_PIOB 30 AT91_PERIPH_B AT91_PINCTRL_NONE /* RF0 */
1404 AT91_PIOB 29 AT91_PERIPH_B AT91_PINCTRL_NONE>; /* RD0 */
1405 };
1406 };
1407
1408 ssc1 {
1409 pinctrl_ssc1_tx: ssc1_tx {
1410 atmel,pins =
1411 <AT91_PIOC 19 AT91_PERIPH_B AT91_PINCTRL_NONE /* TK1 */
1412 AT91_PIOC 20 AT91_PERIPH_B AT91_PINCTRL_NONE /* TF1 */
1413 AT91_PIOC 21 AT91_PERIPH_B AT91_PINCTRL_NONE>; /* TD1 */
1414 };
1415
1416 pinctrl_ssc1_rx: ssc1_rx {
1417 atmel,pins =
1418 <AT91_PIOC 24 AT91_PERIPH_B AT91_PINCTRL_NONE /* RK1 */
1419 AT91_PIOC 22 AT91_PERIPH_B AT91_PINCTRL_NONE /* RF1 */
1420 AT91_PIOC 23 AT91_PERIPH_B AT91_PINCTRL_NONE>; /* RD1 */
1421 };
1422 };
1423
7c661394
NF		 1424 usart2 {
1425 pinctrl_usart2: usart2-0 {
1426 atmel,pins =
1427 <AT91_PIOB 4 AT91_PERIPH_B AT91_PINCTRL_NONE /* RXD - conflicts with G0_CRS, ISI_HSYNC */
1428 AT91_PIOB 5 AT91_PERIPH_B AT91_PINCTRL_PULL_UP /* TXD - conflicts with G0_COL, PCK2 */
1429 >;
1430 };
1431 pinctrl_usart2_rts: usart2_rts-0 {
1432 atmel,pins = <AT91_PIOB 11 AT91_PERIPH_B AT91_PINCTRL_NONE>; /* conflicts with G0_RX3, PWMH1 */
1433 };
1434 pinctrl_usart2_cts: usart2_cts-0 {
1435 atmel,pins = <AT91_PIOB 3 AT91_PERIPH_B AT91_PINCTRL_NONE>; /* conflicts with G0_TXER, ISI_VSYNC */
1436 };
1437 };
1438
1439 usart3 {
1440 pinctrl_usart3: usart3-0 {
1441 atmel,pins =
1442 <AT91_PIOE 16 AT91_PERIPH_B AT91_PINCTRL_NONE /* RXD */
1443 AT91_PIOE 17 AT91_PERIPH_B AT91_PINCTRL_PULL_UP /* TXD */
1444 >;
1445 };
1446 };
1447
1448 usart4 {
1449 pinctrl_usart4: usart4-0 {
1450 atmel,pins =
1451 <AT91_PIOE 26 AT91_PERIPH_B AT91_PINCTRL_NONE /* RXD */
1452 AT91_PIOE 27 AT91_PERIPH_B AT91_PINCTRL_PULL_UP /* TXD */
1453 >;
1454 };
1455 pinctrl_usart4_rts: usart4_rts-0 {
1456 atmel,pins = <AT91_PIOE 28 AT91_PERIPH_B AT91_PINCTRL_NONE>; /* conflicts with NWAIT, A19 */
1457 };
1458 pinctrl_usart4_cts: usart4_cts-0 {
1459 atmel,pins = <AT91_PIOE 0 AT91_PERIPH_C AT91_PINCTRL_NONE>; /* conflicts with A0/NBS0, MCI0_CDB */
1460 };
1461 };
1462 };
1463
1464 aic: interrupt-controller@fc06e000 {
1465 #interrupt-cells = <3>;
1466 compatible = "atmel,sama5d4-aic";
1467 interrupt-controller;
1468 reg = <0xfc06e000 0x200>;
1469 atmel,external-irqs = <56>;
1470 };
1471 };
1472 };
1473};
Linux 6.x block layer and io_uring tree(s)