[linux-2.6-block.git] / arch / arm / boot / dts / sama5d2.dtsi

/*
 * sama5d2.dtsi - Device Tree Include file for SAMA5D2 family SoC
 *
 *  Copyright (C) 2015 Atmel,
 *                2015 Ludovic Desroches <ludovic.desroches@atmel.com>
 *
 * This file is dual-licensed: you can use it either under the terms
 * of the GPL or the X11 license, at your option. Note that this dual
 * licensing only applies to this file, and not this project as a
 * whole.
 *
 *  a) This file is free software; you can redistribute it and/or
 *     modify it under the terms of the GNU General Public License as
 *     published by the Free Software Foundation; either version 2 of the
 *     License, or (at your option) any later version.
 *
 *     This file is distributed in the hope that it will be useful,
 *     but WITHOUT ANY WARRANTY; without even the implied warranty of
 *     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 *     GNU General Public License for more details.
 *
 * Or, alternatively,
 *
 *  b) Permission is hereby granted, free of charge, to any person
 *     obtaining a copy of this software and associated documentation
 *     files (the "Software"), to deal in the Software without
 *     restriction, including without limitation the rights to use,
 *     copy, modify, merge, publish, distribute, sublicense, and/or
 *     sell copies of the Software, and to permit persons to whom the
 *     Software is furnished to do so, subject to the following
 *     conditions:
 *
 *     The above copyright notice and this permission notice shall be
 *     included in all copies or substantial portions of the Software.
 *
 *     THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
 *     EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
 *     OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
 *     NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
 *     HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
 *     WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
 *     FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
 *     OTHER DEALINGS IN THE SOFTWARE.
 */

#include "skeleton.dtsi"
#include <dt-bindings/dma/at91.h>
#include <dt-bindings/interrupt-controller/irq.h>
#include <dt-bindings/clock/at91.h>

/ {
	model = "Atmel SAMA5D2 family SoC";
	compatible = "atmel,sama5d2";
	interrupt-parent = <&aic>;

	aliases {
		serial0 = &uart1;
		serial1 = &uart3;
		tcb0 = &tcb0;
		tcb1 = &tcb1;
	};

	cpus {
		#address-cells = <1>;
		#size-cells = <0>;

		cpu@0 {
			device_type = "cpu";
			compatible = "arm,cortex-a5";
			reg = <0>;
			next-level-cache = <&L2>;
		};
	};

	memory {
		reg = <0x20000000 0x20000000>;
	};

	clocks {
		slow_xtal: slow_xtal {
			compatible = "fixed-clock";
			#clock-cells = <0>;
			clock-frequency = <0>;
		};

		main_xtal: main_xtal {
			compatible = "fixed-clock";
			#clock-cells = <0>;
			clock-frequency = <0>;
		};

		adc_op_clk: adc_op_clk{
			compatible = "fixed-clock";
			#clock-cells = <0>;
			clock-frequency = <1000000>;
		};
	};

	ns_sram: sram@00200000 {
		compatible = "mmio-sram";
		reg = <0x00200000 0x20000>;
	};

	ahb {
		compatible = "simple-bus";
		#address-cells = <1>;
		#size-cells = <1>;
		ranges;

		usb0: gadget@00300000 {
			#address-cells = <1>;
			#size-cells = <0>;
			compatible = "atmel,sama5d3-udc";
			reg = <0x00300000 0x100000
			       0xfc02c000 0x400>;
			interrupts = <42 IRQ_TYPE_LEVEL_HIGH 2>;
			clocks = <&udphs_clk>, <&utmi>;
			clock-names = "pclk", "hclk";
			status = "disabled";

			ep0 {
				reg = <0>;
				atmel,fifo-size = <64>;
				atmel,nb-banks = <1>;
			};

			ep1 {
				reg = <1>;
				atmel,fifo-size = <1024>;
				atmel,nb-banks = <3>;
				atmel,can-dma;
				atmel,can-isoc;
			};

			ep2 {
				reg = <2>;
				atmel,fifo-size = <1024>;
				atmel,nb-banks = <3>;
				atmel,can-dma;
				atmel,can-isoc;
			};

			ep3 {
				reg = <3>;
				atmel,fifo-size = <1024>;
				atmel,nb-banks = <2>;
				atmel,can-dma;
				atmel,can-isoc;
			};

			ep4 {
				reg = <4>;
				atmel,fifo-size = <1024>;
				atmel,nb-banks = <2>;
				atmel,can-dma;
				atmel,can-isoc;
			};

			ep5 {
				reg = <5>;
				atmel,fifo-size = <1024>;
				atmel,nb-banks = <2>;
				atmel,can-dma;
				atmel,can-isoc;
			};

			ep6 {
				reg = <6>;
				atmel,fifo-size = <1024>;
				atmel,nb-banks = <2>;
				atmel,can-dma;
				atmel,can-isoc;
			};

			ep7 {
				reg = <7>;
				atmel,fifo-size = <1024>;
				atmel,nb-banks = <2>;
				atmel,can-dma;
				atmel,can-isoc;
			};

			ep8 {
				reg = <8>;
				atmel,fifo-size = <1024>;
				atmel,nb-banks = <2>;
				atmel,can-isoc;
			};

			ep9 {
				reg = <9>;
				atmel,fifo-size = <1024>;
				atmel,nb-banks = <2>;
				atmel,can-isoc;
			};

			ep10 {
				reg = <10>;
				atmel,fifo-size = <1024>;
				atmel,nb-banks = <2>;
				atmel,can-isoc;
			};

			ep11 {
				reg = <11>;
				atmel,fifo-size = <1024>;
				atmel,nb-banks = <2>;
				atmel,can-isoc;
			};

			ep12 {
				reg = <12>;
				atmel,fifo-size = <1024>;
				atmel,nb-banks = <2>;
				atmel,can-isoc;
			};

			ep13 {
				reg = <13>;
				atmel,fifo-size = <1024>;
				atmel,nb-banks = <2>;
				atmel,can-isoc;
			};

			ep14 {
				reg = <14>;
				atmel,fifo-size = <1024>;
				atmel,nb-banks = <2>;
				atmel,can-isoc;
			};

			ep15 {
				reg = <15>;
				atmel,fifo-size = <1024>;
				atmel,nb-banks = <2>;
				atmel,can-isoc;
			};
		};

		usb1: ohci@00400000 {
			compatible = "atmel,at91rm9200-ohci", "usb-ohci";
			reg = <0x00400000 0x100000>;
			interrupts = <41 IRQ_TYPE_LEVEL_HIGH 2>;
			clocks = <&uhphs_clk>, <&uhphs_clk>, <&uhpck>;
			clock-names = "ohci_clk", "hclk", "uhpck";
			status = "disabled";
		};

		usb2: ehci@00500000 {
			compatible = "atmel,at91sam9g45-ehci", "usb-ehci";
			reg = <0x00500000 0x100000>;
			interrupts = <41 IRQ_TYPE_LEVEL_HIGH 2>;
			clocks = <&utmi>, <&uhphs_clk>;
			clock-names = "usb_clk", "ehci_clk";
			status = "disabled";
		};

		L2: cache-controller@00a00000 {
			compatible = "arm,pl310-cache";
			reg = <0x00a00000 0x1000>;
			interrupts = <63 IRQ_TYPE_LEVEL_HIGH 4>;
			cache-unified;
			cache-level = <2>;
		};

		apb {
			compatible = "simple-bus";
			#address-cells = <1>;
			#size-cells = <1>;
			ranges;

			ramc0: ramc@f000c000 {
				compatible = "atmel,sama5d3-ddramc";
				reg = <0xf000c000 0x200>;
				clocks = <&ddrck>, <&mpddr_clk>;
				clock-names = "ddrck", "mpddr";
			};

			dma0: dma-controller@f0010000 {
				compatible = "atmel,sama5d4-dma";
				reg = <0xf0010000 0x1000>;
				interrupts = <6 IRQ_TYPE_LEVEL_HIGH 0>;
				#dma-cells = <1>;
				clocks = <&dma0_clk>;
				clock-names = "dma_clk";
			};

			pmc: pmc@f0014000 {
				compatible = "atmel,sama5d2-pmc";
				reg = <0xf0014000 0x160>;
				interrupts = <74 IRQ_TYPE_LEVEL_HIGH 7>;
				interrupt-controller;
				#address-cells = <1>;
				#size-cells = <0>;
				#interrupt-cells = <1>;

				main_rc_osc: main_rc_osc {
					compatible = "atmel,at91sam9x5-clk-main-rc-osc";
					#clock-cells = <0>;
					interrupt-parent = <&pmc>;
					interrupts = <AT91_PMC_MOSCRCS>;
					clock-frequency = <12000000>;
					clock-accuracy = <100000000>;
				};

				main_osc: main_osc {
					compatible = "atmel,at91rm9200-clk-main-osc";
					#clock-cells = <0>;
					interrupt-parent = <&pmc>;
					interrupts = <AT91_PMC_MOSCS>;
					clocks = <&main_xtal>;
				};

				main: mainck {
					compatible = "atmel,at91sam9x5-clk-main";
					#clock-cells = <0>;
					interrupt-parent = <&pmc>;
					interrupts = <AT91_PMC_MOSCSELS>;
					clocks = <&main_rc_osc &main_osc>;
				};

				plla: pllack {
					compatible = "atmel,sama5d3-clk-pll";
					#clock-cells = <0>;
					interrupt-parent = <&pmc>;
					interrupts = <AT91_PMC_LOCKA>;
					clocks = <&main>;
					reg = <0>;
					atmel,clk-input-range = <12000000 12000000>;
					#atmel,pll-clk-output-range-cells = <4>;
					atmel,pll-clk-output-ranges = <600000000 1200000000 0 0>;
				};

				plladiv: plladivck {
					compatible = "atmel,at91sam9x5-clk-plldiv";
					#clock-cells = <0>;
					clocks = <&plla>;
				};

				utmi: utmick {
					compatible = "atmel,at91sam9x5-clk-utmi";
					#clock-cells = <0>;
					interrupt-parent = <&pmc>;
					interrupts = <AT91_PMC_LOCKU>;
					clocks = <&main>;
				};

				mck: masterck {
					compatible = "atmel,at91sam9x5-clk-master";
					#clock-cells = <0>;
					interrupt-parent = <&pmc>;
					interrupts = <AT91_PMC_MCKRDY>;
					clocks = <&clk32k>, <&main>, <&plladiv>, <&utmi>;
					atmel,clk-output-range = <124000000 166000000>;
					atmel,clk-divisors = <1 2 4 3>;
				};

				h32ck: h32mxck {
					#clock-cells = <0>;
					compatible = "atmel,sama5d4-clk-h32mx";
					clocks = <&mck>;
				};

				usb: usbck {
					compatible = "atmel,at91sam9x5-clk-usb";
					#clock-cells = <0>;
					clocks = <&plladiv>, <&utmi>;
				};

				prog: progck {
					compatible = "atmel,at91sam9x5-clk-programmable";
					#address-cells = <1>;
					#size-cells = <0>;
					interrupt-parent = <&pmc>;
					clocks = <&clk32k>, <&main>, <&plladiv>, <&utmi>, <&mck>;

					prog0: prog0 {
						#clock-cells = <0>;
						reg = <0>;
						interrupts = <AT91_PMC_PCKRDY(0)>;
					};

					prog1: prog1 {
						#clock-cells = <0>;
						reg = <1>;
						interrupts = <AT91_PMC_PCKRDY(1)>;
					};

					prog2: prog2 {
						#clock-cells = <0>;
						reg = <2>;
						interrupts = <AT91_PMC_PCKRDY(2)>;
					};
				};

				systemck {
					compatible = "atmel,at91rm9200-clk-system";
					#address-cells = <1>;
					#size-cells = <0>;

					ddrck: ddrck {
						#clock-cells = <0>;
						reg = <2>;
						clocks = <&mck>;
					};

					lcdck: lcdck {
						#clock-cells = <0>;
						reg = <3>;
						clocks = <&mck>;
					};

					uhpck: uhpck {
						#clock-cells = <0>;
						reg = <6>;
						clocks = <&usb>;
					};

					udpck: udpck {
						#clock-cells = <0>;
						reg = <7>;
						clocks = <&usb>;
					};

					pck0: pck0 {
						#clock-cells = <0>;
						reg = <8>;
						clocks = <&prog0>;
					};

					pck1: pck1 {
						#clock-cells = <0>;
						reg = <9>;
						clocks = <&prog1>;
					};

					pck2: pck2 {
						#clock-cells = <0>;
						reg = <10>;
						clocks = <&prog2>;
					};

					iscck: iscck {
						#clock-cells = <0>;
						reg = <18>;
						clocks = <&mck>;
					};
				};

				periph32ck {
					compatible = "atmel,at91sam9x5-clk-peripheral";
					#address-cells = <1>;
					#size-cells = <0>;
					clocks = <&h32ck>;

					macb0_clk: macb0_clk {
						#clock-cells = <0>;
						reg = <5>;
						atmel,clk-output-range = <0 83000000>;
					};

					tdes_clk: tdes_clk {
						#clock-cells = <0>;
						reg = <11>;
						atmel,clk-output-range = <0 83000000>;
					};

					matrix1_clk: matrix1_clk {
						#clock-cells = <0>;
						reg = <14>;
					};

					hsmc_clk: hsmc_clk {
						#clock-cells = <0>;
						reg = <17>;
					};

					pioA_clk: pioA_clk {
						#clock-cells = <0>;
						reg = <18>;
						atmel,clk-output-range = <0 83000000>;
					};

					flx0_clk: flx0_clk {
						#clock-cells = <0>;
						reg = <19>;
						atmel,clk-output-range = <0 83000000>;
					};

					flx1_clk: flx1_clk {
						#clock-cells = <0>;
						reg = <20>;
						atmel,clk-output-range = <0 83000000>;
					};

					flx2_clk: flx2_clk {
						#clock-cells = <0>;
						reg = <21>;
						atmel,clk-output-range = <0 83000000>;
					};

					flx3_clk: flx3_clk {
						#clock-cells = <0>;
						reg = <22>;
						atmel,clk-output-range = <0 83000000>;
					};

					flx4_clk: flx4_clk {
						#clock-cells = <0>;
						reg = <23>;
						atmel,clk-output-range = <0 83000000>;
					};

					uart0_clk: uart0_clk {
						#clock-cells = <0>;
						reg = <24>;
						atmel,clk-output-range = <0 83000000>;
					};

					uart1_clk: uart1_clk {
						#clock-cells = <0>;
						reg = <25>;
						atmel,clk-output-range = <0 83000000>;
					};

					uart2_clk: uart2_clk {
						#clock-cells = <0>;
						reg = <26>;
						atmel,clk-output-range = <0 83000000>;
					};

					uart3_clk: uart3_clk {
						#clock-cells = <0>;
						reg = <27>;
						atmel,clk-output-range = <0 83000000>;
					};

					uart4_clk: uart4_clk {
						#clock-cells = <0>;
						reg = <28>;
						atmel,clk-output-range = <0 83000000>;
					};

					twi0_clk: twi0_clk {
						reg = <29>;
						#clock-cells = <0>;
						atmel,clk-output-range = <0 83000000>;
					};

					twi1_clk: twi1_clk {
						#clock-cells = <0>;
						reg = <30>;
						atmel,clk-output-range = <0 83000000>;
					};

					spi0_clk: spi0_clk {
						#clock-cells = <0>;
						reg = <33>;
						atmel,clk-output-range = <0 83000000>;
					};

					spi1_clk: spi1_clk {
						#clock-cells = <0>;
						reg = <34>;
						atmel,clk-output-range = <0 83000000>;
					};

					tcb0_clk: tcb0_clk {
						#clock-cells = <0>;
						reg = <35>;
						atmel,clk-output-range = <0 83000000>;
					};

					tcb1_clk: tcb1_clk {
						#clock-cells = <0>;
						reg = <36>;
						atmel,clk-output-range = <0 83000000>;
					};

					pwm_clk: pwm_clk {
						#clock-cells = <0>;
						reg = <38>;
						atmel,clk-output-range = <0 83000000>;
					};

					adc_clk: adc_clk {
						#clock-cells = <0>;
						reg = <40>;
						atmel,clk-output-range = <0 83000000>;
					};

					uhphs_clk: uhphs_clk {
						#clock-cells = <0>;
						reg = <41>;
						atmel,clk-output-range = <0 83000000>;
					};

					udphs_clk: udphs_clk {
						#clock-cells = <0>;
						reg = <42>;
						atmel,clk-output-range = <0 83000000>;
					};

					ssc0_clk: ssc0_clk {
						#clock-cells = <0>;
						reg = <43>;
						atmel,clk-output-range = <0 83000000>;
					};

					ssc1_clk: ssc1_clk {
						#clock-cells = <0>;
						reg = <44>;
						atmel,clk-output-range = <0 83000000>;
					};

					trng_clk: trng_clk {
						#clock-cells = <0>;
						reg = <47>;
						atmel,clk-output-range = <0 83000000>;
					};

					classd_clk: classd_clk {
						#clock-cells = <0>;
						reg = <59>;
						atmel,clk-output-range = <0 83000000>;
					};
				};

				periph64ck {
					compatible = "atmel,at91sam9x5-clk-peripheral";
					#address-cells = <1>;
					#size-cells = <0>;
					clocks = <&mck>;

					dma0_clk: dma0_clk {
						#clock-cells = <0>;
						reg = <6>;
					};

					dma1_clk: dma1_clk {
						#clock-cells = <0>;
						reg = <7>;
					};

					aes_clk: aes_clk {
						#clock-cells = <0>;
						reg = <9>;
					};

					aesb_clk: aesb_clk {
						#clock-cells = <0>;
						reg = <10>;
					};

					sha_clk: sha_clk {
						#clock-cells = <0>;
						reg = <12>;
					};

					mpddr_clk: mpddr_clk {
						#clock-cells = <0>;
						reg = <13>;
					};

					matrix0_clk: matrix0_clk {
						#clock-cells = <0>;
						reg = <15>;
					};

					sdmmc0_hclk: sdmmc0_hclk {
						#clock-cells = <0>;
						reg = <31>;
					};

					sdmmc1_hclk: sdmmc1_hclk {
						#clock-cells = <0>;
						reg = <32>;
					};

					lcdc_clk: lcdc_clk {
						#clock-cells = <0>;
						reg = <45>;
					};

					isc_clk: isc_clk {
						#clock-cells = <0>;
						reg = <46>;
					};

					qspi0_clk: qspi0_clk {
						#clock-cells = <0>;
						reg = <52>;
					};

					qspi1_clk: qspi1_clk {
						#clock-cells = <0>;
						reg = <53>;
					};
				};
			};

			sha@f0028000 {
				compatible = "atmel,at91sam9g46-sha";
				reg = <0xf0028000 0x100>;
				interrupts = <12 IRQ_TYPE_LEVEL_HIGH 0>;
				dmas = <&dma0
					(AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) |
					 AT91_XDMAC_DT_PERID(30))>;
				dma-names = "tx";
				clocks = <&sha_clk>;
				clock-names = "sha_clk";
				status = "disabled";
			};

			aes@f002c000 {
				compatible = "atmel,at91sam9g46-aes";
				reg = <0xf002c000 0x100>;
				interrupts = <9 IRQ_TYPE_LEVEL_HIGH 0>;
				dmas = <&dma0
					(AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) |
					 AT91_XDMAC_DT_PERID(26))>,
				       <&dma0
					(AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) |
					 AT91_XDMAC_DT_PERID(27))>;
				dma-names = "tx", "rx";
				clocks = <&aes_clk>;
				clock-names = "aes_clk";
				status = "disabled";
			};

			spi0: spi@f8000000 {
				compatible = "atmel,at91rm9200-spi";
				reg = <0xf8000000 0x100>;
				interrupts = <33 IRQ_TYPE_LEVEL_HIGH 7>;
				dmas = <&dma0
					(AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) |
					 AT91_XDMAC_DT_PERID(6))>,
				       <&dma0
					(AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) |
					 AT91_XDMAC_DT_PERID(7))>;
				dma-names = "tx", "rx";
				clocks = <&spi0_clk>;
				clock-names = "spi_clk";
				atmel,fifo-size = <16>;
				#address-cells = <1>;
				#size-cells = <0>;
				status = "disabled";
			};

			macb0: ethernet@f8008000 {
				compatible = "atmel,sama5d2-gem";
				reg = <0xf8008000 0x1000>;
				interrupts = <5  IRQ_TYPE_LEVEL_HIGH 3		/* Queue 0 */
					      66 IRQ_TYPE_LEVEL_HIGH 3          /* Queue 1 */
					      67 IRQ_TYPE_LEVEL_HIGH 3>;        /* Queue 2 */
				#address-cells = <1>;
				#size-cells = <0>;
				clocks = <&macb0_clk>, <&macb0_clk>;
				clock-names = "hclk", "pclk";
				status = "disabled";
			};

			tcb0: timer@f800c000 {
				compatible = "atmel,at91sam9x5-tcb";
				reg = <0xf800c000 0x100>;
				interrupts = <35 IRQ_TYPE_LEVEL_HIGH 0>;
				clocks = <&tcb0_clk>, <&clk32k>;
				clock-names = "t0_clk", "slow_clk";
			};

			tcb1: timer@f8010000 {
				compatible = "atmel,at91sam9x5-tcb";
				reg = <0xf8010000 0x100>;
				interrupts = <36 IRQ_TYPE_LEVEL_HIGH 0>;
				clocks = <&tcb1_clk>, <&clk32k>;
				clock-names = "t0_clk", "slow_clk";
			};

			uart0: serial@f801c000 {
				compatible = "atmel,at91sam9260-usart";
				reg = <0xf801c000 0x100>;
				interrupts = <24 IRQ_TYPE_LEVEL_HIGH 7>;
				clocks = <&uart0_clk>;
				clock-names = "usart";
				status = "disabled";
			};

			uart1: serial@f8020000 {
				compatible = "atmel,at91sam9260-usart";
				reg = <0xf8020000 0x100>;
				interrupts = <25 IRQ_TYPE_LEVEL_HIGH 7>;
				clocks = <&uart1_clk>;
				clock-names = "usart";
				status = "disabled";
			};

			uart2: serial@f8024000 {
				compatible = "atmel,at91sam9260-usart";
				reg = <0xf8024000 0x100>;
				interrupts = <26 IRQ_TYPE_LEVEL_HIGH 7>;
				clocks = <&uart2_clk>;
				clock-names = "usart";
				status = "disabled";
			};

			i2c0: i2c@f8028000 {
				compatible = "atmel,sama5d2-i2c";
				reg = <0xf8028000 0x100>;
				interrupts = <29 IRQ_TYPE_LEVEL_HIGH 7>;
				dmas = <&dma0
					(AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) |
					 AT91_XDMAC_DT_PERID(0))>,
				       <&dma0
					(AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) |
					 AT91_XDMAC_DT_PERID(1))>;
				dma-names = "tx", "rx";
				#address-cells = <1>;
				#size-cells = <0>;
				clocks = <&twi0_clk>;
				status = "disabled";
			};

			pit: timer@f8048030 {
				compatible = "atmel,at91sam9260-pit";
				reg = <0xf8048030 0x10>;
				interrupts = <3 IRQ_TYPE_LEVEL_HIGH 5>;
				clocks = <&h32ck>;
			};

			sckc@f8048050 {
				compatible = "atmel,at91sam9x5-sckc";
				reg = <0xf8048050 0x4>;

				slow_rc_osc: slow_rc_osc {
					compatible = "atmel,at91sam9x5-clk-slow-rc-osc";
					#clock-cells = <0>;
					clock-frequency = <32768>;
					clock-accuracy = <250000000>;
					atmel,startup-time-usec = <75>;
				};

				slow_osc: slow_osc {
					compatible = "atmel,at91sam9x5-clk-slow-osc";
					#clock-cells = <0>;
					clocks = <&slow_xtal>;
					atmel,startup-time-usec = <1200000>;
				};

				clk32k: slowck {
					compatible = "atmel,at91sam9x5-clk-slow";
					#clock-cells = <0>;
					clocks = <&slow_rc_osc &slow_osc>;
				};
			};

			rtc@f80480b0 {
				compatible = "atmel,at91rm9200-rtc";
				reg = <0xf80480b0 0x30>;
				interrupts = <74 IRQ_TYPE_LEVEL_HIGH 7>;
				clocks = <&clk32k>;
			};

			spi1: spi@fc000000 {
				compatible = "atmel,at91rm9200-spi";
				reg = <0xfc000000 0x100>;
				interrupts = <34 IRQ_TYPE_LEVEL_HIGH 7>;
				dmas = <&dma0
					(AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) |
					 AT91_XDMAC_DT_PERID(8))>,
				       <&dma0
					(AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) |
					 AT91_XDMAC_DT_PERID(9))>;
				dma-names = "tx", "rx";
				clocks = <&spi1_clk>;
				clock-names = "spi_clk";
				atmel,fifo-size = <16>;
				#address-cells = <1>;
				#size-cells = <0>;
				status = "disabled";
			};

			uart3: serial@fc008000 {
				compatible = "atmel,at91sam9260-usart";
				reg = <0xfc008000 0x100>;
				interrupts = <27 IRQ_TYPE_LEVEL_HIGH 7>;
				clocks = <&uart3_clk>;
				clock-names = "usart";
				status = "disabled";
			};

			uart4: serial@fc00c000 {
				compatible = "atmel,at91sam9260-usart";
				reg = <0xfc00c000 0x100>;
				interrupts = <28 IRQ_TYPE_LEVEL_HIGH 7>;
				clocks = <&uart4_clk>;
				clock-names = "usart";
				status = "disabled";
			};

			aic: interrupt-controller@fc020000 {
				#interrupt-cells = <3>;
				compatible = "atmel,sama5d2-aic";
				interrupt-controller;
				reg = <0xfc020000 0x200>;
				atmel,external-irqs = <49>;
			};

			i2c1: i2c@fc028000 {
				compatible = "atmel,sama5d2-i2c";
				reg = <0xfc028000 0x100>;
				interrupts = <30 IRQ_TYPE_LEVEL_HIGH 7>;
				dmas = <&dma0
					(AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) |
					 AT91_XDMAC_DT_PERID(2))>,
				       <&dma0
					(AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) |
					 AT91_XDMAC_DT_PERID(3))>;
				dma-names = "tx", "rx";
				#address-cells = <1>;
				#size-cells = <0>;
				clocks = <&twi1_clk>;
				status = "disabled";
			};
		};
	};
};
Commit	Line	Data
e30cf8d3 LD	1	/*
	2	* sama5d2.dtsi - Device Tree Include file for SAMA5D2 family SoC
	3	*
	4	* Copyright (C) 2015 Atmel,
	5	* 2015 Ludovic Desroches <ludovic.desroches@atmel.com>
	6	*
	7	* This file is dual-licensed: you can use it either under the terms
	8	* of the GPL or the X11 license, at your option. Note that this dual
	9	* licensing only applies to this file, and not this project as a
	10	* whole.
	11	*
	12	* a) This file is free software; you can redistribute it and/or
	13	* modify it under the terms of the GNU General Public License as
	14	* published by the Free Software Foundation; either version 2 of the
	15	* License, or (at your option) any later version.
	16	*
	17	* This file is distributed in the hope that it will be useful,
	18	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	19	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	20	* GNU General Public License for more details.
	21	*
	22	* Or, alternatively,
	23	*
	24	* b) Permission is hereby granted, free of charge, to any person
	25	* obtaining a copy of this software and associated documentation
	26	* files (the "Software"), to deal in the Software without
	27	* restriction, including without limitation the rights to use,
	28	* copy, modify, merge, publish, distribute, sublicense, and/or
	29	* sell copies of the Software, and to permit persons to whom the
	30	* Software is furnished to do so, subject to the following
	31	* conditions:
	32	*
	33	* The above copyright notice and this permission notice shall be
	34	* included in all copies or substantial portions of the Software.
	35	*
	36	* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
	37	* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
	38	* OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
	39	* NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
	40	* HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
	41	* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
	42	* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
	43	* OTHER DEALINGS IN THE SOFTWARE.
	44	*/
	45
	46	#include "skeleton.dtsi"
	47	#include <dt-bindings/dma/at91.h>
	48	#include <dt-bindings/interrupt-controller/irq.h>
	49	#include <dt-bindings/clock/at91.h>
	50
	51	/ {
	52	model = "Atmel SAMA5D2 family SoC";
	53	compatible = "atmel,sama5d2";
	54	interrupt-parent = <&aic>;
	55
	56	aliases {
	57	serial0 = &uart1;
	58	serial1 = &uart3;
	59	tcb0 = &tcb0;
	60	tcb1 = &tcb1;
	61	};
	62
	63	cpus {
	64	#address-cells = <1>;
65	#size-cells = <0>;
66
67	cpu@0 {
68	device_type = "cpu";
69	compatible = "arm,cortex-a5";
70	reg = <0>;
71	next-level-cache = <&L2>;
72	};
73	};
74
75	memory {
76	reg = <0x20000000 0x20000000>;
77	};
78
79	clocks {
80	slow_xtal: slow_xtal {
81	compatible = "fixed-clock";
82	#clock-cells = <0>;
83	clock-frequency = <0>;
84	};
85
86	main_xtal: main_xtal {
87	compatible = "fixed-clock";
88	#clock-cells = <0>;
89	clock-frequency = <0>;
90	};
91
92	adc_op_clk: adc_op_clk{
93	compatible = "fixed-clock";
94	#clock-cells = <0>;
95	clock-frequency = <1000000>;
96	};
97	};
98
99	ns_sram: sram@00200000 {
100	compatible = "mmio-sram";
101	reg = <0x00200000 0x20000>;
102	};
103
104	ahb {
105	compatible = "simple-bus";
106	#address-cells = <1>;
107	#size-cells = <1>;
108	ranges;
109
110	usb0: gadget@00300000 {
111	#address-cells = <1>;
112	#size-cells = <0>;
113	compatible = "atmel,sama5d3-udc";
114	reg = <0x00300000 0x100000
115	0xfc02c000 0x400>;
116	interrupts = <42 IRQ_TYPE_LEVEL_HIGH 2>;
117	clocks = <&udphs_clk>, <&utmi>;
118	clock-names = "pclk", "hclk";
119	status = "disabled";
120
121	ep0 {
122	reg = <0>;
123	atmel,fifo-size = <64>;
124	atmel,nb-banks = <1>;
125	};
126
127	ep1 {
128	reg = <1>;
129	atmel,fifo-size = <1024>;
130	atmel,nb-banks = <3>;
131	atmel,can-dma;
132	atmel,can-isoc;
133	};
134
135	ep2 {
136	reg = <2>;
137	atmel,fifo-size = <1024>;
138	atmel,nb-banks = <3>;
139	atmel,can-dma;
140	atmel,can-isoc;
141	};
142
143	ep3 {
144	reg = <3>;
145	atmel,fifo-size = <1024>;
146	atmel,nb-banks = <2>;
147	atmel,can-dma;
148	atmel,can-isoc;
149	};
150
151	ep4 {
152	reg = <4>;
153	atmel,fifo-size = <1024>;
154	atmel,nb-banks = <2>;
155	atmel,can-dma;
156	atmel,can-isoc;
157	};
158
159	ep5 {
160	reg = <5>;
161	atmel,fifo-size = <1024>;
162	atmel,nb-banks = <2>;
163	atmel,can-dma;
164	atmel,can-isoc;
165	};
166
167	ep6 {
168	reg = <6>;
169	atmel,fifo-size = <1024>;
170	atmel,nb-banks = <2>;
171	atmel,can-dma;
172	atmel,can-isoc;
173	};
174
175	ep7 {
176	reg = <7>;
177	atmel,fifo-size = <1024>;
178	atmel,nb-banks = <2>;
179	atmel,can-dma;
180	atmel,can-isoc;
181	};
182
183	ep8 {
184	reg = <8>;
185	atmel,fifo-size = <1024>;
186	atmel,nb-banks = <2>;
187	atmel,can-isoc;
188	};
189
190	ep9 {
191	reg = <9>;
192	atmel,fifo-size = <1024>;
193	atmel,nb-banks = <2>;
194	atmel,can-isoc;
195	};
196
197	ep10 {
198	reg = <10>;
199	atmel,fifo-size = <1024>;
200	atmel,nb-banks = <2>;
201	atmel,can-isoc;
202	};
203
204	ep11 {
205	reg = <11>;
206	atmel,fifo-size = <1024>;
207	atmel,nb-banks = <2>;
208	atmel,can-isoc;
209	};
210
211	ep12 {
212	reg = <12>;
213	atmel,fifo-size = <1024>;
214	atmel,nb-banks = <2>;
215	atmel,can-isoc;
216	};
217
218	ep13 {
219	reg = <13>;
220	atmel,fifo-size = <1024>;
221	atmel,nb-banks = <2>;
222	atmel,can-isoc;
223	};
224
225	ep14 {
226	reg = <14>;
227	atmel,fifo-size = <1024>;
228	atmel,nb-banks = <2>;
229	atmel,can-isoc;
230	};
231
232	ep15 {
233	reg = <15>;
234	atmel,fifo-size = <1024>;
235	atmel,nb-banks = <2>;
236	atmel,can-isoc;
237	};
238	};
239
240	usb1: ohci@00400000 {
241	compatible = "atmel,at91rm9200-ohci", "usb-ohci";
242	reg = <0x00400000 0x100000>;
243	interrupts = <41 IRQ_TYPE_LEVEL_HIGH 2>;
244	clocks = <&uhphs_clk>, <&uhphs_clk>, <&uhpck>;
245	clock-names = "ohci_clk", "hclk", "uhpck";
246	status = "disabled";
247	};
248
249	usb2: ehci@00500000 {
250	compatible = "atmel,at91sam9g45-ehci", "usb-ehci";
251	reg = <0x00500000 0x100000>;
252	interrupts = <41 IRQ_TYPE_LEVEL_HIGH 2>;
253	clocks = <&utmi>, <&uhphs_clk>;
254	clock-names = "usb_clk", "ehci_clk";
255	status = "disabled";
256	};
257
258	L2: cache-controller@00a00000 {
259	compatible = "arm,pl310-cache";
260	reg = <0x00a00000 0x1000>;
261	interrupts = <63 IRQ_TYPE_LEVEL_HIGH 4>;
262	cache-unified;
263	cache-level = <2>;
264	};
265
266	apb {
267	compatible = "simple-bus";
268	#address-cells = <1>;
269	#size-cells = <1>;
270	ranges;
271
272	ramc0: ramc@f000c000 {
273	compatible = "atmel,sama5d3-ddramc";
274	reg = <0xf000c000 0x200>;
275	clocks = <&ddrck>, <&mpddr_clk>;
276	clock-names = "ddrck", "mpddr";
277	};
278
279	dma0: dma-controller@f0010000 {
280	compatible = "atmel,sama5d4-dma";
281	reg = <0xf0010000 0x1000>;
282	interrupts = <6 IRQ_TYPE_LEVEL_HIGH 0>;
283	#dma-cells = <1>;
284	clocks = <&dma0_clk>;
285	clock-names = "dma_clk";
286	};
287
288	pmc: pmc@f0014000 {
289	compatible = "atmel,sama5d2-pmc";
290	reg = <0xf0014000 0x160>;
291	interrupts = <74 IRQ_TYPE_LEVEL_HIGH 7>;
292	interrupt-controller;
293	#address-cells = <1>;
294	#size-cells = <0>;
295	#interrupt-cells = <1>;
296
297	main_rc_osc: main_rc_osc {
298	compatible = "atmel,at91sam9x5-clk-main-rc-osc";
299	#clock-cells = <0>;
300	interrupt-parent = <&pmc>;
301	interrupts = <AT91_PMC_MOSCRCS>;
302	clock-frequency = <12000000>;
303	clock-accuracy = <100000000>;
304	};
305
306	main_osc: main_osc {
307	compatible = "atmel,at91rm9200-clk-main-osc";
308	#clock-cells = <0>;
309	interrupt-parent = <&pmc>;
310	interrupts = <AT91_PMC_MOSCS>;
311	clocks = <&main_xtal>;
312	};
313
314	main: mainck {
315	compatible = "atmel,at91sam9x5-clk-main";
316	#clock-cells = <0>;
317	interrupt-parent = <&pmc>;
318	interrupts = <AT91_PMC_MOSCSELS>;
319	clocks = <&main_rc_osc &main_osc>;
320	};
321
322	plla: pllack {
323	compatible = "atmel,sama5d3-clk-pll";
324	#clock-cells = <0>;
325	interrupt-parent = <&pmc>;
326	interrupts = <AT91_PMC_LOCKA>;
327	clocks = <&main>;
328	reg = <0>;
329	atmel,clk-input-range = <12000000 12000000>;
330	#atmel,pll-clk-output-range-cells = <4>;
331	atmel,pll-clk-output-ranges = <600000000 1200000000 0 0>;
332	};
333
334	plladiv: plladivck {
335	compatible = "atmel,at91sam9x5-clk-plldiv";
336	#clock-cells = <0>;
337	clocks = <&plla>;
338	};
339
340	utmi: utmick {
341	compatible = "atmel,at91sam9x5-clk-utmi";
342	#clock-cells = <0>;
343	interrupt-parent = <&pmc>;
344	interrupts = <AT91_PMC_LOCKU>;
345	clocks = <&main>;
346	};
347
348	mck: masterck {
349	compatible = "atmel,at91sam9x5-clk-master";
350	#clock-cells = <0>;
351	interrupt-parent = <&pmc>;
352	interrupts = <AT91_PMC_MCKRDY>;
353	clocks = <&clk32k>, <&main>, <&plladiv>, <&utmi>;
354	atmel,clk-output-range = <124000000 166000000>;
355	atmel,clk-divisors = <1 2 4 3>;
356	};
357
358	h32ck: h32mxck {
359	#clock-cells = <0>;
360	compatible = "atmel,sama5d4-clk-h32mx";
361	clocks = <&mck>;
362	};
363
364	usb: usbck {
365	compatible = "atmel,at91sam9x5-clk-usb";
366	#clock-cells = <0>;
367	clocks = <&plladiv>, <&utmi>;
368	};
369
370	prog: progck {
371	compatible = "atmel,at91sam9x5-clk-programmable";
372	#address-cells = <1>;
373	#size-cells = <0>;
374	interrupt-parent = <&pmc>;
375	clocks = <&clk32k>, <&main>, <&plladiv>, <&utmi>, <&mck>;
376
377	prog0: prog0 {
378	#clock-cells = <0>;
379	reg = <0>;
380	interrupts = <AT91_PMC_PCKRDY(0)>;
381	};
382
383	prog1: prog1 {
384	#clock-cells = <0>;
385	reg = <1>;
386	interrupts = <AT91_PMC_PCKRDY(1)>;
387	};
388
389	prog2: prog2 {
390	#clock-cells = <0>;
391	reg = <2>;
392	interrupts = <AT91_PMC_PCKRDY(2)>;
393	};
394	};
395
396	systemck {
397	compatible = "atmel,at91rm9200-clk-system";
398	#address-cells = <1>;
399	#size-cells = <0>;
400
401	ddrck: ddrck {
402	#clock-cells = <0>;
403	reg = <2>;
404	clocks = <&mck>;
405	};
406
407	lcdck: lcdck {
408	#clock-cells = <0>;
409	reg = <3>;
410	clocks = <&mck>;
411	};
412
413	uhpck: uhpck {
414	#clock-cells = <0>;
415	reg = <6>;
416	clocks = <&usb>;
417	};
418
419	udpck: udpck {
420	#clock-cells = <0>;
421	reg = <7>;
422	clocks = <&usb>;
423	};
424
425	pck0: pck0 {
426	#clock-cells = <0>;
427	reg = <8>;
428	clocks = <&prog0>;
429	};
430
431	pck1: pck1 {
432	#clock-cells = <0>;
433	reg = <9>;
434	clocks = <&prog1>;
435	};
436
437	pck2: pck2 {
438	#clock-cells = <0>;
439	reg = <10>;
440	clocks = <&prog2>;
441	};
442
443	iscck: iscck {
444	#clock-cells = <0>;
445	reg = <18>;
446	clocks = <&mck>;
447	};
448	};
449
450	periph32ck {
451	compatible = "atmel,at91sam9x5-clk-peripheral";
452	#address-cells = <1>;
453	#size-cells = <0>;
454	clocks = <&h32ck>;
455
456	macb0_clk: macb0_clk {
457	#clock-cells = <0>;
458	reg = <5>;
459	atmel,clk-output-range = <0 83000000>;
460	};
461
462	tdes_clk: tdes_clk {
463	#clock-cells = <0>;
464	reg = <11>;
465	atmel,clk-output-range = <0 83000000>;
466	};
467
468	matrix1_clk: matrix1_clk {
469	#clock-cells = <0>;
470	reg = <14>;
471	};
472
473	hsmc_clk: hsmc_clk {
474	#clock-cells = <0>;
475	reg = <17>;
476	};
477
478	pioA_clk: pioA_clk {
479	#clock-cells = <0>;
480	reg = <18>;
481	atmel,clk-output-range = <0 83000000>;
482	};
483
484	flx0_clk: flx0_clk {
485	#clock-cells = <0>;
486	reg = <19>;
487	atmel,clk-output-range = <0 83000000>;
488	};
489
490	flx1_clk: flx1_clk {
491	#clock-cells = <0>;
492	reg = <20>;
493	atmel,clk-output-range = <0 83000000>;
494	};
495
496	flx2_clk: flx2_clk {
497	#clock-cells = <0>;
498	reg = <21>;
499	atmel,clk-output-range = <0 83000000>;
500	};
501
502	flx3_clk: flx3_clk {
503	#clock-cells = <0>;
504	reg = <22>;
505	atmel,clk-output-range = <0 83000000>;
506	};
507
508	flx4_clk: flx4_clk {
509	#clock-cells = <0>;
510	reg = <23>;
511	atmel,clk-output-range = <0 83000000>;
512	};
513
514	uart0_clk: uart0_clk {
515	#clock-cells = <0>;
516	reg = <24>;
517	atmel,clk-output-range = <0 83000000>;
518	};
519
520	uart1_clk: uart1_clk {
521	#clock-cells = <0>;
522	reg = <25>;
523	atmel,clk-output-range = <0 83000000>;
524	};
525
526	uart2_clk: uart2_clk {
527	#clock-cells = <0>;
528	reg = <26>;
529	atmel,clk-output-range = <0 83000000>;
530	};
531
532	uart3_clk: uart3_clk {
533	#clock-cells = <0>;
534	reg = <27>;
535	atmel,clk-output-range = <0 83000000>;
536	};
537
538	uart4_clk: uart4_clk {
539	#clock-cells = <0>;
540	reg = <28>;
541	atmel,clk-output-range = <0 83000000>;
542	};
543
544	twi0_clk: twi0_clk {
545	reg = <29>;
546	#clock-cells = <0>;
547	atmel,clk-output-range = <0 83000000>;
548	};
549
550	twi1_clk: twi1_clk {
551	#clock-cells = <0>;
552	reg = <30>;
553	atmel,clk-output-range = <0 83000000>;
554	};
555
556	spi0_clk: spi0_clk {
557	#clock-cells = <0>;
558	reg = <33>;
559	atmel,clk-output-range = <0 83000000>;
560	};
561
562	spi1_clk: spi1_clk {
563	#clock-cells = <0>;
564	reg = <34>;
565	atmel,clk-output-range = <0 83000000>;
566	};
567
568	tcb0_clk: tcb0_clk {
569	#clock-cells = <0>;
570	reg = <35>;
571	atmel,clk-output-range = <0 83000000>;
572	};
573
574	tcb1_clk: tcb1_clk {
575	#clock-cells = <0>;
576	reg = <36>;
577	atmel,clk-output-range = <0 83000000>;
578	};
579
580	pwm_clk: pwm_clk {
581	#clock-cells = <0>;
582	reg = <38>;
583	atmel,clk-output-range = <0 83000000>;
584	};
585
586	adc_clk: adc_clk {
587	#clock-cells = <0>;
588	reg = <40>;
589	atmel,clk-output-range = <0 83000000>;
590	};
591
592	uhphs_clk: uhphs_clk {
593	#clock-cells = <0>;
594	reg = <41>;
595	atmel,clk-output-range = <0 83000000>;
596	};
597
598	udphs_clk: udphs_clk {
599	#clock-cells = <0>;
600	reg = <42>;
601	atmel,clk-output-range = <0 83000000>;
602	};
603
604	ssc0_clk: ssc0_clk {
605	#clock-cells = <0>;
606	reg = <43>;
607	atmel,clk-output-range = <0 83000000>;
608	};
609
610	ssc1_clk: ssc1_clk {
611	#clock-cells = <0>;
612	reg = <44>;
613	atmel,clk-output-range = <0 83000000>;
614	};
615
616	trng_clk: trng_clk {
617	#clock-cells = <0>;
618	reg = <47>;
619	atmel,clk-output-range = <0 83000000>;
620	};
621
622	classd_clk: classd_clk {
623	#clock-cells = <0>;
624	reg = <59>;
625	atmel,clk-output-range = <0 83000000>;
626	};
627	};
628
629	periph64ck {
630	compatible = "atmel,at91sam9x5-clk-peripheral";
631	#address-cells = <1>;
632	#size-cells = <0>;
633	clocks = <&mck>;
634
635	dma0_clk: dma0_clk {
636	#clock-cells = <0>;
637	reg = <6>;
638	};
639
640	dma1_clk: dma1_clk {
641	#clock-cells = <0>;
642	reg = <7>;
643	};
644
645	aes_clk: aes_clk {
646	#clock-cells = <0>;
647	reg = <9>;
648	};
649
650	aesb_clk: aesb_clk {
651	#clock-cells = <0>;
652	reg = <10>;
653	};
654
655	sha_clk: sha_clk {
656	#clock-cells = <0>;
657	reg = <12>;
658	};
659
660	mpddr_clk: mpddr_clk {
661	#clock-cells = <0>;
662	reg = <13>;
663	};
664
665	matrix0_clk: matrix0_clk {
666	#clock-cells = <0>;
667	reg = <15>;
668	};
669
670	sdmmc0_hclk: sdmmc0_hclk {
671	#clock-cells = <0>;
672	reg = <31>;
673	};
674
675	sdmmc1_hclk: sdmmc1_hclk {
676	#clock-cells = <0>;
677	reg = <32>;
678	};
679
680	lcdc_clk: lcdc_clk {
681	#clock-cells = <0>;
682	reg = <45>;
683	};
684
685	isc_clk: isc_clk {
686	#clock-cells = <0>;
687	reg = <46>;
688	};
689
690	qspi0_clk: qspi0_clk {
691	#clock-cells = <0>;
692	reg = <52>;
693	};
694
695	qspi1_clk: qspi1_clk {
696	#clock-cells = <0>;
697	reg = <53>;
698	};
699	};
700	};
701
702	sha@f0028000 {
703	compatible = "atmel,at91sam9g46-sha";
704	reg = <0xf0028000 0x100>;
705	interrupts = <12 IRQ_TYPE_LEVEL_HIGH 0>;
706	dmas = <&dma0
707	(AT91_XDMAC_DT_MEM_IF(0) \| AT91_XDMAC_DT_PER_IF(1) \|
708	AT91_XDMAC_DT_PERID(30))>;
709	dma-names = "tx";
710	clocks = <&sha_clk>;
711	clock-names = "sha_clk";
712	status = "disabled";
713	};
714
715	aes@f002c000 {
716	compatible = "atmel,at91sam9g46-aes";
717	reg = <0xf002c000 0x100>;
718	interrupts = <9 IRQ_TYPE_LEVEL_HIGH 0>;
719	dmas = <&dma0
720	(AT91_XDMAC_DT_MEM_IF(0) \| AT91_XDMAC_DT_PER_IF(1) \|
721	AT91_XDMAC_DT_PERID(26))>,
722	<&dma0
723	(AT91_XDMAC_DT_MEM_IF(0) \| AT91_XDMAC_DT_PER_IF(1) \|
724	AT91_XDMAC_DT_PERID(27))>;
725	dma-names = "tx", "rx";
726	clocks = <&aes_clk>;
727	clock-names = "aes_clk";
728	status = "disabled";
729	};
730
731	spi0: spi@f8000000 {
732	compatible = "atmel,at91rm9200-spi";
733	reg = <0xf8000000 0x100>;
734	interrupts = <33 IRQ_TYPE_LEVEL_HIGH 7>;
735	dmas = <&dma0
736	(AT91_XDMAC_DT_MEM_IF(0) \| AT91_XDMAC_DT_PER_IF(1) \|
737	AT91_XDMAC_DT_PERID(6))>,
738	<&dma0
739	(AT91_XDMAC_DT_MEM_IF(0) \| AT91_XDMAC_DT_PER_IF(1) \|
740	AT91_XDMAC_DT_PERID(7))>;
741	dma-names = "tx", "rx";
742	clocks = <&spi0_clk>;
743	clock-names = "spi_clk";
744	atmel,fifo-size = <16>;
745	#address-cells = <1>;
746	#size-cells = <0>;
747	status = "disabled";
748	};
749
750	macb0: ethernet@f8008000 {
751	compatible = "atmel,sama5d2-gem";
752	reg = <0xf8008000 0x1000>;
753	interrupts = <5 IRQ_TYPE_LEVEL_HIGH 3 /* Queue 0 */
754	66 IRQ_TYPE_LEVEL_HIGH 3 /* Queue 1 */
755	67 IRQ_TYPE_LEVEL_HIGH 3>; /* Queue 2 */
756	#address-cells = <1>;
757	#size-cells = <0>;
758	clocks = <&macb0_clk>, <&macb0_clk>;
759	clock-names = "hclk", "pclk";
760	status = "disabled";
761	};
762
763	tcb0: timer@f800c000 {
764	compatible = "atmel,at91sam9x5-tcb";
765	reg = <0xf800c000 0x100>;
766	interrupts = <35 IRQ_TYPE_LEVEL_HIGH 0>;
761c5867 AB	767	clocks = <&tcb0_clk>, <&clk32k>;
761c5867 AB	768	clock-names = "t0_clk", "slow_clk";
e30cf8d3 LD	769	};
	770
	771	tcb1: timer@f8010000 {
	772	compatible = "atmel,at91sam9x5-tcb";
	773	reg = <0xf8010000 0x100>;
	774	interrupts = <36 IRQ_TYPE_LEVEL_HIGH 0>;
761c5867 AB	775	clocks = <&tcb1_clk>, <&clk32k>;
761c5867 AB	776	clock-names = "t0_clk", "slow_clk";
e30cf8d3 LD	777	};
	778
	779	uart0: serial@f801c000 {
	780	compatible = "atmel,at91sam9260-usart";
	781	reg = <0xf801c000 0x100>;
	782	interrupts = <24 IRQ_TYPE_LEVEL_HIGH 7>;
	783	clocks = <&uart0_clk>;
	784	clock-names = "usart";
	785	status = "disabled";
	786	};
	787
	788	uart1: serial@f8020000 {
	789	compatible = "atmel,at91sam9260-usart";
	790	reg = <0xf8020000 0x100>;
	791	interrupts = <25 IRQ_TYPE_LEVEL_HIGH 7>;
	792	clocks = <&uart1_clk>;
	793	clock-names = "usart";
	794	status = "disabled";
	795	};
	796
	797	uart2: serial@f8024000 {
	798	compatible = "atmel,at91sam9260-usart";
	799	reg = <0xf8024000 0x100>;
	800	interrupts = <26 IRQ_TYPE_LEVEL_HIGH 7>;
	801	clocks = <&uart2_clk>;
	802	clock-names = "usart";
	803	status = "disabled";
	804	};
	805
	806	i2c0: i2c@f8028000 {
	807	compatible = "atmel,sama5d2-i2c";
	808	reg = <0xf8028000 0x100>;
	809	interrupts = <29 IRQ_TYPE_LEVEL_HIGH 7>;
	810	dmas = <&dma0
	811	(AT91_XDMAC_DT_MEM_IF(0) \| AT91_XDMAC_DT_PER_IF(1) \|
	812	AT91_XDMAC_DT_PERID(0))>,
	813	<&dma0
	814	(AT91_XDMAC_DT_MEM_IF(0) \| AT91_XDMAC_DT_PER_IF(1) \|
	815	AT91_XDMAC_DT_PERID(1))>;
	816	dma-names = "tx", "rx";
	817	#address-cells = <1>;
	818	#size-cells = <0>;
	819	clocks = <&twi0_clk>;
	820	status = "disabled";
	821	};
	822
	823	pit: timer@f8048030 {
	824	compatible = "atmel,at91sam9260-pit";
	825	reg = <0xf8048030 0x10>;
	826	interrupts = <3 IRQ_TYPE_LEVEL_HIGH 5>;
	827	clocks = <&h32ck>;
	828	};
	829
	830	sckc@f8048050 {
	831	compatible = "atmel,at91sam9x5-sckc";
	832	reg = <0xf8048050 0x4>;
	833
	834	slow_rc_osc: slow_rc_osc {
	835	compatible = "atmel,at91sam9x5-clk-slow-rc-osc";
	836	#clock-cells = <0>;
	837	clock-frequency = <32768>;
	838	clock-accuracy = <250000000>;
	839	atmel,startup-time-usec = <75>;
	840	};
841
842	slow_osc: slow_osc {
843	compatible = "atmel,at91sam9x5-clk-slow-osc";
844	#clock-cells = <0>;
845	clocks = <&slow_xtal>;
846	atmel,startup-time-usec = <1200000>;
847	};
848
849	clk32k: slowck {
850	compatible = "atmel,at91sam9x5-clk-slow";
851	#clock-cells = <0>;
852	clocks = <&slow_rc_osc &slow_osc>;
853	};
854	};
855
856	rtc@f80480b0 {
857	compatible = "atmel,at91rm9200-rtc";
858	reg = <0xf80480b0 0x30>;
859	interrupts = <74 IRQ_TYPE_LEVEL_HIGH 7>;
761c5867	860	clocks = <&clk32k>;
e30cf8d3 LD	861	};
	862
	863	spi1: spi@fc000000 {
	864	compatible = "atmel,at91rm9200-spi";
	865	reg = <0xfc000000 0x100>;
	866	interrupts = <34 IRQ_TYPE_LEVEL_HIGH 7>;
	867	dmas = <&dma0
	868	(AT91_XDMAC_DT_MEM_IF(0) \| AT91_XDMAC_DT_PER_IF(1) \|
	869	AT91_XDMAC_DT_PERID(8))>,
	870	<&dma0
	871	(AT91_XDMAC_DT_MEM_IF(0) \| AT91_XDMAC_DT_PER_IF(1) \|
	872	AT91_XDMAC_DT_PERID(9))>;
	873	dma-names = "tx", "rx";
	874	clocks = <&spi1_clk>;
	875	clock-names = "spi_clk";
	876	atmel,fifo-size = <16>;
	877	#address-cells = <1>;
	878	#size-cells = <0>;
	879	status = "disabled";
	880	};
	881
	882	uart3: serial@fc008000 {
	883	compatible = "atmel,at91sam9260-usart";
	884	reg = <0xfc008000 0x100>;
	885	interrupts = <27 IRQ_TYPE_LEVEL_HIGH 7>;
	886	clocks = <&uart3_clk>;
	887	clock-names = "usart";
	888	status = "disabled";
	889	};
	890
	891	uart4: serial@fc00c000 {
	892	compatible = "atmel,at91sam9260-usart";
	893	reg = <0xfc00c000 0x100>;
	894	interrupts = <28 IRQ_TYPE_LEVEL_HIGH 7>;
	895	clocks = <&uart4_clk>;
	896	clock-names = "usart";
	897	status = "disabled";
	898	};
	899
	900	aic: interrupt-controller@fc020000 {
	901	#interrupt-cells = <3>;
	902	compatible = "atmel,sama5d2-aic";
	903	interrupt-controller;
	904	reg = <0xfc020000 0x200>;
	905	atmel,external-irqs = <49>;
	906	};
	907
	908	i2c1: i2c@fc028000 {
	909	compatible = "atmel,sama5d2-i2c";
	910	reg = <0xfc028000 0x100>;
	911	interrupts = <30 IRQ_TYPE_LEVEL_HIGH 7>;
	912	dmas = <&dma0
	913	(AT91_XDMAC_DT_MEM_IF(0) \| AT91_XDMAC_DT_PER_IF(1) \|
	914	AT91_XDMAC_DT_PERID(2))>,
	915	<&dma0
	916	(AT91_XDMAC_DT_MEM_IF(0) \| AT91_XDMAC_DT_PER_IF(1) \|
	917	AT91_XDMAC_DT_PERID(3))>;
	918	dma-names = "tx", "rx";
	919	#address-cells = <1>;
	920	#size-cells = <0>;
	921	clocks = <&twi1_clk>;
	922	status = "disabled";
	923	};
	924	};
925	};
926	};