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35aca364 HS |
1 | /* |
2 | * Samsung's S3C2416 SoC device tree source | |
3 | * | |
4 | * Copyright (c) 2013 Heiko Stuebner <heiko@sntech.de> | |
5 | * | |
6 | * This program is free software; you can redistribute it and/or modify | |
7 | * it under the terms of the GNU General Public License version 2 as | |
8 | * published by the Free Software Foundation. | |
9 | */ | |
10 | ||
8cb28748 | 11 | #include <dt-bindings/clock/s3c2443.h> |
3799279f PV |
12 | #include "s3c24xx.dtsi" |
13 | #include "s3c2416-pinctrl.dtsi" | |
35aca364 HS |
14 | |
15 | / { | |
16 | model = "Samsung S3C2416 SoC"; | |
17 | compatible = "samsung,s3c2416"; | |
18 | ||
19 | cpus { | |
20 | #address-cells = <1>; | |
21 | #size-cells = <0>; | |
22 | ||
23 | cpu { | |
24 | compatible = "arm,arm926ejs"; | |
25 | }; | |
26 | }; | |
27 | ||
28 | interrupt-controller@4a000000 { | |
29 | compatible = "samsung,s3c2416-irq"; | |
30 | }; | |
31 | ||
8cb28748 HS |
32 | clocks: clock-controller@0x4c000000 { |
33 | compatible = "samsung,s3c2416-clock"; | |
34 | reg = <0x4c000000 0x40>; | |
35 | #clock-cells = <1>; | |
36 | }; | |
37 | ||
35aca364 HS |
38 | pinctrl@56000000 { |
39 | compatible = "samsung,s3c2416-pinctrl"; | |
40 | }; | |
41 | ||
8cb28748 HS |
42 | timer@51000000 { |
43 | clocks = <&clocks PCLK_PWM>; | |
44 | clock-names = "timers"; | |
45 | }; | |
46 | ||
35aca364 HS |
47 | serial@50000000 { |
48 | compatible = "samsung,s3c2440-uart"; | |
8cb28748 HS |
49 | clock-names = "uart", "clk_uart_baud2", |
50 | "clk_uart_baud3"; | |
51 | clocks = <&clocks PCLK_UART0>, <&clocks PCLK_UART0>, | |
52 | <&clocks SCLK_UART>; | |
35aca364 HS |
53 | }; |
54 | ||
55 | serial@50004000 { | |
56 | compatible = "samsung,s3c2440-uart"; | |
8cb28748 HS |
57 | clock-names = "uart", "clk_uart_baud2", |
58 | "clk_uart_baud3"; | |
59 | clocks = <&clocks PCLK_UART1>, <&clocks PCLK_UART1>, | |
60 | <&clocks SCLK_UART>; | |
35aca364 HS |
61 | }; |
62 | ||
63 | serial@50008000 { | |
64 | compatible = "samsung,s3c2440-uart"; | |
8cb28748 HS |
65 | clock-names = "uart", "clk_uart_baud2", |
66 | "clk_uart_baud3"; | |
67 | clocks = <&clocks PCLK_UART2>, <&clocks PCLK_UART2>, | |
68 | <&clocks SCLK_UART>; | |
35aca364 HS |
69 | }; |
70 | ||
71 | serial@5000C000 { | |
72 | compatible = "samsung,s3c2440-uart"; | |
73 | reg = <0x5000C000 0x4000>; | |
74 | interrupts = <1 18 24 4>, <1 18 25 4>; | |
8cb28748 HS |
75 | clock-names = "uart", "clk_uart_baud2", |
76 | "clk_uart_baud3"; | |
77 | clocks = <&clocks PCLK_UART3>, <&clocks PCLK_UART3>, | |
78 | <&clocks SCLK_UART>; | |
35aca364 HS |
79 | status = "disabled"; |
80 | }; | |
81 | ||
82 | sdhci@4AC00000 { | |
83 | compatible = "samsung,s3c6410-sdhci"; | |
84 | reg = <0x4AC00000 0x100>; | |
85 | interrupts = <0 0 21 3>; | |
8cb28748 HS |
86 | clock-names = "hsmmc", "mmc_busclk.0", |
87 | "mmc_busclk.2"; | |
88 | clocks = <&clocks HCLK_HSMMC0>, <&clocks HCLK_HSMMC0>, | |
89 | <&clocks MUX_HSMMC0>; | |
35aca364 HS |
90 | status = "disabled"; |
91 | }; | |
92 | ||
93 | sdhci@4A800000 { | |
94 | compatible = "samsung,s3c6410-sdhci"; | |
95 | reg = <0x4A800000 0x100>; | |
96 | interrupts = <0 0 20 3>; | |
8cb28748 HS |
97 | clock-names = "hsmmc", "mmc_busclk.0", |
98 | "mmc_busclk.2"; | |
99 | clocks = <&clocks HCLK_HSMMC1>, <&clocks HCLK_HSMMC1>, | |
100 | <&clocks MUX_HSMMC1>; | |
35aca364 HS |
101 | status = "disabled"; |
102 | }; | |
103 | ||
104 | watchdog@53000000 { | |
105 | interrupts = <1 9 27 3>; | |
8cb28748 HS |
106 | clocks = <&clocks PCLK_WDT>; |
107 | clock-names = "watchdog"; | |
35aca364 HS |
108 | }; |
109 | ||
110 | rtc@57000000 { | |
111 | compatible = "samsung,s3c2416-rtc"; | |
8cb28748 HS |
112 | clocks = <&clocks PCLK_RTC>; |
113 | clock-names = "rtc"; | |
35aca364 HS |
114 | }; |
115 | ||
116 | i2c@54000000 { | |
117 | compatible = "samsung,s3c2440-i2c"; | |
8cb28748 HS |
118 | clocks = <&clocks PCLK_I2C0>; |
119 | clock-names = "i2c"; | |
35aca364 HS |
120 | }; |
121 | }; |