Merge tag 'for-linus' of git://github.com/openrisc/linux
[linux-2.6-block.git] / arch / arm / boot / dts / s3c2416.dtsi
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1/*
2 * Samsung's S3C2416 SoC device tree source
3 *
4 * Copyright (c) 2013 Heiko Stuebner <heiko@sntech.de>
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
9 */
10
8cb28748 11#include <dt-bindings/clock/s3c2443.h>
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12#include "s3c24xx.dtsi"
13#include "s3c2416-pinctrl.dtsi"
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14
15/ {
16 model = "Samsung S3C2416 SoC";
17 compatible = "samsung,s3c2416";
18
1e64f48e 19 aliases {
3ae9d92f 20 serial3 = &uart_3;
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21 };
22
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23 cpus {
24 #address-cells = <1>;
25 #size-cells = <0>;
26
27 cpu {
6716f6c6 28 compatible = "arm,arm926ej-s";
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29 };
30 };
31
32 interrupt-controller@4a000000 {
33 compatible = "samsung,s3c2416-irq";
34 };
35
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36 clocks: clock-controller@0x4c000000 {
37 compatible = "samsung,s3c2416-clock";
38 reg = <0x4c000000 0x40>;
39 #clock-cells = <1>;
40 };
41
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42 pinctrl@56000000 {
43 compatible = "samsung,s3c2416-pinctrl";
44 };
45
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46 timer@51000000 {
47 clocks = <&clocks PCLK_PWM>;
48 clock-names = "timers";
49 };
50
3ae9d92f 51 uart_0: serial@50000000 {
35aca364 52 compatible = "samsung,s3c2440-uart";
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53 clock-names = "uart", "clk_uart_baud2",
54 "clk_uart_baud3";
55 clocks = <&clocks PCLK_UART0>, <&clocks PCLK_UART0>,
56 <&clocks SCLK_UART>;
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57 };
58
3ae9d92f 59 uart_1: serial@50004000 {
35aca364 60 compatible = "samsung,s3c2440-uart";
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61 clock-names = "uart", "clk_uart_baud2",
62 "clk_uart_baud3";
63 clocks = <&clocks PCLK_UART1>, <&clocks PCLK_UART1>,
64 <&clocks SCLK_UART>;
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65 };
66
3ae9d92f 67 uart_2: serial@50008000 {
35aca364 68 compatible = "samsung,s3c2440-uart";
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69 clock-names = "uart", "clk_uart_baud2",
70 "clk_uart_baud3";
71 clocks = <&clocks PCLK_UART2>, <&clocks PCLK_UART2>,
72 <&clocks SCLK_UART>;
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73 };
74
3ae9d92f 75 uart_3: serial@5000C000 {
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76 compatible = "samsung,s3c2440-uart";
77 reg = <0x5000C000 0x4000>;
78 interrupts = <1 18 24 4>, <1 18 25 4>;
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79 clock-names = "uart", "clk_uart_baud2",
80 "clk_uart_baud3";
81 clocks = <&clocks PCLK_UART3>, <&clocks PCLK_UART3>,
82 <&clocks SCLK_UART>;
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83 status = "disabled";
84 };
85
3ae9d92f 86 sdhci_1: sdhci@4AC00000 {
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87 compatible = "samsung,s3c6410-sdhci";
88 reg = <0x4AC00000 0x100>;
89 interrupts = <0 0 21 3>;
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90 clock-names = "hsmmc", "mmc_busclk.0",
91 "mmc_busclk.2";
92 clocks = <&clocks HCLK_HSMMC0>, <&clocks HCLK_HSMMC0>,
93 <&clocks MUX_HSMMC0>;
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94 status = "disabled";
95 };
96
3ae9d92f 97 sdhci_0: sdhci@4A800000 {
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98 compatible = "samsung,s3c6410-sdhci";
99 reg = <0x4A800000 0x100>;
100 interrupts = <0 0 20 3>;
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101 clock-names = "hsmmc", "mmc_busclk.0",
102 "mmc_busclk.2";
103 clocks = <&clocks HCLK_HSMMC1>, <&clocks HCLK_HSMMC1>,
104 <&clocks MUX_HSMMC1>;
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105 status = "disabled";
106 };
107
3ae9d92f 108 watchdog: watchdog@53000000 {
35aca364 109 interrupts = <1 9 27 3>;
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110 clocks = <&clocks PCLK_WDT>;
111 clock-names = "watchdog";
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112 };
113
3ae9d92f 114 rtc: rtc@57000000 {
35aca364 115 compatible = "samsung,s3c2416-rtc";
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116 clocks = <&clocks PCLK_RTC>;
117 clock-names = "rtc";
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118 };
119
120 i2c@54000000 {
121 compatible = "samsung,s3c2440-i2c";
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122 clocks = <&clocks PCLK_I2C0>;
123 clock-names = "i2c";
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124 };
125};