Commit | Line | Data |
---|---|---|
2ab557b7 | 1 | /* |
b1772506 HS |
2 | * This file is dual-licensed: you can use it either under the terms |
3 | * of the GPL or the X11 license, at your option. Note that this dual | |
4 | * licensing only applies to this file, and not this project as a | |
5 | * whole. | |
2ab557b7 | 6 | * |
b1772506 HS |
7 | * a) This file is free software; you can redistribute it and/or |
8 | * modify it under the terms of the GNU General Public License as | |
9 | * published by the Free Software Foundation; either version 2 of the | |
10 | * License, or (at your option) any later version. | |
11 | * | |
12 | * This file is distributed in the hope that it will be useful, | |
13 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
14 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
15 | * GNU General Public License for more details. | |
16 | * | |
17 | * Or, alternatively, | |
18 | * | |
19 | * b) Permission is hereby granted, free of charge, to any person | |
20 | * obtaining a copy of this software and associated documentation | |
21 | * files (the "Software"), to deal in the Software without | |
22 | * restriction, including without limitation the rights to use, | |
23 | * copy, modify, merge, publish, distribute, sublicense, and/or | |
24 | * sell copies of the Software, and to permit persons to whom the | |
25 | * Software is furnished to do so, subject to the following | |
26 | * conditions: | |
27 | * | |
28 | * The above copyright notice and this permission notice shall be | |
29 | * included in all copies or substantial portions of the Software. | |
30 | * | |
31 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, | |
32 | * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES | |
33 | * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND | |
34 | * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT | |
35 | * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, | |
36 | * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING | |
37 | * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR | |
38 | * OTHER DEALINGS IN THE SOFTWARE. | |
2ab557b7 HS |
39 | */ |
40 | ||
41 | #include <dt-bindings/gpio/gpio.h> | |
42 | #include <dt-bindings/interrupt-controller/irq.h> | |
43 | #include <dt-bindings/interrupt-controller/arm-gic.h> | |
44 | #include <dt-bindings/pinctrl/rockchip.h> | |
45 | #include <dt-bindings/clock/rk3288-cru.h> | |
e3df026c | 46 | #include <dt-bindings/power/rk3288-power.h> |
b67d6bc3 | 47 | #include <dt-bindings/thermal/thermal.h> |
b63af764 | 48 | #include <dt-bindings/power/rk3288-power.h> |
b60ab70b | 49 | #include <dt-bindings/soc/rockchip,boot-mode.h> |
2ab557b7 HS |
50 | |
51 | / { | |
79db45be TH |
52 | #address-cells = <2>; |
53 | #size-cells = <2>; | |
c6b2d392 | 54 | |
2ab557b7 HS |
55 | compatible = "rockchip,rk3288"; |
56 | ||
57 | interrupt-parent = <&gic>; | |
58 | ||
59 | aliases { | |
85ef8d61 | 60 | ethernet0 = &gmac; |
2ab557b7 HS |
61 | i2c0 = &i2c0; |
62 | i2c1 = &i2c1; | |
63 | i2c2 = &i2c2; | |
64 | i2c3 = &i2c3; | |
65 | i2c4 = &i2c4; | |
66 | i2c5 = &i2c5; | |
d7f9a388 DA |
67 | mshc0 = &emmc; |
68 | mshc1 = &sdmmc; | |
69 | mshc2 = &sdio0; | |
70 | mshc3 = &sdio1; | |
2ab557b7 HS |
71 | serial0 = &uart0; |
72 | serial1 = &uart1; | |
73 | serial2 = &uart2; | |
74 | serial3 = &uart3; | |
75 | serial4 = &uart4; | |
1f53170b | 76 | spi0 = &spi0; |
77 | spi1 = &spi1; | |
78 | spi2 = &spi2; | |
2ab557b7 HS |
79 | }; |
80 | ||
f1840780 SR |
81 | arm-pmu { |
82 | compatible = "arm,cortex-a12-pmu"; | |
83 | interrupts = <GIC_SPI 151 IRQ_TYPE_LEVEL_HIGH>, | |
84 | <GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH>, | |
85 | <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>, | |
86 | <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>; | |
4863dcd3 | 87 | interrupt-affinity = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>; |
f1840780 SR |
88 | }; |
89 | ||
2ab557b7 HS |
90 | cpus { |
91 | #address-cells = <1>; | |
92 | #size-cells = <0>; | |
08bcc754 | 93 | enable-method = "rockchip,rk3066-smp"; |
fbdbc732 | 94 | rockchip,pmu = <&pmu>; |
2ab557b7 | 95 | |
be8a77c5 | 96 | cpu0: cpu@500 { |
2ab557b7 HS |
97 | device_type = "cpu"; |
98 | compatible = "arm,cortex-a12"; | |
99 | reg = <0x500>; | |
044542af | 100 | resets = <&cru SRST_CORE0>; |
be8a77c5 HS |
101 | operating-points = < |
102 | /* KHz uV */ | |
103 | 1608000 1350000 | |
104 | 1512000 1300000 | |
105 | 1416000 1200000 | |
106 | 1200000 1100000 | |
107 | 1008000 1050000 | |
108 | 816000 1000000 | |
109 | 696000 950000 | |
110 | 600000 900000 | |
111 | 408000 900000 | |
112 | 312000 900000 | |
113 | 216000 900000 | |
114 | 126000 900000 | |
115 | >; | |
b67d6bc3 | 116 | #cooling-cells = <2>; /* min followed by max */ |
be8a77c5 HS |
117 | clock-latency = <40000>; |
118 | clocks = <&cru ARMCLK>; | |
2ab557b7 | 119 | }; |
4863dcd3 | 120 | cpu1: cpu@501 { |
2ab557b7 HS |
121 | device_type = "cpu"; |
122 | compatible = "arm,cortex-a12"; | |
123 | reg = <0x501>; | |
044542af | 124 | resets = <&cru SRST_CORE1>; |
2ab557b7 | 125 | }; |
4863dcd3 | 126 | cpu2: cpu@502 { |
2ab557b7 HS |
127 | device_type = "cpu"; |
128 | compatible = "arm,cortex-a12"; | |
129 | reg = <0x502>; | |
044542af | 130 | resets = <&cru SRST_CORE2>; |
2ab557b7 | 131 | }; |
4863dcd3 | 132 | cpu3: cpu@503 { |
2ab557b7 HS |
133 | device_type = "cpu"; |
134 | compatible = "arm,cortex-a12"; | |
135 | reg = <0x503>; | |
044542af | 136 | resets = <&cru SRST_CORE3>; |
2ab557b7 HS |
137 | }; |
138 | }; | |
139 | ||
982891c3 | 140 | amba { |
2ef7d5f3 | 141 | compatible = "simple-bus"; |
79db45be TH |
142 | #address-cells = <2>; |
143 | #size-cells = <2>; | |
982891c3 HS |
144 | ranges; |
145 | ||
146 | dmac_peri: dma-controller@ff250000 { | |
147 | compatible = "arm,pl330", "arm,primecell"; | |
79db45be | 148 | reg = <0x0 0xff250000 0x0 0x4000>; |
982891c3 HS |
149 | interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>, |
150 | <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>; | |
151 | #dma-cells = <1>; | |
e7d6c9b1 | 152 | arm,pl330-broken-no-flushp; |
982891c3 HS |
153 | clocks = <&cru ACLK_DMAC2>; |
154 | clock-names = "apb_pclk"; | |
155 | }; | |
156 | ||
157 | dmac_bus_ns: dma-controller@ff600000 { | |
158 | compatible = "arm,pl330", "arm,primecell"; | |
79db45be | 159 | reg = <0x0 0xff600000 0x0 0x4000>; |
982891c3 HS |
160 | interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>, |
161 | <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>; | |
162 | #dma-cells = <1>; | |
e7d6c9b1 | 163 | arm,pl330-broken-no-flushp; |
982891c3 HS |
164 | clocks = <&cru ACLK_DMAC1>; |
165 | clock-names = "apb_pclk"; | |
166 | status = "disabled"; | |
167 | }; | |
168 | ||
169 | dmac_bus_s: dma-controller@ffb20000 { | |
170 | compatible = "arm,pl330", "arm,primecell"; | |
79db45be | 171 | reg = <0x0 0xffb20000 0x0 0x4000>; |
982891c3 HS |
172 | interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>, |
173 | <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>; | |
174 | #dma-cells = <1>; | |
e7d6c9b1 | 175 | arm,pl330-broken-no-flushp; |
982891c3 HS |
176 | clocks = <&cru ACLK_DMAC1>; |
177 | clock-names = "apb_pclk"; | |
178 | }; | |
179 | }; | |
180 | ||
b21bcfc9 | 181 | reserved-memory { |
79db45be TH |
182 | #address-cells = <2>; |
183 | #size-cells = <2>; | |
b21bcfc9 HS |
184 | ranges; |
185 | ||
186 | /* | |
187 | * The rk3288 cannot use the memory area above 0xfe000000 | |
188 | * for dma operations for some reason. While there is | |
189 | * probably a better solution available somewhere, we | |
190 | * haven't found it yet and while devices with 2GB of ram | |
191 | * are not affected, this issue prevents 4GB from booting. | |
192 | * So to make these devices at least bootable, block | |
193 | * this area for the time being until the real solution | |
194 | * is found. | |
195 | */ | |
196 | dma-unusable@fe000000 { | |
79db45be | 197 | reg = <0x0 0xfe000000 0x0 0x1000000>; |
b21bcfc9 HS |
198 | }; |
199 | }; | |
200 | ||
2ab557b7 HS |
201 | xin24m: oscillator { |
202 | compatible = "fixed-clock"; | |
203 | clock-frequency = <24000000>; | |
204 | clock-output-names = "xin24m"; | |
205 | #clock-cells = <0>; | |
206 | }; | |
207 | ||
208 | timer { | |
209 | compatible = "arm,armv7-timer"; | |
e2405a59 | 210 | arm,cpu-registers-not-fw-configured; |
2ab557b7 HS |
211 | interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>, |
212 | <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>, | |
213 | <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>, | |
214 | <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>; | |
215 | clock-frequency = <24000000>; | |
216 | }; | |
217 | ||
e48cc181 DL |
218 | timer: timer@ff810000 { |
219 | compatible = "rockchip,rk3288-timer"; | |
79db45be | 220 | reg = <0x0 0xff810000 0x0 0x20>; |
e48cc181 DL |
221 | interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>; |
222 | clocks = <&xin24m>, <&cru PCLK_TIMER>; | |
223 | clock-names = "timer", "pclk"; | |
224 | }; | |
225 | ||
a29cb8c4 DK |
226 | display-subsystem { |
227 | compatible = "rockchip,display-subsystem"; | |
228 | ports = <&vopl_out>, <&vopb_out>; | |
229 | }; | |
230 | ||
85095bf3 DA |
231 | sdmmc: dwmmc@ff0c0000 { |
232 | compatible = "rockchip,rk3288-dw-mshc"; | |
6a8883d6 | 233 | max-frequency = <150000000>; |
f71ddc58 AS |
234 | clocks = <&cru HCLK_SDMMC>, <&cru SCLK_SDMMC>, |
235 | <&cru SCLK_SDMMC_DRV>, <&cru SCLK_SDMMC_SAMPLE>; | |
236 | clock-names = "biu", "ciu", "ciu-drive", "ciu-sample"; | |
85095bf3 DA |
237 | fifo-depth = <0x100>; |
238 | interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>; | |
79db45be | 239 | reg = <0x0 0xff0c0000 0x0 0x4000>; |
06ecaae9 HS |
240 | resets = <&cru SRST_MMC0>; |
241 | reset-names = "reset"; | |
85095bf3 DA |
242 | status = "disabled"; |
243 | }; | |
244 | ||
f1a07231 AK |
245 | sdio0: dwmmc@ff0d0000 { |
246 | compatible = "rockchip,rk3288-dw-mshc"; | |
6a8883d6 | 247 | max-frequency = <150000000>; |
f71ddc58 AS |
248 | clocks = <&cru HCLK_SDIO0>, <&cru SCLK_SDIO0>, |
249 | <&cru SCLK_SDIO0_DRV>, <&cru SCLK_SDIO0_SAMPLE>; | |
250 | clock-names = "biu", "ciu", "ciu-drive", "ciu-sample"; | |
f1a07231 AK |
251 | fifo-depth = <0x100>; |
252 | interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>; | |
79db45be | 253 | reg = <0x0 0xff0d0000 0x0 0x4000>; |
06ecaae9 HS |
254 | resets = <&cru SRST_SDIO0>; |
255 | reset-names = "reset"; | |
f1a07231 AK |
256 | status = "disabled"; |
257 | }; | |
258 | ||
259 | sdio1: dwmmc@ff0e0000 { | |
260 | compatible = "rockchip,rk3288-dw-mshc"; | |
6a8883d6 | 261 | max-frequency = <150000000>; |
f71ddc58 AS |
262 | clocks = <&cru HCLK_SDIO1>, <&cru SCLK_SDIO1>, |
263 | <&cru SCLK_SDIO1_DRV>, <&cru SCLK_SDIO1_SAMPLE>; | |
264 | clock-names = "biu", "ciu", "ciu-drive", "ciu-sample"; | |
f1a07231 AK |
265 | fifo-depth = <0x100>; |
266 | interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>; | |
79db45be | 267 | reg = <0x0 0xff0e0000 0x0 0x4000>; |
06ecaae9 HS |
268 | resets = <&cru SRST_SDIO1>; |
269 | reset-names = "reset"; | |
f1a07231 AK |
270 | status = "disabled"; |
271 | }; | |
272 | ||
85095bf3 DA |
273 | emmc: dwmmc@ff0f0000 { |
274 | compatible = "rockchip,rk3288-dw-mshc"; | |
6a8883d6 | 275 | max-frequency = <150000000>; |
f71ddc58 AS |
276 | clocks = <&cru HCLK_EMMC>, <&cru SCLK_EMMC>, |
277 | <&cru SCLK_EMMC_DRV>, <&cru SCLK_EMMC_SAMPLE>; | |
278 | clock-names = "biu", "ciu", "ciu-drive", "ciu-sample"; | |
85095bf3 DA |
279 | fifo-depth = <0x100>; |
280 | interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>; | |
79db45be | 281 | reg = <0x0 0xff0f0000 0x0 0x4000>; |
06ecaae9 HS |
282 | resets = <&cru SRST_EMMC>; |
283 | reset-names = "reset"; | |
85095bf3 DA |
284 | status = "disabled"; |
285 | }; | |
286 | ||
f23a6179 HS |
287 | saradc: saradc@ff100000 { |
288 | compatible = "rockchip,saradc"; | |
79db45be | 289 | reg = <0x0 0xff100000 0x0 0x100>; |
f23a6179 HS |
290 | interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>; |
291 | #io-channel-cells = <1>; | |
292 | clocks = <&cru SCLK_SARADC>, <&cru PCLK_SARADC>; | |
293 | clock-names = "saradc", "apb_pclk"; | |
3d4267a5 CW |
294 | resets = <&cru SRST_SARADC>; |
295 | reset-names = "saradc-apb"; | |
f23a6179 HS |
296 | status = "disabled"; |
297 | }; | |
298 | ||
1f53170b | 299 | spi0: spi@ff110000 { |
300 | compatible = "rockchip,rk3288-spi", "rockchip,rk3066-spi"; | |
301 | clocks = <&cru SCLK_SPI0>, <&cru PCLK_SPI0>; | |
302 | clock-names = "spiclk", "apb_pclk"; | |
11bd57b8 DA |
303 | dmas = <&dmac_peri 11>, <&dmac_peri 12>; |
304 | dma-names = "tx", "rx"; | |
1f53170b | 305 | interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>; |
306 | pinctrl-names = "default"; | |
307 | pinctrl-0 = <&spi0_clk &spi0_tx &spi0_rx &spi0_cs0>; | |
79db45be | 308 | reg = <0x0 0xff110000 0x0 0x1000>; |
1f53170b | 309 | #address-cells = <1>; |
310 | #size-cells = <0>; | |
311 | status = "disabled"; | |
312 | }; | |
313 | ||
314 | spi1: spi@ff120000 { | |
315 | compatible = "rockchip,rk3288-spi", "rockchip,rk3066-spi"; | |
316 | clocks = <&cru SCLK_SPI1>, <&cru PCLK_SPI1>; | |
317 | clock-names = "spiclk", "apb_pclk"; | |
11bd57b8 DA |
318 | dmas = <&dmac_peri 13>, <&dmac_peri 14>; |
319 | dma-names = "tx", "rx"; | |
1f53170b | 320 | interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>; |
321 | pinctrl-names = "default"; | |
322 | pinctrl-0 = <&spi1_clk &spi1_tx &spi1_rx &spi1_cs0>; | |
79db45be | 323 | reg = <0x0 0xff120000 0x0 0x1000>; |
1f53170b | 324 | #address-cells = <1>; |
325 | #size-cells = <0>; | |
326 | status = "disabled"; | |
327 | }; | |
328 | ||
329 | spi2: spi@ff130000 { | |
330 | compatible = "rockchip,rk3288-spi", "rockchip,rk3066-spi"; | |
331 | clocks = <&cru SCLK_SPI2>, <&cru PCLK_SPI2>; | |
332 | clock-names = "spiclk", "apb_pclk"; | |
11bd57b8 DA |
333 | dmas = <&dmac_peri 15>, <&dmac_peri 16>; |
334 | dma-names = "tx", "rx"; | |
1f53170b | 335 | interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>; |
336 | pinctrl-names = "default"; | |
337 | pinctrl-0 = <&spi2_clk &spi2_tx &spi2_rx &spi2_cs0>; | |
79db45be | 338 | reg = <0x0 0xff130000 0x0 0x1000>; |
1f53170b | 339 | #address-cells = <1>; |
340 | #size-cells = <0>; | |
341 | status = "disabled"; | |
342 | }; | |
343 | ||
2ab557b7 HS |
344 | i2c1: i2c@ff140000 { |
345 | compatible = "rockchip,rk3288-i2c"; | |
79db45be | 346 | reg = <0x0 0xff140000 0x0 0x1000>; |
2ab557b7 HS |
347 | interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>; |
348 | #address-cells = <1>; | |
349 | #size-cells = <0>; | |
350 | clock-names = "i2c"; | |
351 | clocks = <&cru PCLK_I2C1>; | |
352 | pinctrl-names = "default"; | |
353 | pinctrl-0 = <&i2c1_xfer>; | |
354 | status = "disabled"; | |
355 | }; | |
356 | ||
357 | i2c3: i2c@ff150000 { | |
358 | compatible = "rockchip,rk3288-i2c"; | |
79db45be | 359 | reg = <0x0 0xff150000 0x0 0x1000>; |
2ab557b7 HS |
360 | interrupts = <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>; |
361 | #address-cells = <1>; | |
362 | #size-cells = <0>; | |
363 | clock-names = "i2c"; | |
364 | clocks = <&cru PCLK_I2C3>; | |
365 | pinctrl-names = "default"; | |
366 | pinctrl-0 = <&i2c3_xfer>; | |
367 | status = "disabled"; | |
368 | }; | |
369 | ||
370 | i2c4: i2c@ff160000 { | |
371 | compatible = "rockchip,rk3288-i2c"; | |
79db45be | 372 | reg = <0x0 0xff160000 0x0 0x1000>; |
2ab557b7 HS |
373 | interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>; |
374 | #address-cells = <1>; | |
375 | #size-cells = <0>; | |
376 | clock-names = "i2c"; | |
377 | clocks = <&cru PCLK_I2C4>; | |
378 | pinctrl-names = "default"; | |
379 | pinctrl-0 = <&i2c4_xfer>; | |
380 | status = "disabled"; | |
381 | }; | |
382 | ||
383 | i2c5: i2c@ff170000 { | |
384 | compatible = "rockchip,rk3288-i2c"; | |
79db45be | 385 | reg = <0x0 0xff170000 0x0 0x1000>; |
2ab557b7 HS |
386 | interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>; |
387 | #address-cells = <1>; | |
388 | #size-cells = <0>; | |
389 | clock-names = "i2c"; | |
390 | clocks = <&cru PCLK_I2C5>; | |
391 | pinctrl-names = "default"; | |
392 | pinctrl-0 = <&i2c5_xfer>; | |
393 | status = "disabled"; | |
394 | }; | |
395 | ||
396 | uart0: serial@ff180000 { | |
397 | compatible = "rockchip,rk3288-uart", "snps,dw-apb-uart"; | |
79db45be | 398 | reg = <0x0 0xff180000 0x0 0x100>; |
2ab557b7 HS |
399 | interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>; |
400 | reg-shift = <2>; | |
401 | reg-io-width = <4>; | |
402 | clocks = <&cru SCLK_UART0>, <&cru PCLK_UART0>; | |
403 | clock-names = "baudclk", "apb_pclk"; | |
404 | pinctrl-names = "default"; | |
405 | pinctrl-0 = <&uart0_xfer>; | |
406 | status = "disabled"; | |
407 | }; | |
408 | ||
409 | uart1: serial@ff190000 { | |
410 | compatible = "rockchip,rk3288-uart", "snps,dw-apb-uart"; | |
79db45be | 411 | reg = <0x0 0xff190000 0x0 0x100>; |
2ab557b7 HS |
412 | interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>; |
413 | reg-shift = <2>; | |
414 | reg-io-width = <4>; | |
415 | clocks = <&cru SCLK_UART1>, <&cru PCLK_UART1>; | |
416 | clock-names = "baudclk", "apb_pclk"; | |
417 | pinctrl-names = "default"; | |
418 | pinctrl-0 = <&uart1_xfer>; | |
419 | status = "disabled"; | |
420 | }; | |
421 | ||
422 | uart2: serial@ff690000 { | |
423 | compatible = "rockchip,rk3288-uart", "snps,dw-apb-uart"; | |
79db45be | 424 | reg = <0x0 0xff690000 0x0 0x100>; |
2ab557b7 HS |
425 | interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>; |
426 | reg-shift = <2>; | |
427 | reg-io-width = <4>; | |
428 | clocks = <&cru SCLK_UART2>, <&cru PCLK_UART2>; | |
429 | clock-names = "baudclk", "apb_pclk"; | |
430 | pinctrl-names = "default"; | |
431 | pinctrl-0 = <&uart2_xfer>; | |
432 | status = "disabled"; | |
433 | }; | |
434 | ||
435 | uart3: serial@ff1b0000 { | |
436 | compatible = "rockchip,rk3288-uart", "snps,dw-apb-uart"; | |
79db45be | 437 | reg = <0x0 0xff1b0000 0x0 0x100>; |
2ab557b7 HS |
438 | interrupts = <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>; |
439 | reg-shift = <2>; | |
440 | reg-io-width = <4>; | |
441 | clocks = <&cru SCLK_UART3>, <&cru PCLK_UART3>; | |
442 | clock-names = "baudclk", "apb_pclk"; | |
443 | pinctrl-names = "default"; | |
444 | pinctrl-0 = <&uart3_xfer>; | |
445 | status = "disabled"; | |
446 | }; | |
447 | ||
448 | uart4: serial@ff1c0000 { | |
449 | compatible = "rockchip,rk3288-uart", "snps,dw-apb-uart"; | |
79db45be | 450 | reg = <0x0 0xff1c0000 0x0 0x100>; |
2ab557b7 HS |
451 | interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>; |
452 | reg-shift = <2>; | |
453 | reg-io-width = <4>; | |
454 | clocks = <&cru SCLK_UART4>, <&cru PCLK_UART4>; | |
455 | clock-names = "baudclk", "apb_pclk"; | |
456 | pinctrl-names = "default"; | |
457 | pinctrl-0 = <&uart4_xfer>; | |
458 | status = "disabled"; | |
459 | }; | |
460 | ||
b67d6bc3 | 461 | thermal-zones { |
f87305fa CW |
462 | reserve_thermal: reserve_thermal { |
463 | polling-delay-passive = <1000>; /* milliseconds */ | |
464 | polling-delay = <5000>; /* milliseconds */ | |
465 | ||
466 | thermal-sensors = <&tsadc 0>; | |
467 | }; | |
468 | ||
469 | cpu_thermal: cpu_thermal { | |
470 | polling-delay-passive = <100>; /* milliseconds */ | |
471 | polling-delay = <5000>; /* milliseconds */ | |
472 | ||
473 | thermal-sensors = <&tsadc 1>; | |
474 | ||
475 | trips { | |
476 | cpu_alert0: cpu_alert0 { | |
477 | temperature = <70000>; /* millicelsius */ | |
478 | hysteresis = <2000>; /* millicelsius */ | |
479 | type = "passive"; | |
480 | }; | |
481 | cpu_alert1: cpu_alert1 { | |
482 | temperature = <75000>; /* millicelsius */ | |
483 | hysteresis = <2000>; /* millicelsius */ | |
484 | type = "passive"; | |
485 | }; | |
486 | cpu_crit: cpu_crit { | |
487 | temperature = <90000>; /* millicelsius */ | |
488 | hysteresis = <2000>; /* millicelsius */ | |
489 | type = "critical"; | |
490 | }; | |
491 | }; | |
492 | ||
493 | cooling-maps { | |
494 | map0 { | |
495 | trip = <&cpu_alert0>; | |
496 | cooling-device = | |
497 | <&cpu0 THERMAL_NO_LIMIT 6>; | |
498 | }; | |
499 | map1 { | |
500 | trip = <&cpu_alert1>; | |
501 | cooling-device = | |
502 | <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; | |
503 | }; | |
504 | }; | |
505 | }; | |
506 | ||
507 | gpu_thermal: gpu_thermal { | |
508 | polling-delay-passive = <100>; /* milliseconds */ | |
509 | polling-delay = <5000>; /* milliseconds */ | |
510 | ||
511 | thermal-sensors = <&tsadc 2>; | |
512 | ||
513 | trips { | |
514 | gpu_alert0: gpu_alert0 { | |
515 | temperature = <70000>; /* millicelsius */ | |
516 | hysteresis = <2000>; /* millicelsius */ | |
517 | type = "passive"; | |
518 | }; | |
519 | gpu_crit: gpu_crit { | |
520 | temperature = <90000>; /* millicelsius */ | |
521 | hysteresis = <2000>; /* millicelsius */ | |
522 | type = "critical"; | |
523 | }; | |
524 | }; | |
525 | ||
526 | cooling-maps { | |
527 | map0 { | |
528 | trip = <&gpu_alert0>; | |
529 | cooling-device = | |
530 | <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; | |
531 | }; | |
532 | }; | |
533 | }; | |
b67d6bc3 CW |
534 | }; |
535 | ||
536 | tsadc: tsadc@ff280000 { | |
537 | compatible = "rockchip,rk3288-tsadc"; | |
79db45be | 538 | reg = <0x0 0xff280000 0x0 0x100>; |
b67d6bc3 CW |
539 | interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>; |
540 | clocks = <&cru SCLK_TSADC>, <&cru PCLK_TSADC>; | |
541 | clock-names = "tsadc", "apb_pclk"; | |
542 | resets = <&cru SRST_TSADC>; | |
543 | reset-names = "tsadc-apb"; | |
784359b8 CW |
544 | pinctrl-names = "init", "default", "sleep"; |
545 | pinctrl-0 = <&otp_gpio>; | |
546 | pinctrl-1 = <&otp_out>; | |
547 | pinctrl-2 = <&otp_gpio>; | |
b67d6bc3 CW |
548 | #thermal-sensor-cells = <1>; |
549 | rockchip,hw-tshut-temp = <95000>; | |
550 | status = "disabled"; | |
551 | }; | |
552 | ||
3d3fb74a RC |
553 | gmac: ethernet@ff290000 { |
554 | compatible = "rockchip,rk3288-gmac"; | |
79db45be | 555 | reg = <0x0 0xff290000 0x0 0x10000>; |
d5bfbeb8 VP |
556 | interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>, |
557 | <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>; | |
558 | interrupt-names = "macirq", "eth_wake_irq"; | |
3d3fb74a RC |
559 | rockchip,grf = <&grf>; |
560 | clocks = <&cru SCLK_MAC>, | |
561 | <&cru SCLK_MAC_RX>, <&cru SCLK_MAC_TX>, | |
562 | <&cru SCLK_MACREF>, <&cru SCLK_MACREF_OUT>, | |
563 | <&cru ACLK_GMAC>, <&cru PCLK_GMAC>; | |
564 | clock-names = "stmmaceth", | |
565 | "mac_clk_rx", "mac_clk_tx", | |
566 | "clk_mac_ref", "clk_mac_refout", | |
567 | "aclk_mac", "pclk_mac"; | |
e6b54649 RP |
568 | resets = <&cru SRST_MAC>; |
569 | reset-names = "stmmaceth"; | |
54b0bc60 | 570 | status = "disabled"; |
3d3fb74a RC |
571 | }; |
572 | ||
c9c32c50 DA |
573 | usb_host0_ehci: usb@ff500000 { |
574 | compatible = "generic-ehci"; | |
79db45be | 575 | reg = <0x0 0xff500000 0x0 0x100>; |
c9c32c50 DA |
576 | interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>; |
577 | clocks = <&cru HCLK_USBHOST0>; | |
578 | clock-names = "usbhost"; | |
f6db7029 YL |
579 | phys = <&usbphy1>; |
580 | phy-names = "usb"; | |
c9c32c50 DA |
581 | status = "disabled"; |
582 | }; | |
583 | ||
584 | /* NOTE: ohci@ff520000 doesn't actually work on hardware */ | |
585 | ||
12dd3653 KY |
586 | usb_host1: usb@ff540000 { |
587 | compatible = "rockchip,rk3288-usb", "rockchip,rk3066-usb", | |
588 | "snps,dwc2"; | |
79db45be | 589 | reg = <0x0 0xff540000 0x0 0x40000>; |
12dd3653 KY |
590 | interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>; |
591 | clocks = <&cru HCLK_USBHOST1>; | |
592 | clock-names = "otg"; | |
cabd2ea2 | 593 | dr_mode = "host"; |
f6db7029 YL |
594 | phys = <&usbphy2>; |
595 | phy-names = "usb2-phy"; | |
12dd3653 KY |
596 | status = "disabled"; |
597 | }; | |
598 | ||
599 | usb_otg: usb@ff580000 { | |
600 | compatible = "rockchip,rk3288-usb", "rockchip,rk3066-usb", | |
601 | "snps,dwc2"; | |
79db45be | 602 | reg = <0x0 0xff580000 0x0 0x40000>; |
12dd3653 KY |
603 | interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>; |
604 | clocks = <&cru HCLK_OTG0>; | |
605 | clock-names = "otg"; | |
cabd2ea2 YL |
606 | dr_mode = "otg"; |
607 | g-np-tx-fifo-size = <16>; | |
608 | g-rx-fifo-size = <275>; | |
609 | g-tx-fifo-size = <256 128 128 64 64 32>; | |
f6db7029 YL |
610 | phys = <&usbphy0>; |
611 | phy-names = "usb2-phy"; | |
12dd3653 KY |
612 | status = "disabled"; |
613 | }; | |
614 | ||
c9c32c50 DA |
615 | usb_hsic: usb@ff5c0000 { |
616 | compatible = "generic-ehci"; | |
79db45be | 617 | reg = <0x0 0xff5c0000 0x0 0x100>; |
c9c32c50 DA |
618 | interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>; |
619 | clocks = <&cru HCLK_HSIC>; | |
620 | clock-names = "usbhost"; | |
621 | status = "disabled"; | |
622 | }; | |
623 | ||
2ab557b7 HS |
624 | i2c0: i2c@ff650000 { |
625 | compatible = "rockchip,rk3288-i2c"; | |
79db45be | 626 | reg = <0x0 0xff650000 0x0 0x1000>; |
2ab557b7 HS |
627 | interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>; |
628 | #address-cells = <1>; | |
629 | #size-cells = <0>; | |
630 | clock-names = "i2c"; | |
631 | clocks = <&cru PCLK_I2C0>; | |
632 | pinctrl-names = "default"; | |
633 | pinctrl-0 = <&i2c0_xfer>; | |
634 | status = "disabled"; | |
635 | }; | |
636 | ||
637 | i2c2: i2c@ff660000 { | |
638 | compatible = "rockchip,rk3288-i2c"; | |
79db45be | 639 | reg = <0x0 0xff660000 0x0 0x1000>; |
2ab557b7 HS |
640 | interrupts = <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>; |
641 | #address-cells = <1>; | |
642 | #size-cells = <0>; | |
643 | clock-names = "i2c"; | |
644 | clocks = <&cru PCLK_I2C2>; | |
645 | pinctrl-names = "default"; | |
646 | pinctrl-0 = <&i2c2_xfer>; | |
647 | status = "disabled"; | |
648 | }; | |
649 | ||
df542df3 DA |
650 | pwm0: pwm@ff680000 { |
651 | compatible = "rockchip,rk3288-pwm"; | |
79db45be | 652 | reg = <0x0 0xff680000 0x0 0x10>; |
df542df3 DA |
653 | #pwm-cells = <3>; |
654 | pinctrl-names = "default"; | |
655 | pinctrl-0 = <&pwm0_pin>; | |
656 | clocks = <&cru PCLK_PWM>; | |
657 | clock-names = "pwm"; | |
658 | status = "disabled"; | |
659 | }; | |
660 | ||
661 | pwm1: pwm@ff680010 { | |
662 | compatible = "rockchip,rk3288-pwm"; | |
79db45be | 663 | reg = <0x0 0xff680010 0x0 0x10>; |
df542df3 DA |
664 | #pwm-cells = <3>; |
665 | pinctrl-names = "default"; | |
666 | pinctrl-0 = <&pwm1_pin>; | |
667 | clocks = <&cru PCLK_PWM>; | |
668 | clock-names = "pwm"; | |
669 | status = "disabled"; | |
670 | }; | |
671 | ||
672 | pwm2: pwm@ff680020 { | |
673 | compatible = "rockchip,rk3288-pwm"; | |
79db45be | 674 | reg = <0x0 0xff680020 0x0 0x10>; |
df542df3 DA |
675 | #pwm-cells = <3>; |
676 | pinctrl-names = "default"; | |
677 | pinctrl-0 = <&pwm2_pin>; | |
678 | clocks = <&cru PCLK_PWM>; | |
679 | clock-names = "pwm"; | |
680 | status = "disabled"; | |
681 | }; | |
682 | ||
683 | pwm3: pwm@ff680030 { | |
684 | compatible = "rockchip,rk3288-pwm"; | |
79db45be | 685 | reg = <0x0 0xff680030 0x0 0x10>; |
df542df3 DA |
686 | #pwm-cells = <2>; |
687 | pinctrl-names = "default"; | |
688 | pinctrl-0 = <&pwm3_pin>; | |
689 | clocks = <&cru PCLK_PWM>; | |
690 | clock-names = "pwm"; | |
691 | status = "disabled"; | |
692 | }; | |
693 | ||
1123d412 KY |
694 | bus_intmem@ff700000 { |
695 | compatible = "mmio-sram"; | |
79db45be | 696 | reg = <0x0 0xff700000 0x0 0x18000>; |
1123d412 KY |
697 | #address-cells = <1>; |
698 | #size-cells = <1>; | |
79db45be | 699 | ranges = <0 0x0 0xff700000 0x18000>; |
1123d412 KY |
700 | smp-sram@0 { |
701 | compatible = "rockchip,rk3066-smp-sram"; | |
702 | reg = <0x00 0x10>; | |
703 | }; | |
704 | }; | |
705 | ||
eecfe981 CZ |
706 | sram@ff720000 { |
707 | compatible = "rockchip,rk3288-pmu-sram", "mmio-sram"; | |
79db45be | 708 | reg = <0x0 0xff720000 0x0 0x1000>; |
eecfe981 CZ |
709 | }; |
710 | ||
2ab557b7 | 711 | pmu: power-management@ff730000 { |
b63af764 | 712 | compatible = "rockchip,rk3288-pmu", "syscon", "simple-mfd"; |
79db45be | 713 | reg = <0x0 0xff730000 0x0 0x100>; |
b63af764 CW |
714 | |
715 | power: power-controller { | |
716 | compatible = "rockchip,rk3288-power-controller"; | |
717 | #power-domain-cells = <1>; | |
718 | #address-cells = <1>; | |
719 | #size-cells = <0>; | |
720 | ||
df5ea015 SS |
721 | assigned-clocks = <&cru SCLK_EDP_24M>; |
722 | assigned-clock-parents = <&xin24m>; | |
723 | ||
b63af764 CW |
724 | /* |
725 | * Note: Although SCLK_* are the working clocks | |
726 | * of device without including on the NOC, needed for | |
727 | * synchronous reset. | |
728 | * | |
729 | * The clocks on the which NOC: | |
730 | * ACLK_IEP/ACLK_VIP/ACLK_VOP0 are on ACLK_VIO0_NIU. | |
731 | * ACLK_ISP/ACLK_VOP1 are on ACLK_VIO1_NIU. | |
732 | * ACLK_RGA is on ACLK_RGA_NIU. | |
733 | * The others (HCLK_*,PLCK_*) are on HCLK_VIO_NIU. | |
734 | * | |
735 | * Which clock are device clocks: | |
736 | * clocks devices | |
737 | * *_IEP IEP:Image Enhancement Processor | |
738 | * *_ISP ISP:Image Signal Processing | |
739 | * *_VIP VIP:Video Input Processor | |
740 | * *_VOP* VOP:Visual Output Processor | |
741 | * *_RGA RGA | |
742 | * *_EDP* EDP | |
743 | * *_LVDS_* LVDS | |
744 | * *_HDMI HDMI | |
745 | * *_MIPI_* MIPI | |
746 | */ | |
95cface9 | 747 | pd_vio@RK3288_PD_VIO { |
b63af764 CW |
748 | reg = <RK3288_PD_VIO>; |
749 | clocks = <&cru ACLK_IEP>, | |
750 | <&cru ACLK_ISP>, | |
751 | <&cru ACLK_RGA>, | |
752 | <&cru ACLK_VIP>, | |
753 | <&cru ACLK_VOP0>, | |
754 | <&cru ACLK_VOP1>, | |
755 | <&cru DCLK_VOP0>, | |
756 | <&cru DCLK_VOP1>, | |
757 | <&cru HCLK_IEP>, | |
758 | <&cru HCLK_ISP>, | |
759 | <&cru HCLK_RGA>, | |
760 | <&cru HCLK_VIP>, | |
761 | <&cru HCLK_VOP0>, | |
762 | <&cru HCLK_VOP1>, | |
763 | <&cru PCLK_EDP_CTRL>, | |
764 | <&cru PCLK_HDMI_CTRL>, | |
765 | <&cru PCLK_LVDS_PHY>, | |
766 | <&cru PCLK_MIPI_CSI>, | |
767 | <&cru PCLK_MIPI_DSI0>, | |
768 | <&cru PCLK_MIPI_DSI1>, | |
769 | <&cru SCLK_EDP_24M>, | |
770 | <&cru SCLK_EDP>, | |
771 | <&cru SCLK_ISP_JPE>, | |
772 | <&cru SCLK_ISP>, | |
773 | <&cru SCLK_RGA>; | |
0af13f70 EZ |
774 | pm_qos = <&qos_vio0_iep>, |
775 | <&qos_vio1_vop>, | |
776 | <&qos_vio1_isp_w0>, | |
777 | <&qos_vio1_isp_w1>, | |
778 | <&qos_vio0_vop>, | |
779 | <&qos_vio0_vip>, | |
780 | <&qos_vio2_rga_r>, | |
781 | <&qos_vio2_rga_w>, | |
782 | <&qos_vio1_isp_r>; | |
b63af764 CW |
783 | }; |
784 | ||
785 | /* | |
786 | * Note: The following 3 are HEVC(H.265) clocks, | |
787 | * and on the ACLK_HEVC_NIU (NOC). | |
788 | */ | |
95cface9 | 789 | pd_hevc@RK3288_PD_HEVC { |
b63af764 CW |
790 | reg = <RK3288_PD_HEVC>; |
791 | clocks = <&cru ACLK_HEVC>, | |
792 | <&cru SCLK_HEVC_CABAC>, | |
793 | <&cru SCLK_HEVC_CORE>; | |
0af13f70 EZ |
794 | pm_qos = <&qos_hevc_r>, |
795 | <&qos_hevc_w>; | |
b63af764 CW |
796 | }; |
797 | ||
798 | /* | |
799 | * Note: ACLK_VCODEC/HCLK_VCODEC are VCODEC | |
800 | * (video endecoder & decoder) clocks that on the | |
801 | * ACLK_VCODEC_NIU and HCLK_VCODEC_NIU (NOC). | |
802 | */ | |
95cface9 | 803 | pd_video@RK3288_PD_VIDEO { |
b63af764 CW |
804 | reg = <RK3288_PD_VIDEO>; |
805 | clocks = <&cru ACLK_VCODEC>, | |
806 | <&cru HCLK_VCODEC>; | |
0af13f70 | 807 | pm_qos = <&qos_video>; |
b63af764 CW |
808 | }; |
809 | ||
810 | /* | |
811 | * Note: ACLK_GPU is the GPU clock, | |
812 | * and on the ACLK_GPU_NIU (NOC). | |
813 | */ | |
95cface9 | 814 | pd_gpu@RK3288_PD_GPU { |
b63af764 CW |
815 | reg = <RK3288_PD_GPU>; |
816 | clocks = <&cru ACLK_GPU>; | |
0af13f70 EZ |
817 | pm_qos = <&qos_gpu_r>, |
818 | <&qos_gpu_w>; | |
b63af764 CW |
819 | }; |
820 | }; | |
b60ab70b AY |
821 | |
822 | reboot-mode { | |
823 | compatible = "syscon-reboot-mode"; | |
824 | offset = <0x94>; | |
825 | mode-normal = <BOOT_NORMAL>; | |
826 | mode-recovery = <BOOT_RECOVERY>; | |
827 | mode-bootloader = <BOOT_FASTBOOT>; | |
828 | mode-loader = <BOOT_BL_DOWNLOAD>; | |
829 | }; | |
2ab557b7 HS |
830 | }; |
831 | ||
832 | sgrf: syscon@ff740000 { | |
833 | compatible = "rockchip,rk3288-sgrf", "syscon"; | |
79db45be | 834 | reg = <0x0 0xff740000 0x0 0x1000>; |
2ab557b7 HS |
835 | }; |
836 | ||
837 | cru: clock-controller@ff760000 { | |
838 | compatible = "rockchip,rk3288-cru"; | |
79db45be | 839 | reg = <0x0 0xff760000 0x0 0x1000>; |
2ab557b7 HS |
840 | rockchip,grf = <&grf>; |
841 | #clock-cells = <1>; | |
842 | #reset-cells = <1>; | |
cd78d0cd KY |
843 | assigned-clocks = <&cru PLL_GPLL>, <&cru PLL_CPLL>, |
844 | <&cru PLL_NPLL>, <&cru ACLK_CPU>, | |
845 | <&cru HCLK_CPU>, <&cru PCLK_CPU>, | |
846 | <&cru ACLK_PERI>, <&cru HCLK_PERI>, | |
847 | <&cru PCLK_PERI>; | |
848 | assigned-clock-rates = <594000000>, <400000000>, | |
849 | <500000000>, <300000000>, | |
850 | <150000000>, <75000000>, | |
851 | <300000000>, <150000000>, | |
852 | <75000000>; | |
2ab557b7 HS |
853 | }; |
854 | ||
855 | grf: syscon@ff770000 { | |
6e38e6b2 | 856 | compatible = "rockchip,rk3288-grf", "syscon", "simple-mfd"; |
79db45be | 857 | reg = <0x0 0xff770000 0x0 0x1000>; |
4b915450 HS |
858 | |
859 | edp_phy: edp-phy { | |
860 | compatible = "rockchip,rk3288-dp-phy"; | |
861 | clocks = <&cru SCLK_EDP_24M>; | |
862 | clock-names = "24m"; | |
863 | #phy-cells = <0>; | |
864 | status = "disabled"; | |
865 | }; | |
3445b2fa HS |
866 | |
867 | io_domains: io-domains { | |
868 | compatible = "rockchip,rk3288-io-voltage-domain"; | |
869 | status = "disabled"; | |
870 | }; | |
546a3521 HS |
871 | |
872 | usbphy: usbphy { | |
873 | compatible = "rockchip,rk3288-usb-phy"; | |
874 | #address-cells = <1>; | |
875 | #size-cells = <0>; | |
876 | status = "disabled"; | |
877 | ||
878 | usbphy0: usb-phy@320 { | |
879 | #phy-cells = <0>; | |
880 | reg = <0x320>; | |
881 | clocks = <&cru SCLK_OTGPHY0>; | |
882 | clock-names = "phyclk"; | |
883 | #clock-cells = <0>; | |
884 | }; | |
885 | ||
886 | usbphy1: usb-phy@334 { | |
887 | #phy-cells = <0>; | |
888 | reg = <0x334>; | |
889 | clocks = <&cru SCLK_OTGPHY1>; | |
890 | clock-names = "phyclk"; | |
891 | #clock-cells = <0>; | |
892 | }; | |
893 | ||
894 | usbphy2: usb-phy@348 { | |
895 | #phy-cells = <0>; | |
896 | reg = <0x348>; | |
897 | clocks = <&cru SCLK_OTGPHY2>; | |
898 | clock-names = "phyclk"; | |
899 | #clock-cells = <0>; | |
900 | }; | |
901 | }; | |
2ab557b7 HS |
902 | }; |
903 | ||
904 | wdt: watchdog@ff800000 { | |
905 | compatible = "rockchip,rk3288-wdt", "snps,dw-wdt"; | |
79db45be | 906 | reg = <0x0 0xff800000 0x0 0x100>; |
39d05162 | 907 | clocks = <&cru PCLK_WDT>; |
1a1b698b | 908 | interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>; |
2ab557b7 HS |
909 | status = "disabled"; |
910 | }; | |
911 | ||
874e568e SS |
912 | spdif: sound@ff88b0000 { |
913 | compatible = "rockchip,rk3288-spdif", "rockchip,rk3066-spdif"; | |
79db45be | 914 | reg = <0x0 0xff8b0000 0x0 0x10000>; |
874e568e SS |
915 | #sound-dai-cells = <0>; |
916 | clock-names = "hclk", "mclk"; | |
917 | clocks = <&cru HCLK_SPDIF8CH>, <&cru SCLK_SPDIF8CH>; | |
918 | dmas = <&dmac_bus_s 3>; | |
919 | dma-names = "tx"; | |
57dcfa56 | 920 | interrupts = <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>; |
874e568e SS |
921 | pinctrl-names = "default"; |
922 | pinctrl-0 = <&spdif_tx>; | |
923 | rockchip,grf = <&grf>; | |
924 | status = "disabled"; | |
925 | }; | |
926 | ||
a0f95e35 J |
927 | i2s: i2s@ff890000 { |
928 | compatible = "rockchip,rk3288-i2s", "rockchip,rk3066-i2s"; | |
79db45be | 929 | reg = <0x0 0xff890000 0x0 0x10000>; |
57dcfa56 | 930 | interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>; |
a0f95e35 J |
931 | #address-cells = <1>; |
932 | #size-cells = <0>; | |
933 | dmas = <&dmac_bus_s 0>, <&dmac_bus_s 1>; | |
934 | dma-names = "tx", "rx"; | |
935 | clock-names = "i2s_hclk", "i2s_clk"; | |
936 | clocks = <&cru HCLK_I2S0>, <&cru SCLK_I2S0>; | |
937 | pinctrl-names = "default"; | |
938 | pinctrl-0 = <&i2s0_bus>; | |
e241657d SZ |
939 | rockchip,playback-channels = <8>; |
940 | rockchip,capture-channels = <2>; | |
a0f95e35 J |
941 | status = "disabled"; |
942 | }; | |
943 | ||
c2cb6161 ZW |
944 | crypto: cypto-controller@ff8a0000 { |
945 | compatible = "rockchip,rk3288-crypto"; | |
79db45be | 946 | reg = <0x0 0xff8a0000 0x0 0x4000>; |
c2cb6161 ZW |
947 | interrupts = <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>; |
948 | clocks = <&cru ACLK_CRYPTO>, <&cru HCLK_CRYPTO>, | |
949 | <&cru SCLK_CRYPTO>, <&cru ACLK_DMAC1>; | |
950 | clock-names = "aclk", "hclk", "sclk", "apb_pclk"; | |
951 | resets = <&cru SRST_CRYPTO>; | |
952 | reset-names = "crypto-rst"; | |
953 | status = "okay"; | |
954 | }; | |
955 | ||
1cc47e63 SX |
956 | iep_mmu: iommu@ff900800 { |
957 | compatible = "rockchip,iommu"; | |
958 | reg = <0x0 0xff900800 0x0 0x40>; | |
959 | interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH 0>; | |
960 | interrupt-names = "iep_mmu"; | |
961 | #iommu-cells = <0>; | |
962 | status = "disabled"; | |
963 | }; | |
964 | ||
965 | isp_mmu: iommu@ff914000 { | |
966 | compatible = "rockchip,iommu"; | |
967 | reg = <0x0 0xff914000 0x0 0x100>, <0x0 0xff915000 0x0 0x100>; | |
968 | interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>; | |
969 | interrupt-names = "isp_mmu"; | |
970 | #iommu-cells = <0>; | |
971 | rockchip,disable-mmu-reset; | |
972 | status = "disabled"; | |
973 | }; | |
974 | ||
a29cb8c4 DK |
975 | vopb: vop@ff930000 { |
976 | compatible = "rockchip,rk3288-vop"; | |
79db45be | 977 | reg = <0x0 0xff930000 0x0 0x19c>; |
a29cb8c4 DK |
978 | interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>; |
979 | clocks = <&cru ACLK_VOP0>, <&cru DCLK_VOP0>, <&cru HCLK_VOP0>; | |
980 | clock-names = "aclk_vop", "dclk_vop", "hclk_vop"; | |
b63af764 | 981 | power-domains = <&power RK3288_PD_VIO>; |
a29cb8c4 DK |
982 | resets = <&cru SRST_LCDC0_AXI>, <&cru SRST_LCDC0_AHB>, <&cru SRST_LCDC0_DCLK>; |
983 | reset-names = "axi", "ahb", "dclk"; | |
984 | iommus = <&vopb_mmu>; | |
985 | status = "disabled"; | |
986 | ||
987 | vopb_out: port { | |
988 | #address-cells = <1>; | |
989 | #size-cells = <0>; | |
d5a1df48 AY |
990 | |
991 | vopb_out_hdmi: endpoint@0 { | |
992 | reg = <0>; | |
993 | remote-endpoint = <&hdmi_in_vopb>; | |
994 | }; | |
6df7ec61 HS |
995 | |
996 | vopb_out_edp: endpoint@1 { | |
997 | reg = <1>; | |
998 | remote-endpoint = <&edp_in_vopb>; | |
999 | }; | |
1000 | ||
cab6f070 CZ |
1001 | vopb_out_mipi: endpoint@2 { |
1002 | reg = <2>; | |
1003 | remote-endpoint = <&mipi_in_vopb>; | |
1004 | }; | |
316ffa32 SH |
1005 | |
1006 | vopb_out_lvds: endpoint@3 { | |
1007 | reg = <3>; | |
1008 | remote-endpoint = <&lvds_in_vopb>; | |
1009 | }; | |
a29cb8c4 DK |
1010 | }; |
1011 | }; | |
1012 | ||
7cae068b DK |
1013 | vopb_mmu: iommu@ff930300 { |
1014 | compatible = "rockchip,iommu"; | |
79db45be | 1015 | reg = <0x0 0xff930300 0x0 0x100>; |
7cae068b DK |
1016 | interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>; |
1017 | interrupt-names = "vopb_mmu"; | |
b63af764 | 1018 | power-domains = <&power RK3288_PD_VIO>; |
7cae068b DK |
1019 | #iommu-cells = <0>; |
1020 | status = "disabled"; | |
1021 | }; | |
1022 | ||
a29cb8c4 DK |
1023 | vopl: vop@ff940000 { |
1024 | compatible = "rockchip,rk3288-vop"; | |
79db45be | 1025 | reg = <0x0 0xff940000 0x0 0x19c>; |
a29cb8c4 DK |
1026 | interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>; |
1027 | clocks = <&cru ACLK_VOP1>, <&cru DCLK_VOP1>, <&cru HCLK_VOP1>; | |
1028 | clock-names = "aclk_vop", "dclk_vop", "hclk_vop"; | |
b63af764 | 1029 | power-domains = <&power RK3288_PD_VIO>; |
a29cb8c4 DK |
1030 | resets = <&cru SRST_LCDC1_AXI>, <&cru SRST_LCDC1_AHB>, <&cru SRST_LCDC1_DCLK>; |
1031 | reset-names = "axi", "ahb", "dclk"; | |
1032 | iommus = <&vopl_mmu>; | |
1033 | status = "disabled"; | |
1034 | ||
1035 | vopl_out: port { | |
1036 | #address-cells = <1>; | |
1037 | #size-cells = <0>; | |
d5a1df48 AY |
1038 | |
1039 | vopl_out_hdmi: endpoint@0 { | |
1040 | reg = <0>; | |
1041 | remote-endpoint = <&hdmi_in_vopl>; | |
1042 | }; | |
6df7ec61 HS |
1043 | |
1044 | vopl_out_edp: endpoint@1 { | |
1045 | reg = <1>; | |
1046 | remote-endpoint = <&edp_in_vopl>; | |
1047 | }; | |
1048 | ||
cab6f070 CZ |
1049 | vopl_out_mipi: endpoint@2 { |
1050 | reg = <2>; | |
1051 | remote-endpoint = <&mipi_in_vopl>; | |
1052 | }; | |
316ffa32 SH |
1053 | |
1054 | vopl_out_lvds: endpoint@3 { | |
1055 | reg = <3>; | |
1056 | remote-endpoint = <&lvds_in_vopl>; | |
1057 | }; | |
a29cb8c4 DK |
1058 | }; |
1059 | }; | |
1060 | ||
7cae068b DK |
1061 | vopl_mmu: iommu@ff940300 { |
1062 | compatible = "rockchip,iommu"; | |
79db45be | 1063 | reg = <0x0 0xff940300 0x0 0x100>; |
7cae068b DK |
1064 | interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>; |
1065 | interrupt-names = "vopl_mmu"; | |
b63af764 | 1066 | power-domains = <&power RK3288_PD_VIO>; |
7cae068b DK |
1067 | #iommu-cells = <0>; |
1068 | status = "disabled"; | |
1069 | }; | |
1070 | ||
cab6f070 CZ |
1071 | mipi_dsi: mipi@ff960000 { |
1072 | compatible = "rockchip,rk3288-mipi-dsi", "snps,dw-mipi-dsi"; | |
79db45be | 1073 | reg = <0x0 0xff960000 0x0 0x4000>; |
5415ba40 | 1074 | interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>; |
cab6f070 CZ |
1075 | clocks = <&cru SCLK_MIPIDSI_24M>, <&cru PCLK_MIPI_DSI0>; |
1076 | clock-names = "ref", "pclk"; | |
1946a201 | 1077 | power-domains = <&power RK3288_PD_VIO>; |
cab6f070 CZ |
1078 | rockchip,grf = <&grf>; |
1079 | #address-cells = <1>; | |
1080 | #size-cells = <0>; | |
1081 | status = "disabled"; | |
1082 | ||
1083 | ports { | |
cab6f070 CZ |
1084 | mipi_in: port { |
1085 | #address-cells = <1>; | |
1086 | #size-cells = <0>; | |
1087 | mipi_in_vopb: endpoint@0 { | |
1088 | reg = <0>; | |
1089 | remote-endpoint = <&vopb_out_mipi>; | |
1090 | }; | |
1091 | mipi_in_vopl: endpoint@1 { | |
1092 | reg = <1>; | |
1093 | remote-endpoint = <&vopl_out_mipi>; | |
1094 | }; | |
1095 | }; | |
1096 | }; | |
1097 | }; | |
1098 | ||
316ffa32 SH |
1099 | lvds: lvds@ff96c000 { |
1100 | compatible = "rockchip,rk3288-lvds"; | |
1101 | reg = <0x0 0xff96c000 0x0 0x4000>; | |
1102 | clocks = <&cru PCLK_LVDS_PHY>; | |
1103 | clock-names = "pclk_lvds"; | |
1104 | pinctrl-names = "lcdc"; | |
1105 | pinctrl-0 = <&lcdc_ctl>; | |
1106 | power-domains = <&power RK3288_PD_VIO>; | |
1107 | rockchip,grf = <&grf>; | |
1108 | status = "disabled"; | |
1109 | ||
1110 | ports { | |
1111 | #address-cells = <1>; | |
1112 | #size-cells = <0>; | |
1113 | ||
1114 | lvds_in: port@0 { | |
1115 | reg = <0>; | |
1116 | ||
1117 | #address-cells = <1>; | |
1118 | #size-cells = <0>; | |
1119 | ||
1120 | lvds_in_vopb: endpoint@0 { | |
1121 | reg = <0>; | |
1122 | remote-endpoint = <&vopb_out_lvds>; | |
1123 | }; | |
1124 | lvds_in_vopl: endpoint@1 { | |
1125 | reg = <1>; | |
1126 | remote-endpoint = <&vopl_out_lvds>; | |
1127 | }; | |
1128 | }; | |
1129 | }; | |
1130 | }; | |
1131 | ||
6df7ec61 HS |
1132 | edp: dp@ff970000 { |
1133 | compatible = "rockchip,rk3288-dp"; | |
79db45be | 1134 | reg = <0x0 0xff970000 0x0 0x4000>; |
6df7ec61 HS |
1135 | interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>; |
1136 | clocks = <&cru SCLK_EDP>, <&cru PCLK_EDP_CTRL>; | |
1137 | clock-names = "dp", "pclk"; | |
1138 | phys = <&edp_phy>; | |
1139 | phy-names = "dp"; | |
1140 | resets = <&cru SRST_EDP>; | |
1141 | reset-names = "dp"; | |
1142 | rockchip,grf = <&grf>; | |
1143 | status = "disabled"; | |
1144 | ||
1145 | ports { | |
1146 | #address-cells = <1>; | |
1147 | #size-cells = <0>; | |
1148 | edp_in: port@0 { | |
1149 | reg = <0>; | |
1150 | #address-cells = <1>; | |
1151 | #size-cells = <0>; | |
1152 | edp_in_vopb: endpoint@0 { | |
1153 | reg = <0>; | |
1154 | remote-endpoint = <&vopb_out_edp>; | |
1155 | }; | |
1156 | edp_in_vopl: endpoint@1 { | |
1157 | reg = <1>; | |
1158 | remote-endpoint = <&vopl_out_edp>; | |
1159 | }; | |
1160 | }; | |
1161 | }; | |
1162 | }; | |
1163 | ||
d5a1df48 AY |
1164 | hdmi: hdmi@ff980000 { |
1165 | compatible = "rockchip,rk3288-dw-hdmi"; | |
79db45be | 1166 | reg = <0x0 0xff980000 0x0 0x20000>; |
d5a1df48 | 1167 | reg-io-width = <4>; |
d5a1df48 AY |
1168 | rockchip,grf = <&grf>; |
1169 | interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>; | |
1170 | clocks = <&cru PCLK_HDMI_CTRL>, <&cru SCLK_HDMI_HDCP>; | |
1171 | clock-names = "iahb", "isfr"; | |
b63af764 | 1172 | power-domains = <&power RK3288_PD_VIO>; |
d5a1df48 AY |
1173 | status = "disabled"; |
1174 | ||
1175 | ports { | |
1176 | hdmi_in: port { | |
1177 | #address-cells = <1>; | |
1178 | #size-cells = <0>; | |
1179 | hdmi_in_vopb: endpoint@0 { | |
1180 | reg = <0>; | |
1181 | remote-endpoint = <&vopb_out_hdmi>; | |
1182 | }; | |
1183 | hdmi_in_vopl: endpoint@1 { | |
1184 | reg = <1>; | |
1185 | remote-endpoint = <&vopl_out_hdmi>; | |
1186 | }; | |
1187 | }; | |
1188 | }; | |
1189 | }; | |
1190 | ||
1cc47e63 SX |
1191 | vpu_mmu: iommu@ff9a0800 { |
1192 | compatible = "rockchip,iommu"; | |
1193 | reg = <0x0 0xff9a0800 0x0 0x100>; | |
1194 | interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>; | |
1195 | interrupt-names = "vpu_mmu"; | |
1196 | #iommu-cells = <0>; | |
1197 | status = "disabled"; | |
1198 | }; | |
1199 | ||
1200 | hevc_mmu: iommu@ff9c0440 { | |
1201 | compatible = "rockchip,iommu"; | |
1202 | reg = <0x0 0xff9c0440 0x0 0x40>, <0x0 0xff9c0480 0x0 0x40>; | |
1203 | interrupts = <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>; | |
1204 | interrupt-names = "hevc_mmu"; | |
1205 | #iommu-cells = <0>; | |
1206 | status = "disabled"; | |
1207 | }; | |
1208 | ||
ca124373 HS |
1209 | gpu: gpu@ffa30000 { |
1210 | compatible = "rockchip,rk3288-mali", "arm,mali-t760"; | |
79db45be | 1211 | reg = <0x0 0xffa30000 0x0 0x10000>; |
e3df026c GT |
1212 | interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>, |
1213 | <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>, | |
1214 | <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>; | |
1215 | interrupt-names = "job", "mmu", "gpu"; | |
1216 | clocks = <&cru ACLK_GPU>; | |
1217 | operating-points-v2 = <&gpu_opp_table>; | |
1218 | power-domains = <&power RK3288_PD_GPU>; | |
1219 | status = "disabled"; | |
1220 | }; | |
1221 | ||
1222 | gpu_opp_table: gpu-opp-table { | |
1223 | compatible = "operating-points-v2"; | |
1224 | ||
1225 | opp@100000000 { | |
1226 | opp-hz = /bits/ 64 <100000000>; | |
1227 | opp-microvolt = <950000>; | |
1228 | }; | |
1229 | opp@200000000 { | |
1230 | opp-hz = /bits/ 64 <200000000>; | |
1231 | opp-microvolt = <950000>; | |
1232 | }; | |
1233 | opp@300000000 { | |
1234 | opp-hz = /bits/ 64 <300000000>; | |
1235 | opp-microvolt = <1000000>; | |
1236 | }; | |
1237 | opp@400000000 { | |
1238 | opp-hz = /bits/ 64 <400000000>; | |
1239 | opp-microvolt = <1100000>; | |
1240 | }; | |
1241 | opp@500000000 { | |
1242 | opp-hz = /bits/ 64 <500000000>; | |
1243 | opp-microvolt = <1200000>; | |
1244 | }; | |
1245 | opp@600000000 { | |
1246 | opp-hz = /bits/ 64 <600000000>; | |
1247 | opp-microvolt = <1250000>; | |
1248 | }; | |
1249 | }; | |
1250 | ||
0af13f70 EZ |
1251 | qos_gpu_r: qos@ffaa0000 { |
1252 | compatible = "syscon"; | |
79db45be | 1253 | reg = <0x0 0xffaa0000 0x0 0x20>; |
0af13f70 EZ |
1254 | }; |
1255 | ||
1256 | qos_gpu_w: qos@ffaa0080 { | |
1257 | compatible = "syscon"; | |
79db45be | 1258 | reg = <0x0 0xffaa0080 0x0 0x20>; |
0af13f70 EZ |
1259 | }; |
1260 | ||
1261 | qos_vio1_vop: qos@ffad0000 { | |
1262 | compatible = "syscon"; | |
79db45be | 1263 | reg = <0x0 0xffad0000 0x0 0x20>; |
0af13f70 EZ |
1264 | }; |
1265 | ||
1266 | qos_vio1_isp_w0: qos@ffad0100 { | |
1267 | compatible = "syscon"; | |
79db45be | 1268 | reg = <0x0 0xffad0100 0x0 0x20>; |
0af13f70 EZ |
1269 | }; |
1270 | ||
1271 | qos_vio1_isp_w1: qos@ffad0180 { | |
1272 | compatible = "syscon"; | |
79db45be | 1273 | reg = <0x0 0xffad0180 0x0 0x20>; |
0af13f70 EZ |
1274 | }; |
1275 | ||
1276 | qos_vio0_vop: qos@ffad0400 { | |
1277 | compatible = "syscon"; | |
79db45be | 1278 | reg = <0x0 0xffad0400 0x0 0x20>; |
0af13f70 EZ |
1279 | }; |
1280 | ||
1281 | qos_vio0_vip: qos@ffad0480 { | |
1282 | compatible = "syscon"; | |
79db45be | 1283 | reg = <0x0 0xffad0480 0x0 0x20>; |
0af13f70 EZ |
1284 | }; |
1285 | ||
1286 | qos_vio0_iep: qos@ffad0500 { | |
1287 | compatible = "syscon"; | |
79db45be | 1288 | reg = <0x0 0xffad0500 0x0 0x20>; |
0af13f70 EZ |
1289 | }; |
1290 | ||
1291 | qos_vio2_rga_r: qos@ffad0800 { | |
1292 | compatible = "syscon"; | |
79db45be | 1293 | reg = <0x0 0xffad0800 0x0 0x20>; |
0af13f70 EZ |
1294 | }; |
1295 | ||
1296 | qos_vio2_rga_w: qos@ffad0880 { | |
1297 | compatible = "syscon"; | |
79db45be | 1298 | reg = <0x0 0xffad0880 0x0 0x20>; |
0af13f70 EZ |
1299 | }; |
1300 | ||
1301 | qos_vio1_isp_r: qos@ffad0900 { | |
1302 | compatible = "syscon"; | |
79db45be | 1303 | reg = <0x0 0xffad0900 0x0 0x20>; |
0af13f70 EZ |
1304 | }; |
1305 | ||
1306 | qos_video: qos@ffae0000 { | |
1307 | compatible = "syscon"; | |
79db45be | 1308 | reg = <0x0 0xffae0000 0x0 0x20>; |
0af13f70 EZ |
1309 | }; |
1310 | ||
1311 | qos_hevc_r: qos@ffaf0000 { | |
1312 | compatible = "syscon"; | |
79db45be | 1313 | reg = <0x0 0xffaf0000 0x0 0x20>; |
0af13f70 EZ |
1314 | }; |
1315 | ||
1316 | qos_hevc_w: qos@ffaf0080 { | |
1317 | compatible = "syscon"; | |
79db45be | 1318 | reg = <0x0 0xffaf0080 0x0 0x20>; |
0af13f70 EZ |
1319 | }; |
1320 | ||
2ab557b7 HS |
1321 | gic: interrupt-controller@ffc01000 { |
1322 | compatible = "arm,gic-400"; | |
1323 | interrupt-controller; | |
1324 | #interrupt-cells = <3>; | |
1325 | #address-cells = <0>; | |
1326 | ||
79db45be TH |
1327 | reg = <0x0 0xffc01000 0x0 0x1000>, |
1328 | <0x0 0xffc02000 0x0 0x2000>, | |
1329 | <0x0 0xffc04000 0x0 0x2000>, | |
1330 | <0x0 0xffc06000 0x0 0x2000>; | |
2ab557b7 HS |
1331 | interrupts = <GIC_PPI 9 0xf04>; |
1332 | }; | |
1333 | ||
88185559 | 1334 | efuse: efuse@ffb40000 { |
85b72602 | 1335 | compatible = "rockchip,rk3288-efuse"; |
79db45be | 1336 | reg = <0x0 0xffb40000 0x0 0x20>; |
88185559 Z |
1337 | #address-cells = <1>; |
1338 | #size-cells = <1>; | |
1339 | clocks = <&cru PCLK_EFUSE256>; | |
1340 | clock-names = "pclk_efuse"; | |
1341 | ||
1342 | cpu_leakage: cpu_leakage@17 { | |
1343 | reg = <0x17 0x1>; | |
1344 | }; | |
1345 | }; | |
1346 | ||
2ab557b7 HS |
1347 | pinctrl: pinctrl { |
1348 | compatible = "rockchip,rk3288-pinctrl"; | |
1349 | rockchip,grf = <&grf>; | |
1350 | rockchip,pmu = <&pmu>; | |
79db45be TH |
1351 | #address-cells = <2>; |
1352 | #size-cells = <2>; | |
2ab557b7 HS |
1353 | ranges; |
1354 | ||
1355 | gpio0: gpio0@ff750000 { | |
1356 | compatible = "rockchip,gpio-bank"; | |
79db45be | 1357 | reg = <0x0 0xff750000 0x0 0x100>; |
2ab557b7 HS |
1358 | interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>; |
1359 | clocks = <&cru PCLK_GPIO0>; | |
1360 | ||
1361 | gpio-controller; | |
1362 | #gpio-cells = <2>; | |
1363 | ||
1364 | interrupt-controller; | |
1365 | #interrupt-cells = <2>; | |
1366 | }; | |
1367 | ||
1368 | gpio1: gpio1@ff780000 { | |
1369 | compatible = "rockchip,gpio-bank"; | |
79db45be | 1370 | reg = <0x0 0xff780000 0x0 0x100>; |
2ab557b7 HS |
1371 | interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>; |
1372 | clocks = <&cru PCLK_GPIO1>; | |
1373 | ||
1374 | gpio-controller; | |
1375 | #gpio-cells = <2>; | |
1376 | ||
1377 | interrupt-controller; | |
1378 | #interrupt-cells = <2>; | |
1379 | }; | |
1380 | ||
1381 | gpio2: gpio2@ff790000 { | |
1382 | compatible = "rockchip,gpio-bank"; | |
79db45be | 1383 | reg = <0x0 0xff790000 0x0 0x100>; |
2ab557b7 HS |
1384 | interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>; |
1385 | clocks = <&cru PCLK_GPIO2>; | |
1386 | ||
1387 | gpio-controller; | |
1388 | #gpio-cells = <2>; | |
1389 | ||
1390 | interrupt-controller; | |
1391 | #interrupt-cells = <2>; | |
1392 | }; | |
1393 | ||
1394 | gpio3: gpio3@ff7a0000 { | |
1395 | compatible = "rockchip,gpio-bank"; | |
79db45be | 1396 | reg = <0x0 0xff7a0000 0x0 0x100>; |
2ab557b7 HS |
1397 | interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>; |
1398 | clocks = <&cru PCLK_GPIO3>; | |
1399 | ||
1400 | gpio-controller; | |
1401 | #gpio-cells = <2>; | |
1402 | ||
1403 | interrupt-controller; | |
1404 | #interrupt-cells = <2>; | |
1405 | }; | |
1406 | ||
1407 | gpio4: gpio4@ff7b0000 { | |
1408 | compatible = "rockchip,gpio-bank"; | |
79db45be | 1409 | reg = <0x0 0xff7b0000 0x0 0x100>; |
2ab557b7 HS |
1410 | interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>; |
1411 | clocks = <&cru PCLK_GPIO4>; | |
1412 | ||
1413 | gpio-controller; | |
1414 | #gpio-cells = <2>; | |
1415 | ||
1416 | interrupt-controller; | |
1417 | #interrupt-cells = <2>; | |
1418 | }; | |
1419 | ||
1420 | gpio5: gpio5@ff7c0000 { | |
1421 | compatible = "rockchip,gpio-bank"; | |
79db45be | 1422 | reg = <0x0 0xff7c0000 0x0 0x100>; |
2ab557b7 HS |
1423 | interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>; |
1424 | clocks = <&cru PCLK_GPIO5>; | |
1425 | ||
1426 | gpio-controller; | |
1427 | #gpio-cells = <2>; | |
1428 | ||
1429 | interrupt-controller; | |
1430 | #interrupt-cells = <2>; | |
1431 | }; | |
1432 | ||
1433 | gpio6: gpio6@ff7d0000 { | |
1434 | compatible = "rockchip,gpio-bank"; | |
79db45be | 1435 | reg = <0x0 0xff7d0000 0x0 0x100>; |
2ab557b7 HS |
1436 | interrupts = <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>; |
1437 | clocks = <&cru PCLK_GPIO6>; | |
1438 | ||
1439 | gpio-controller; | |
1440 | #gpio-cells = <2>; | |
1441 | ||
1442 | interrupt-controller; | |
1443 | #interrupt-cells = <2>; | |
1444 | }; | |
1445 | ||
1446 | gpio7: gpio7@ff7e0000 { | |
1447 | compatible = "rockchip,gpio-bank"; | |
79db45be | 1448 | reg = <0x0 0xff7e0000 0x0 0x100>; |
2ab557b7 HS |
1449 | interrupts = <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>; |
1450 | clocks = <&cru PCLK_GPIO7>; | |
1451 | ||
1452 | gpio-controller; | |
1453 | #gpio-cells = <2>; | |
1454 | ||
1455 | interrupt-controller; | |
1456 | #interrupt-cells = <2>; | |
1457 | }; | |
1458 | ||
1459 | gpio8: gpio8@ff7f0000 { | |
1460 | compatible = "rockchip,gpio-bank"; | |
79db45be | 1461 | reg = <0x0 0xff7f0000 0x0 0x100>; |
2ab557b7 HS |
1462 | interrupts = <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>; |
1463 | clocks = <&cru PCLK_GPIO8>; | |
1464 | ||
1465 | gpio-controller; | |
1466 | #gpio-cells = <2>; | |
1467 | ||
1468 | interrupt-controller; | |
1469 | #interrupt-cells = <2>; | |
1470 | }; | |
1471 | ||
e61ccb12 DA |
1472 | hdmi { |
1473 | hdmi_ddc: hdmi-ddc { | |
1474 | rockchip,pins = <7 19 RK_FUNC_2 &pcfg_pull_none>, | |
1475 | <7 20 RK_FUNC_2 &pcfg_pull_none>; | |
1476 | }; | |
1477 | }; | |
1478 | ||
2ab557b7 HS |
1479 | pcfg_pull_up: pcfg-pull-up { |
1480 | bias-pull-up; | |
1481 | }; | |
1482 | ||
1483 | pcfg_pull_down: pcfg-pull-down { | |
1484 | bias-pull-down; | |
1485 | }; | |
1486 | ||
1487 | pcfg_pull_none: pcfg-pull-none { | |
1488 | bias-disable; | |
1489 | }; | |
1490 | ||
3d3fb74a RC |
1491 | pcfg_pull_none_12ma: pcfg-pull-none-12ma { |
1492 | bias-disable; | |
1493 | drive-strength = <12>; | |
1494 | }; | |
1495 | ||
eecfe981 CZ |
1496 | sleep { |
1497 | global_pwroff: global-pwroff { | |
1498 | rockchip,pins = <0 0 RK_FUNC_1 &pcfg_pull_none>; | |
1499 | }; | |
1500 | ||
1501 | ddrio_pwroff: ddrio-pwroff { | |
1502 | rockchip,pins = <0 1 RK_FUNC_1 &pcfg_pull_none>; | |
1503 | }; | |
1504 | ||
1505 | ddr0_retention: ddr0-retention { | |
1506 | rockchip,pins = <0 2 RK_FUNC_1 &pcfg_pull_up>; | |
1507 | }; | |
1508 | ||
1509 | ddr1_retention: ddr1-retention { | |
1510 | rockchip,pins = <0 3 RK_FUNC_1 &pcfg_pull_up>; | |
1511 | }; | |
1512 | }; | |
1513 | ||
a4e00345 HS |
1514 | edp { |
1515 | edp_hpd: edp-hpd { | |
1516 | rockchip,pins = <7 11 RK_FUNC_2 &pcfg_pull_down>; | |
1517 | }; | |
1518 | }; | |
1519 | ||
2ab557b7 HS |
1520 | i2c0 { |
1521 | i2c0_xfer: i2c0-xfer { | |
1522 | rockchip,pins = <0 15 RK_FUNC_1 &pcfg_pull_none>, | |
1523 | <0 16 RK_FUNC_1 &pcfg_pull_none>; | |
1524 | }; | |
1525 | }; | |
1526 | ||
1527 | i2c1 { | |
1528 | i2c1_xfer: i2c1-xfer { | |
1529 | rockchip,pins = <8 4 RK_FUNC_1 &pcfg_pull_none>, | |
1530 | <8 5 RK_FUNC_1 &pcfg_pull_none>; | |
1531 | }; | |
1532 | }; | |
1533 | ||
1534 | i2c2 { | |
1535 | i2c2_xfer: i2c2-xfer { | |
1536 | rockchip,pins = <6 9 RK_FUNC_1 &pcfg_pull_none>, | |
1537 | <6 10 RK_FUNC_1 &pcfg_pull_none>; | |
1538 | }; | |
1539 | }; | |
1540 | ||
1541 | i2c3 { | |
1542 | i2c3_xfer: i2c3-xfer { | |
1543 | rockchip,pins = <2 16 RK_FUNC_1 &pcfg_pull_none>, | |
1544 | <2 17 RK_FUNC_1 &pcfg_pull_none>; | |
1545 | }; | |
1546 | }; | |
1547 | ||
1548 | i2c4 { | |
1549 | i2c4_xfer: i2c4-xfer { | |
1550 | rockchip,pins = <7 17 RK_FUNC_1 &pcfg_pull_none>, | |
1551 | <7 18 RK_FUNC_1 &pcfg_pull_none>; | |
1552 | }; | |
1553 | }; | |
1554 | ||
1555 | i2c5 { | |
1556 | i2c5_xfer: i2c5-xfer { | |
1557 | rockchip,pins = <7 19 RK_FUNC_1 &pcfg_pull_none>, | |
1558 | <7 20 RK_FUNC_1 &pcfg_pull_none>; | |
a0f95e35 J |
1559 | }; |
1560 | }; | |
1561 | ||
1562 | i2s0 { | |
1563 | i2s0_bus: i2s0-bus { | |
1564 | rockchip,pins = <6 0 RK_FUNC_1 &pcfg_pull_none>, | |
1565 | <6 1 RK_FUNC_1 &pcfg_pull_none>, | |
1566 | <6 2 RK_FUNC_1 &pcfg_pull_none>, | |
1567 | <6 3 RK_FUNC_1 &pcfg_pull_none>, | |
1568 | <6 4 RK_FUNC_1 &pcfg_pull_none>, | |
1569 | <6 8 RK_FUNC_1 &pcfg_pull_none>; | |
2ab557b7 HS |
1570 | }; |
1571 | }; | |
1572 | ||
316ffa32 SH |
1573 | lcdc { |
1574 | lcdc_ctl: lcdc-ctl { | |
1575 | rockchip,pins = <1 24 RK_FUNC_1 &pcfg_pull_none>, | |
1576 | <1 25 RK_FUNC_1 &pcfg_pull_none>, | |
1577 | <1 26 RK_FUNC_1 &pcfg_pull_none>, | |
1578 | <1 27 RK_FUNC_1 &pcfg_pull_none>; | |
1579 | }; | |
1580 | }; | |
1581 | ||
2ab557b7 HS |
1582 | sdmmc { |
1583 | sdmmc_clk: sdmmc-clk { | |
1584 | rockchip,pins = <6 20 RK_FUNC_1 &pcfg_pull_none>; | |
1585 | }; | |
1586 | ||
1587 | sdmmc_cmd: sdmmc-cmd { | |
1588 | rockchip,pins = <6 21 RK_FUNC_1 &pcfg_pull_up>; | |
1589 | }; | |
1590 | ||
d59df5d1 | 1591 | sdmmc_cd: sdmmc-cd { |
2ab557b7 HS |
1592 | rockchip,pins = <6 22 RK_FUNC_1 &pcfg_pull_up>; |
1593 | }; | |
1594 | ||
1595 | sdmmc_bus1: sdmmc-bus1 { | |
1596 | rockchip,pins = <6 16 RK_FUNC_1 &pcfg_pull_up>; | |
1597 | }; | |
1598 | ||
1599 | sdmmc_bus4: sdmmc-bus4 { | |
1600 | rockchip,pins = <6 16 RK_FUNC_1 &pcfg_pull_up>, | |
1601 | <6 17 RK_FUNC_1 &pcfg_pull_up>, | |
1602 | <6 18 RK_FUNC_1 &pcfg_pull_up>, | |
1603 | <6 19 RK_FUNC_1 &pcfg_pull_up>; | |
1604 | }; | |
1605 | }; | |
1606 | ||
f1a07231 AK |
1607 | sdio0 { |
1608 | sdio0_bus1: sdio0-bus1 { | |
1609 | rockchip,pins = <4 20 RK_FUNC_1 &pcfg_pull_up>; | |
1610 | }; | |
1611 | ||
1612 | sdio0_bus4: sdio0-bus4 { | |
1613 | rockchip,pins = <4 20 RK_FUNC_1 &pcfg_pull_up>, | |
1614 | <4 21 RK_FUNC_1 &pcfg_pull_up>, | |
1615 | <4 22 RK_FUNC_1 &pcfg_pull_up>, | |
1616 | <4 23 RK_FUNC_1 &pcfg_pull_up>; | |
1617 | }; | |
1618 | ||
1619 | sdio0_cmd: sdio0-cmd { | |
1620 | rockchip,pins = <4 24 RK_FUNC_1 &pcfg_pull_up>; | |
1621 | }; | |
1622 | ||
1623 | sdio0_clk: sdio0-clk { | |
1624 | rockchip,pins = <4 25 RK_FUNC_1 &pcfg_pull_none>; | |
1625 | }; | |
1626 | ||
1627 | sdio0_cd: sdio0-cd { | |
1628 | rockchip,pins = <4 26 RK_FUNC_1 &pcfg_pull_up>; | |
1629 | }; | |
1630 | ||
1631 | sdio0_wp: sdio0-wp { | |
1632 | rockchip,pins = <4 27 RK_FUNC_1 &pcfg_pull_up>; | |
1633 | }; | |
1634 | ||
1635 | sdio0_pwr: sdio0-pwr { | |
1636 | rockchip,pins = <4 28 RK_FUNC_1 &pcfg_pull_up>; | |
1637 | }; | |
1638 | ||
1639 | sdio0_bkpwr: sdio0-bkpwr { | |
1640 | rockchip,pins = <4 29 RK_FUNC_1 &pcfg_pull_up>; | |
1641 | }; | |
1642 | ||
1643 | sdio0_int: sdio0-int { | |
1644 | rockchip,pins = <4 30 RK_FUNC_1 &pcfg_pull_up>; | |
1645 | }; | |
1646 | }; | |
1647 | ||
1648 | sdio1 { | |
1649 | sdio1_bus1: sdio1-bus1 { | |
1650 | rockchip,pins = <3 24 4 &pcfg_pull_up>; | |
1651 | }; | |
1652 | ||
1653 | sdio1_bus4: sdio1-bus4 { | |
1654 | rockchip,pins = <3 24 4 &pcfg_pull_up>, | |
1655 | <3 25 4 &pcfg_pull_up>, | |
1656 | <3 26 4 &pcfg_pull_up>, | |
1657 | <3 27 4 &pcfg_pull_up>; | |
1658 | }; | |
1659 | ||
1660 | sdio1_cd: sdio1-cd { | |
1661 | rockchip,pins = <3 28 4 &pcfg_pull_up>; | |
1662 | }; | |
1663 | ||
1664 | sdio1_wp: sdio1-wp { | |
1665 | rockchip,pins = <3 29 4 &pcfg_pull_up>; | |
1666 | }; | |
1667 | ||
1668 | sdio1_bkpwr: sdio1-bkpwr { | |
1669 | rockchip,pins = <3 30 4 &pcfg_pull_up>; | |
1670 | }; | |
1671 | ||
1672 | sdio1_int: sdio1-int { | |
1673 | rockchip,pins = <3 31 4 &pcfg_pull_up>; | |
1674 | }; | |
1675 | ||
1676 | sdio1_cmd: sdio1-cmd { | |
1677 | rockchip,pins = <4 6 4 &pcfg_pull_up>; | |
1678 | }; | |
1679 | ||
1680 | sdio1_clk: sdio1-clk { | |
1681 | rockchip,pins = <4 7 4 &pcfg_pull_none>; | |
1682 | }; | |
1683 | ||
1684 | sdio1_pwr: sdio1-pwr { | |
1685 | rockchip,pins = <4 9 4 &pcfg_pull_up>; | |
1686 | }; | |
1687 | }; | |
1688 | ||
2ab557b7 HS |
1689 | emmc { |
1690 | emmc_clk: emmc-clk { | |
1691 | rockchip,pins = <3 18 RK_FUNC_2 &pcfg_pull_none>; | |
1692 | }; | |
1693 | ||
1694 | emmc_cmd: emmc-cmd { | |
1695 | rockchip,pins = <3 16 RK_FUNC_2 &pcfg_pull_up>; | |
1696 | }; | |
1697 | ||
1698 | emmc_pwr: emmc-pwr { | |
1699 | rockchip,pins = <3 9 RK_FUNC_2 &pcfg_pull_up>; | |
1700 | }; | |
1701 | ||
1702 | emmc_bus1: emmc-bus1 { | |
1703 | rockchip,pins = <3 0 RK_FUNC_2 &pcfg_pull_up>; | |
1704 | }; | |
1705 | ||
1706 | emmc_bus4: emmc-bus4 { | |
1707 | rockchip,pins = <3 0 RK_FUNC_2 &pcfg_pull_up>, | |
1708 | <3 1 RK_FUNC_2 &pcfg_pull_up>, | |
1709 | <3 2 RK_FUNC_2 &pcfg_pull_up>, | |
1710 | <3 3 RK_FUNC_2 &pcfg_pull_up>; | |
1711 | }; | |
1712 | ||
1713 | emmc_bus8: emmc-bus8 { | |
1714 | rockchip,pins = <3 0 RK_FUNC_2 &pcfg_pull_up>, | |
1715 | <3 1 RK_FUNC_2 &pcfg_pull_up>, | |
1716 | <3 2 RK_FUNC_2 &pcfg_pull_up>, | |
1717 | <3 3 RK_FUNC_2 &pcfg_pull_up>, | |
1718 | <3 4 RK_FUNC_2 &pcfg_pull_up>, | |
1719 | <3 5 RK_FUNC_2 &pcfg_pull_up>, | |
1720 | <3 6 RK_FUNC_2 &pcfg_pull_up>, | |
1721 | <3 7 RK_FUNC_2 &pcfg_pull_up>; | |
1722 | }; | |
1723 | }; | |
1724 | ||
1f53170b | 1725 | spi0 { |
1726 | spi0_clk: spi0-clk { | |
1727 | rockchip,pins = <5 12 RK_FUNC_1 &pcfg_pull_up>; | |
1728 | }; | |
1729 | spi0_cs0: spi0-cs0 { | |
1730 | rockchip,pins = <5 13 RK_FUNC_1 &pcfg_pull_up>; | |
1731 | }; | |
1732 | spi0_tx: spi0-tx { | |
1733 | rockchip,pins = <5 14 RK_FUNC_1 &pcfg_pull_up>; | |
1734 | }; | |
1735 | spi0_rx: spi0-rx { | |
1736 | rockchip,pins = <5 15 RK_FUNC_1 &pcfg_pull_up>; | |
1737 | }; | |
1738 | spi0_cs1: spi0-cs1 { | |
1739 | rockchip,pins = <5 16 RK_FUNC_1 &pcfg_pull_up>; | |
1740 | }; | |
1741 | }; | |
1742 | spi1 { | |
1743 | spi1_clk: spi1-clk { | |
1744 | rockchip,pins = <7 12 RK_FUNC_2 &pcfg_pull_up>; | |
1745 | }; | |
1746 | spi1_cs0: spi1-cs0 { | |
1747 | rockchip,pins = <7 13 RK_FUNC_2 &pcfg_pull_up>; | |
1748 | }; | |
1749 | spi1_rx: spi1-rx { | |
1750 | rockchip,pins = <7 14 RK_FUNC_2 &pcfg_pull_up>; | |
1751 | }; | |
1752 | spi1_tx: spi1-tx { | |
1753 | rockchip,pins = <7 15 RK_FUNC_2 &pcfg_pull_up>; | |
1754 | }; | |
1755 | }; | |
1756 | ||
1757 | spi2 { | |
1758 | spi2_cs1: spi2-cs1 { | |
1759 | rockchip,pins = <8 3 RK_FUNC_1 &pcfg_pull_up>; | |
1760 | }; | |
1761 | spi2_clk: spi2-clk { | |
1762 | rockchip,pins = <8 6 RK_FUNC_1 &pcfg_pull_up>; | |
1763 | }; | |
1764 | spi2_cs0: spi2-cs0 { | |
1765 | rockchip,pins = <8 7 RK_FUNC_1 &pcfg_pull_up>; | |
1766 | }; | |
1767 | spi2_rx: spi2-rx { | |
1768 | rockchip,pins = <8 8 RK_FUNC_1 &pcfg_pull_up>; | |
1769 | }; | |
1770 | spi2_tx: spi2-tx { | |
1771 | rockchip,pins = <8 9 RK_FUNC_1 &pcfg_pull_up>; | |
1772 | }; | |
1773 | }; | |
1774 | ||
2ab557b7 HS |
1775 | uart0 { |
1776 | uart0_xfer: uart0-xfer { | |
1777 | rockchip,pins = <4 16 RK_FUNC_1 &pcfg_pull_up>, | |
1778 | <4 17 RK_FUNC_1 &pcfg_pull_none>; | |
1779 | }; | |
1780 | ||
1781 | uart0_cts: uart0-cts { | |
8915f364 | 1782 | rockchip,pins = <4 18 RK_FUNC_1 &pcfg_pull_up>; |
2ab557b7 HS |
1783 | }; |
1784 | ||
1785 | uart0_rts: uart0-rts { | |
1786 | rockchip,pins = <4 19 RK_FUNC_1 &pcfg_pull_none>; | |
1787 | }; | |
1788 | }; | |
1789 | ||
1790 | uart1 { | |
1791 | uart1_xfer: uart1-xfer { | |
1792 | rockchip,pins = <5 8 RK_FUNC_1 &pcfg_pull_up>, | |
1793 | <5 9 RK_FUNC_1 &pcfg_pull_none>; | |
1794 | }; | |
1795 | ||
1796 | uart1_cts: uart1-cts { | |
8915f364 | 1797 | rockchip,pins = <5 10 RK_FUNC_1 &pcfg_pull_up>; |
2ab557b7 HS |
1798 | }; |
1799 | ||
1800 | uart1_rts: uart1-rts { | |
1801 | rockchip,pins = <5 11 RK_FUNC_1 &pcfg_pull_none>; | |
1802 | }; | |
1803 | }; | |
1804 | ||
1805 | uart2 { | |
1806 | uart2_xfer: uart2-xfer { | |
1807 | rockchip,pins = <7 22 RK_FUNC_1 &pcfg_pull_up>, | |
1808 | <7 23 RK_FUNC_1 &pcfg_pull_none>; | |
1809 | }; | |
1810 | /* no rts / cts for uart2 */ | |
1811 | }; | |
1812 | ||
1813 | uart3 { | |
1814 | uart3_xfer: uart3-xfer { | |
1815 | rockchip,pins = <7 7 RK_FUNC_1 &pcfg_pull_up>, | |
1816 | <7 8 RK_FUNC_1 &pcfg_pull_none>; | |
1817 | }; | |
1818 | ||
1819 | uart3_cts: uart3-cts { | |
8915f364 | 1820 | rockchip,pins = <7 9 RK_FUNC_1 &pcfg_pull_up>; |
2ab557b7 HS |
1821 | }; |
1822 | ||
1823 | uart3_rts: uart3-rts { | |
1824 | rockchip,pins = <7 10 RK_FUNC_1 &pcfg_pull_none>; | |
1825 | }; | |
1826 | }; | |
1827 | ||
1828 | uart4 { | |
1829 | uart4_xfer: uart4-xfer { | |
1830 | rockchip,pins = <5 12 3 &pcfg_pull_up>, | |
1831 | <5 13 3 &pcfg_pull_none>; | |
1832 | }; | |
1833 | ||
1834 | uart4_cts: uart4-cts { | |
8915f364 | 1835 | rockchip,pins = <5 14 3 &pcfg_pull_up>; |
2ab557b7 HS |
1836 | }; |
1837 | ||
1838 | uart4_rts: uart4-rts { | |
1839 | rockchip,pins = <5 15 3 &pcfg_pull_none>; | |
1840 | }; | |
1841 | }; | |
df542df3 | 1842 | |
b67d6bc3 | 1843 | tsadc { |
784359b8 CW |
1844 | otp_gpio: otp-gpio { |
1845 | rockchip,pins = <0 10 RK_FUNC_GPIO &pcfg_pull_none>; | |
1846 | }; | |
1847 | ||
b67d6bc3 CW |
1848 | otp_out: otp-out { |
1849 | rockchip,pins = <0 10 RK_FUNC_1 &pcfg_pull_none>; | |
1850 | }; | |
1851 | }; | |
1852 | ||
df542df3 DA |
1853 | pwm0 { |
1854 | pwm0_pin: pwm0-pin { | |
1855 | rockchip,pins = <7 0 RK_FUNC_1 &pcfg_pull_none>; | |
1856 | }; | |
1857 | }; | |
1858 | ||
1859 | pwm1 { | |
1860 | pwm1_pin: pwm1-pin { | |
1861 | rockchip,pins = <7 1 RK_FUNC_1 &pcfg_pull_none>; | |
1862 | }; | |
1863 | }; | |
1864 | ||
1865 | pwm2 { | |
1866 | pwm2_pin: pwm2-pin { | |
1867 | rockchip,pins = <7 22 3 &pcfg_pull_none>; | |
1868 | }; | |
1869 | }; | |
1870 | ||
1871 | pwm3 { | |
1872 | pwm3_pin: pwm3-pin { | |
1873 | rockchip,pins = <7 23 3 &pcfg_pull_none>; | |
1874 | }; | |
1875 | }; | |
3d3fb74a RC |
1876 | |
1877 | gmac { | |
1878 | rgmii_pins: rgmii-pins { | |
1879 | rockchip,pins = <3 30 3 &pcfg_pull_none>, | |
1880 | <3 31 3 &pcfg_pull_none>, | |
1881 | <3 26 3 &pcfg_pull_none>, | |
1882 | <3 27 3 &pcfg_pull_none>, | |
1883 | <3 28 3 &pcfg_pull_none_12ma>, | |
1884 | <3 29 3 &pcfg_pull_none_12ma>, | |
1885 | <3 24 3 &pcfg_pull_none_12ma>, | |
1886 | <3 25 3 &pcfg_pull_none_12ma>, | |
1887 | <4 0 3 &pcfg_pull_none>, | |
1888 | <4 5 3 &pcfg_pull_none>, | |
1889 | <4 6 3 &pcfg_pull_none>, | |
1890 | <4 9 3 &pcfg_pull_none_12ma>, | |
1891 | <4 4 3 &pcfg_pull_none_12ma>, | |
1892 | <4 1 3 &pcfg_pull_none>, | |
1893 | <4 3 3 &pcfg_pull_none>; | |
1894 | }; | |
1895 | ||
1896 | rmii_pins: rmii-pins { | |
1897 | rockchip,pins = <3 30 3 &pcfg_pull_none>, | |
1898 | <3 31 3 &pcfg_pull_none>, | |
1899 | <3 28 3 &pcfg_pull_none>, | |
1900 | <3 29 3 &pcfg_pull_none>, | |
1901 | <4 0 3 &pcfg_pull_none>, | |
1902 | <4 5 3 &pcfg_pull_none>, | |
1903 | <4 4 3 &pcfg_pull_none>, | |
1904 | <4 1 3 &pcfg_pull_none>, | |
1905 | <4 2 3 &pcfg_pull_none>, | |
1906 | <4 3 3 &pcfg_pull_none>; | |
1907 | }; | |
1908 | }; | |
874e568e SS |
1909 | |
1910 | spdif { | |
1911 | spdif_tx: spdif-tx { | |
1912 | rockchip,pins = <RK_GPIO6 11 RK_FUNC_1 &pcfg_pull_none>; | |
1913 | }; | |
1914 | }; | |
2ab557b7 HS |
1915 | }; |
1916 | }; |