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ARM: dts: rockchip: unuse the slot-node and deprecate the supports-highspeed for...
[linux-block.git] / arch / arm / boot / dts / rk3288.dtsi
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2ab557b7
HS		 1/*
2 * This program is free software; you can redistribute it and/or modify
3 * it under the terms of the GNU General Public License as published by
4 * the Free Software Foundation; either version 2 of the License, or
5 * (at your option) any later version.
6 *
7 * This program is distributed in the hope that it will be useful,
8 * but WITHOUT ANY WARRANTY; without even the implied warranty of
9 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
10 * GNU General Public License for more details.
11 */
12
13#include <dt-bindings/gpio/gpio.h>
14#include <dt-bindings/interrupt-controller/irq.h>
15#include <dt-bindings/interrupt-controller/arm-gic.h>
16#include <dt-bindings/pinctrl/rockchip.h>
17#include <dt-bindings/clock/rk3288-cru.h>
18#include "skeleton.dtsi"
19
20/ {
21 compatible = "rockchip,rk3288";
22
23 interrupt-parent = <&gic>;
24
25 aliases {
26 i2c0 = &i2c0;
27 i2c1 = &i2c1;
28 i2c2 = &i2c2;
29 i2c3 = &i2c3;
30 i2c4 = &i2c4;
31 i2c5 = &i2c5;
32 serial0 = &uart0;
33 serial1 = &uart1;
34 serial2 = &uart2;
35 serial3 = &uart3;
36 serial4 = &uart4;
37 };
38
39 cpus {
40 #address-cells = <1>;
41 #size-cells = <0>;
42
43 cpu@500 {
44 device_type = "cpu";
45 compatible = "arm,cortex-a12";
46 reg = <0x500>;
47 };
48 cpu@501 {
49 device_type = "cpu";
50 compatible = "arm,cortex-a12";
51 reg = <0x501>;
52 };
53 cpu@502 {
54 device_type = "cpu";
55 compatible = "arm,cortex-a12";
56 reg = <0x502>;
57 };
58 cpu@503 {
59 device_type = "cpu";
60 compatible = "arm,cortex-a12";
61 reg = <0x503>;
62 };
63 };
64
65 xin24m: oscillator {
66 compatible = "fixed-clock";
67 clock-frequency = <24000000>;
68 clock-output-names = "xin24m";
69 #clock-cells = <0>;
70 };
71
72 timer {
73 compatible = "arm,armv7-timer";
74 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
75 <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
76 <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
77 <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
78 clock-frequency = <24000000>;
79 };
80
81 i2c1: i2c@ff140000 {
82 compatible = "rockchip,rk3288-i2c";
83 reg = <0xff140000 0x1000>;
84 interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>;
85 #address-cells = <1>;
86 #size-cells = <0>;
87 clock-names = "i2c";
88 clocks = <&cru PCLK_I2C1>;
89 pinctrl-names = "default";
90 pinctrl-0 = <&i2c1_xfer>;
91 status = "disabled";
92 };
93
94 i2c3: i2c@ff150000 {
95 compatible = "rockchip,rk3288-i2c";
96 reg = <0xff150000 0x1000>;
97 interrupts = <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>;
98 #address-cells = <1>;
99 #size-cells = <0>;
100 clock-names = "i2c";
101 clocks = <&cru PCLK_I2C3>;
102 pinctrl-names = "default";
103 pinctrl-0 = <&i2c3_xfer>;
104 status = "disabled";
105 };
106
107 i2c4: i2c@ff160000 {
108 compatible = "rockchip,rk3288-i2c";
109 reg = <0xff160000 0x1000>;
110 interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>;
111 #address-cells = <1>;
112 #size-cells = <0>;
113 clock-names = "i2c";
114 clocks = <&cru PCLK_I2C4>;
115 pinctrl-names = "default";
116 pinctrl-0 = <&i2c4_xfer>;
117 status = "disabled";
118 };
119
120 i2c5: i2c@ff170000 {
121 compatible = "rockchip,rk3288-i2c";
122 reg = <0xff170000 0x1000>;
123 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>;
124 #address-cells = <1>;
125 #size-cells = <0>;
126 clock-names = "i2c";
127 clocks = <&cru PCLK_I2C5>;
128 pinctrl-names = "default";
129 pinctrl-0 = <&i2c5_xfer>;
130 status = "disabled";
131 };
132
133 uart0: serial@ff180000 {
134 compatible = "rockchip,rk3288-uart", "snps,dw-apb-uart";
135 reg = <0xff180000 0x100>;
136 interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>;
137 reg-shift = <2>;
138 reg-io-width = <4>;
139 clocks = <&cru SCLK_UART0>, <&cru PCLK_UART0>;
140 clock-names = "baudclk", "apb_pclk";
141 pinctrl-names = "default";
142 pinctrl-0 = <&uart0_xfer>;
143 status = "disabled";
144 };
145
146 uart1: serial@ff190000 {
147 compatible = "rockchip,rk3288-uart", "snps,dw-apb-uart";
148 reg = <0xff190000 0x100>;
149 interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>;
150 reg-shift = <2>;
151 reg-io-width = <4>;
152 clocks = <&cru SCLK_UART1>, <&cru PCLK_UART1>;
153 clock-names = "baudclk", "apb_pclk";
154 pinctrl-names = "default";
155 pinctrl-0 = <&uart1_xfer>;
156 status = "disabled";
157 };
158
159 uart2: serial@ff690000 {
160 compatible = "rockchip,rk3288-uart", "snps,dw-apb-uart";
161 reg = <0xff690000 0x100>;
162 interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>;
163 reg-shift = <2>;
164 reg-io-width = <4>;
165 clocks = <&cru SCLK_UART2>, <&cru PCLK_UART2>;
166 clock-names = "baudclk", "apb_pclk";
167 pinctrl-names = "default";
168 pinctrl-0 = <&uart2_xfer>;
169 status = "disabled";
170 };
171
172 uart3: serial@ff1b0000 {
173 compatible = "rockchip,rk3288-uart", "snps,dw-apb-uart";
174 reg = <0xff1b0000 0x100>;
175 interrupts = <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>;
176 reg-shift = <2>;
177 reg-io-width = <4>;
178 clocks = <&cru SCLK_UART3>, <&cru PCLK_UART3>;
179 clock-names = "baudclk", "apb_pclk";
180 pinctrl-names = "default";
181 pinctrl-0 = <&uart3_xfer>;
182 status = "disabled";
183 };
184
185 uart4: serial@ff1c0000 {
186 compatible = "rockchip,rk3288-uart", "snps,dw-apb-uart";
187 reg = <0xff1c0000 0x100>;
188 interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>;
189 reg-shift = <2>;
190 reg-io-width = <4>;
191 clocks = <&cru SCLK_UART4>, <&cru PCLK_UART4>;
192 clock-names = "baudclk", "apb_pclk";
193 pinctrl-names = "default";
194 pinctrl-0 = <&uart4_xfer>;
195 status = "disabled";
196 };
197
c9c32c50
DA		 198 usb_host0_ehci: usb@ff500000 {
199 compatible = "generic-ehci";
200 reg = <0xff500000 0x100>;
201 interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>;
202 clocks = <&cru HCLK_USBHOST0>;
203 clock-names = "usbhost";
204 status = "disabled";
205 };
206
207 /* NOTE: ohci@ff520000 doesn't actually work on hardware */
208
209 usb_hsic: usb@ff5c0000 {
210 compatible = "generic-ehci";
211 reg = <0xff5c0000 0x100>;
212 interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
213 clocks = <&cru HCLK_HSIC>;
214 clock-names = "usbhost";
215 status = "disabled";
216 };
217
2ab557b7
HS		 218 i2c0: i2c@ff650000 {
219 compatible = "rockchip,rk3288-i2c";
220 reg = <0xff650000 0x1000>;
221 interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>;
222 #address-cells = <1>;
223 #size-cells = <0>;
224 clock-names = "i2c";
225 clocks = <&cru PCLK_I2C0>;
226 pinctrl-names = "default";
227 pinctrl-0 = <&i2c0_xfer>;
228 status = "disabled";
229 };
230
231 i2c2: i2c@ff660000 {
232 compatible = "rockchip,rk3288-i2c";
233 reg = <0xff660000 0x1000>;
234 interrupts = <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>;
235 #address-cells = <1>;
236 #size-cells = <0>;
237 clock-names = "i2c";
238 clocks = <&cru PCLK_I2C2>;
239 pinctrl-names = "default";
240 pinctrl-0 = <&i2c2_xfer>;
241 status = "disabled";
242 };
243
244 pmu: power-management@ff730000 {
245 compatible = "rockchip,rk3288-pmu", "syscon";
246 reg = <0xff730000 0x100>;
247 };
248
249 sgrf: syscon@ff740000 {
250 compatible = "rockchip,rk3288-sgrf", "syscon";
251 reg = <0xff740000 0x1000>;
252 };
253
254 cru: clock-controller@ff760000 {
255 compatible = "rockchip,rk3288-cru";
256 reg = <0xff760000 0x1000>;
257 rockchip,grf = <&grf>;
258 #clock-cells = <1>;
259 #reset-cells = <1>;
260 };
261
262 grf: syscon@ff770000 {
263 compatible = "rockchip,rk3288-grf", "syscon";
264 reg = <0xff770000 0x1000>;
265 };
266
267 wdt: watchdog@ff800000 {
268 compatible = "rockchip,rk3288-wdt", "snps,dw-wdt";
269 reg = <0xff800000 0x100>;
270 interrupts = <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>;
271 status = "disabled";
272 };
273
274 gic: interrupt-controller@ffc01000 {
275 compatible = "arm,gic-400";
276 interrupt-controller;
277 #interrupt-cells = <3>;
278 #address-cells = <0>;
279
280 reg = <0xffc01000 0x1000>,
281 <0xffc02000 0x1000>,
282 <0xffc04000 0x2000>,
283 <0xffc06000 0x2000>;
284 interrupts = <GIC_PPI 9 0xf04>;
285 };
286
287 pinctrl: pinctrl {
288 compatible = "rockchip,rk3288-pinctrl";
289 rockchip,grf = <&grf>;
290 rockchip,pmu = <&pmu>;
291 #address-cells = <1>;
292 #size-cells = <1>;
293 ranges;
294
295 gpio0: gpio0@ff750000 {
296 compatible = "rockchip,gpio-bank";
297 reg = <0xff750000 0x100>;
298 interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>;
299 clocks = <&cru PCLK_GPIO0>;
300
301 gpio-controller;
302 #gpio-cells = <2>;
303
304 interrupt-controller;
305 #interrupt-cells = <2>;
306 };
307
308 gpio1: gpio1@ff780000 {
309 compatible = "rockchip,gpio-bank";
310 reg = <0xff780000 0x100>;
311 interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>;
312 clocks = <&cru PCLK_GPIO1>;
313
314 gpio-controller;
315 #gpio-cells = <2>;
316
317 interrupt-controller;
318 #interrupt-cells = <2>;
319 };
320
321 gpio2: gpio2@ff790000 {
322 compatible = "rockchip,gpio-bank";
323 reg = <0xff790000 0x100>;
324 interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
325 clocks = <&cru PCLK_GPIO2>;
326
327 gpio-controller;
328 #gpio-cells = <2>;
329
330 interrupt-controller;
331 #interrupt-cells = <2>;
332 };
333
334 gpio3: gpio3@ff7a0000 {
335 compatible = "rockchip,gpio-bank";
336 reg = <0xff7a0000 0x100>;
337 interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>;
338 clocks = <&cru PCLK_GPIO3>;
339
340 gpio-controller;
341 #gpio-cells = <2>;
342
343 interrupt-controller;
344 #interrupt-cells = <2>;
345 };
346
347 gpio4: gpio4@ff7b0000 {
348 compatible = "rockchip,gpio-bank";
349 reg = <0xff7b0000 0x100>;
350 interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>;
351 clocks = <&cru PCLK_GPIO4>;
352
353 gpio-controller;
354 #gpio-cells = <2>;
355
356 interrupt-controller;
357 #interrupt-cells = <2>;
358 };
359
360 gpio5: gpio5@ff7c0000 {
361 compatible = "rockchip,gpio-bank";
362 reg = <0xff7c0000 0x100>;
363 interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
364 clocks = <&cru PCLK_GPIO5>;
365
366 gpio-controller;
367 #gpio-cells = <2>;
368
369 interrupt-controller;
370 #interrupt-cells = <2>;
371 };
372
373 gpio6: gpio6@ff7d0000 {
374 compatible = "rockchip,gpio-bank";
375 reg = <0xff7d0000 0x100>;
376 interrupts = <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>;
377 clocks = <&cru PCLK_GPIO6>;
378
379 gpio-controller;
380 #gpio-cells = <2>;
381
382 interrupt-controller;
383 #interrupt-cells = <2>;
384 };
385
386 gpio7: gpio7@ff7e0000 {
387 compatible = "rockchip,gpio-bank";
388 reg = <0xff7e0000 0x100>;
389 interrupts = <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>;
390 clocks = <&cru PCLK_GPIO7>;
391
392 gpio-controller;
393 #gpio-cells = <2>;
394
395 interrupt-controller;
396 #interrupt-cells = <2>;
397 };
398
399 gpio8: gpio8@ff7f0000 {
400 compatible = "rockchip,gpio-bank";
401 reg = <0xff7f0000 0x100>;
402 interrupts = <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>;
403 clocks = <&cru PCLK_GPIO8>;
404
405 gpio-controller;
406 #gpio-cells = <2>;
407
408 interrupt-controller;
409 #interrupt-cells = <2>;
410 };
411
412 pcfg_pull_up: pcfg-pull-up {
413 bias-pull-up;
414 };
415
416 pcfg_pull_down: pcfg-pull-down {
417 bias-pull-down;
418 };
419
420 pcfg_pull_none: pcfg-pull-none {
421 bias-disable;
422 };
423
424 i2c0 {
425 i2c0_xfer: i2c0-xfer {
426 rockchip,pins = <0 15 RK_FUNC_1 &pcfg_pull_none>,
427 <0 16 RK_FUNC_1 &pcfg_pull_none>;
428 };
429 };
430
431 i2c1 {
432 i2c1_xfer: i2c1-xfer {
433 rockchip,pins = <8 4 RK_FUNC_1 &pcfg_pull_none>,
434 <8 5 RK_FUNC_1 &pcfg_pull_none>;
435 };
436 };
437
438 i2c2 {
439 i2c2_xfer: i2c2-xfer {
440 rockchip,pins = <6 9 RK_FUNC_1 &pcfg_pull_none>,
441 <6 10 RK_FUNC_1 &pcfg_pull_none>;
442 };
443 };
444
445 i2c3 {
446 i2c3_xfer: i2c3-xfer {
447 rockchip,pins = <2 16 RK_FUNC_1 &pcfg_pull_none>,
448 <2 17 RK_FUNC_1 &pcfg_pull_none>;
449 };
450 };
451
452 i2c4 {
453 i2c4_xfer: i2c4-xfer {
454 rockchip,pins = <7 17 RK_FUNC_1 &pcfg_pull_none>,
455 <7 18 RK_FUNC_1 &pcfg_pull_none>;
456 };
457 };
458
459 i2c5 {
460 i2c5_xfer: i2c5-xfer {
461 rockchip,pins = <7 19 RK_FUNC_1 &pcfg_pull_none>,
462 <7 20 RK_FUNC_1 &pcfg_pull_none>;
463 };
464 };
465
466 sdmmc {
467 sdmmc_clk: sdmmc-clk {
468 rockchip,pins = <6 20 RK_FUNC_1 &pcfg_pull_none>;
469 };
470
471 sdmmc_cmd: sdmmc-cmd {
472 rockchip,pins = <6 21 RK_FUNC_1 &pcfg_pull_up>;
473 };
474
475 sdmmc_cd: sdmcc-cd {
476 rockchip,pins = <6 22 RK_FUNC_1 &pcfg_pull_up>;
477 };
478
479 sdmmc_bus1: sdmmc-bus1 {
480 rockchip,pins = <6 16 RK_FUNC_1 &pcfg_pull_up>;
481 };
482
483 sdmmc_bus4: sdmmc-bus4 {
484 rockchip,pins = <6 16 RK_FUNC_1 &pcfg_pull_up>,
485 <6 17 RK_FUNC_1 &pcfg_pull_up>,
486 <6 18 RK_FUNC_1 &pcfg_pull_up>,
487 <6 19 RK_FUNC_1 &pcfg_pull_up>;
488 };
489 };
490
491 emmc {
492 emmc_clk: emmc-clk {
493 rockchip,pins = <3 18 RK_FUNC_2 &pcfg_pull_none>;
494 };
495
496 emmc_cmd: emmc-cmd {
497 rockchip,pins = <3 16 RK_FUNC_2 &pcfg_pull_up>;
498 };
499
500 emmc_pwr: emmc-pwr {
501 rockchip,pins = <3 9 RK_FUNC_2 &pcfg_pull_up>;
502 };
503
504 emmc_bus1: emmc-bus1 {
505 rockchip,pins = <3 0 RK_FUNC_2 &pcfg_pull_up>;
506 };
507
508 emmc_bus4: emmc-bus4 {
509 rockchip,pins = <3 0 RK_FUNC_2 &pcfg_pull_up>,
510 <3 1 RK_FUNC_2 &pcfg_pull_up>,
511 <3 2 RK_FUNC_2 &pcfg_pull_up>,
512 <3 3 RK_FUNC_2 &pcfg_pull_up>;
513 };
514
515 emmc_bus8: emmc-bus8 {
516 rockchip,pins = <3 0 RK_FUNC_2 &pcfg_pull_up>,
517 <3 1 RK_FUNC_2 &pcfg_pull_up>,
518 <3 2 RK_FUNC_2 &pcfg_pull_up>,
519 <3 3 RK_FUNC_2 &pcfg_pull_up>,
520 <3 4 RK_FUNC_2 &pcfg_pull_up>,
521 <3 5 RK_FUNC_2 &pcfg_pull_up>,
522 <3 6 RK_FUNC_2 &pcfg_pull_up>,
523 <3 7 RK_FUNC_2 &pcfg_pull_up>;
524 };
525 };
526
527 uart0 {
528 uart0_xfer: uart0-xfer {
529 rockchip,pins = <4 16 RK_FUNC_1 &pcfg_pull_up>,
530 <4 17 RK_FUNC_1 &pcfg_pull_none>;
531 };
532
533 uart0_cts: uart0-cts {
534 rockchip,pins = <4 18 RK_FUNC_1 &pcfg_pull_none>;
535 };
536
537 uart0_rts: uart0-rts {
538 rockchip,pins = <4 19 RK_FUNC_1 &pcfg_pull_none>;
539 };
540 };
541
542 uart1 {
543 uart1_xfer: uart1-xfer {
544 rockchip,pins = <5 8 RK_FUNC_1 &pcfg_pull_up>,
545 <5 9 RK_FUNC_1 &pcfg_pull_none>;
546 };
547
548 uart1_cts: uart1-cts {
549 rockchip,pins = <5 10 RK_FUNC_1 &pcfg_pull_none>;
550 };
551
552 uart1_rts: uart1-rts {
553 rockchip,pins = <5 11 RK_FUNC_1 &pcfg_pull_none>;
554 };
555 };
556
557 uart2 {
558 uart2_xfer: uart2-xfer {
559 rockchip,pins = <7 22 RK_FUNC_1 &pcfg_pull_up>,
560 <7 23 RK_FUNC_1 &pcfg_pull_none>;
561 };
562 /* no rts / cts for uart2 */
563 };
564
565 uart3 {
566 uart3_xfer: uart3-xfer {
567 rockchip,pins = <7 7 RK_FUNC_1 &pcfg_pull_up>,
568 <7 8 RK_FUNC_1 &pcfg_pull_none>;
569 };
570
571 uart3_cts: uart3-cts {
572 rockchip,pins = <7 9 RK_FUNC_1 &pcfg_pull_none>;
573 };
574
575 uart3_rts: uart3-rts {
576 rockchip,pins = <7 10 RK_FUNC_1 &pcfg_pull_none>;
577 };
578 };
579
580 uart4 {
581 uart4_xfer: uart4-xfer {
582 rockchip,pins = <5 12 3 &pcfg_pull_up>,
583 <5 13 3 &pcfg_pull_none>;
584 };
585
586 uart4_cts: uart4-cts {
587 rockchip,pins = <5 14 3 &pcfg_pull_none>;
588 };
589
590 uart4_rts: uart4-rts {
591 rockchip,pins = <5 15 3 &pcfg_pull_none>;
592 };
593 };
594 };
595};
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