[linux-2.6-block.git] / arch / arm / boot / dts / rk3066a.dtsi

/*
 * Copyright (c) 2013 MundoReader S.L.
 * Author: Heiko Stuebner <heiko@sntech.de>
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License as published by
 * the Free Software Foundation; either version 2 of the License, or
 * (at your option) any later version.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 * GNU General Public License for more details.
 */

#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/pinctrl/rockchip.h>
#include <dt-bindings/clock/rk3066a-cru.h>
#include "rk3xxx.dtsi"

/ {
	compatible = "rockchip,rk3066a";

	cpus {
		#address-cells = <1>;
		#size-cells = <0>;
		enable-method = "rockchip,rk3066-smp";

		cpu@0 {
			device_type = "cpu";
			compatible = "arm,cortex-a9";
			next-level-cache = <&L2>;
			reg = <0x0>;
		};
		cpu@1 {
			device_type = "cpu";
			compatible = "arm,cortex-a9";
			next-level-cache = <&L2>;
			reg = <0x1>;
		};
	};

	timer@20038000 {
		compatible = "snps,dw-apb-timer-osc";
		reg = <0x20038000 0x100>;
		interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>;
		clocks = <&cru SCLK_TIMER0>, <&cru PCLK_TIMER0>;
		clock-names = "timer", "pclk";
	};

	timer@2003a000 {
		compatible = "snps,dw-apb-timer-osc";
		reg = <0x2003a000 0x100>;
		interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;
		clocks = <&cru SCLK_TIMER1>, <&cru PCLK_TIMER1>;
		clock-names = "timer", "pclk";
	};

	timer@2000e000 {
		compatible = "snps,dw-apb-timer-osc";
		reg = <0x2000e000 0x100>;
		interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>;
		clocks = <&cru SCLK_TIMER2>, <&cru PCLK_TIMER2>;
		clock-names = "timer", "pclk";
	};

	sram: sram@10080000 {
		compatible = "mmio-sram";
		reg = <0x10080000 0x10000>;
		#address-cells = <1>;
		#size-cells = <1>;
		ranges = <0 0x10080000 0x10000>;

		smp-sram@0 {
			compatible = "rockchip,rk3066-smp-sram";
			reg = <0x0 0x50>;
		};
	};

	cru: clock-controller@20000000 {
		compatible = "rockchip,rk3066a-cru";
		reg = <0x20000000 0x1000>;
		rockchip,grf = <&grf>;

		#clock-cells = <1>;
		#reset-cells = <1>;
	};

	pinctrl: pinctrl@20008000 {
		compatible = "rockchip,rk3066a-pinctrl";
		rockchip,grf = <&grf>;
		#address-cells = <1>;
		#size-cells = <1>;
		ranges;

		gpio0: gpio0@20034000 {
			compatible = "rockchip,gpio-bank";
			reg = <0x20034000 0x100>;
			interrupts = <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&cru PCLK_GPIO0>;

			gpio-controller;
			#gpio-cells = <2>;

			interrupt-controller;
			#interrupt-cells = <2>;
		};

		gpio1: gpio1@2003c000 {
			compatible = "rockchip,gpio-bank";
			reg = <0x2003c000 0x100>;
			interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&cru PCLK_GPIO1>;

			gpio-controller;
			#gpio-cells = <2>;

			interrupt-controller;
			#interrupt-cells = <2>;
		};

		gpio2: gpio2@2003e000 {
			compatible = "rockchip,gpio-bank";
			reg = <0x2003e000 0x100>;
			interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&cru PCLK_GPIO2>;

			gpio-controller;
			#gpio-cells = <2>;

			interrupt-controller;
			#interrupt-cells = <2>;
		};

		gpio3: gpio3@20080000 {
			compatible = "rockchip,gpio-bank";
			reg = <0x20080000 0x100>;
			interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&cru PCLK_GPIO3>;

			gpio-controller;
			#gpio-cells = <2>;

			interrupt-controller;
			#interrupt-cells = <2>;
		};

		gpio4: gpio4@20084000 {
			compatible = "rockchip,gpio-bank";
			reg = <0x20084000 0x100>;
			interrupts = <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&cru PCLK_GPIO4>;

			gpio-controller;
			#gpio-cells = <2>;

			interrupt-controller;
			#interrupt-cells = <2>;
		};

		gpio6: gpio6@2000a000 {
			compatible = "rockchip,gpio-bank";
			reg = <0x2000a000 0x100>;
			interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&cru PCLK_GPIO6>;

			gpio-controller;
			#gpio-cells = <2>;

			interrupt-controller;
			#interrupt-cells = <2>;
		};

		pcfg_pull_default: pcfg_pull_default {
			bias-pull-pin-default;
		};

		pcfg_pull_none: pcfg_pull_none {
			bias-disable;
		};

		uart0 {
			uart0_xfer: uart0-xfer {
				rockchip,pins = <RK_GPIO1 0 RK_FUNC_1 &pcfg_pull_default>,
						<RK_GPIO1 1 RK_FUNC_1 &pcfg_pull_default>;
			};

			uart0_cts: uart0-cts {
				rockchip,pins = <RK_GPIO1 2 RK_FUNC_1 &pcfg_pull_default>;
			};

			uart0_rts: uart0-rts {
				rockchip,pins = <RK_GPIO1 3 RK_FUNC_1 &pcfg_pull_default>;
			};
		};

		uart1 {
			uart1_xfer: uart1-xfer {
				rockchip,pins = <RK_GPIO1 4 RK_FUNC_1 &pcfg_pull_default>,
						<RK_GPIO1 5 RK_FUNC_1 &pcfg_pull_default>;
			};

			uart1_cts: uart1-cts {
				rockchip,pins = <RK_GPIO1 6 RK_FUNC_1 &pcfg_pull_default>;
			};

			uart1_rts: uart1-rts {
				rockchip,pins = <RK_GPIO1 7 RK_FUNC_1 &pcfg_pull_default>;
			};
		};

		uart2 {
			uart2_xfer: uart2-xfer {
				rockchip,pins = <RK_GPIO1 8 RK_FUNC_1 &pcfg_pull_default>,
						<RK_GPIO1 9 RK_FUNC_1 &pcfg_pull_default>;
			};
			/* no rts / cts for uart2 */
		};

		uart3 {
			uart3_xfer: uart3-xfer {
				rockchip,pins = <RK_GPIO3 27 RK_FUNC_1 &pcfg_pull_default>,
						<RK_GPIO3 28 RK_FUNC_1 &pcfg_pull_default>;
			};

			uart3_cts: uart3-cts {
				rockchip,pins = <RK_GPIO3 29 RK_FUNC_1 &pcfg_pull_default>;
			};

			uart3_rts: uart3-rts {
				rockchip,pins = <RK_GPIO3 30 RK_FUNC_1 &pcfg_pull_default>;
			};
		};

		sd0 {
			sd0_clk: sd0-clk {
				rockchip,pins = <RK_GPIO3 8 RK_FUNC_1 &pcfg_pull_default>;
			};

			sd0_cmd: sd0-cmd {
				rockchip,pins = <RK_GPIO3 9 RK_FUNC_1 &pcfg_pull_default>;
			};

			sd0_cd: sd0-cd {
				rockchip,pins = <RK_GPIO3 14 RK_FUNC_1 &pcfg_pull_default>;
			};

			sd0_wp: sd0-wp {
				rockchip,pins = <RK_GPIO3 15 RK_FUNC_1 &pcfg_pull_default>;
			};

			sd0_bus1: sd0-bus-width1 {
				rockchip,pins = <RK_GPIO3 10 RK_FUNC_1 &pcfg_pull_default>;
			};

			sd0_bus4: sd0-bus-width4 {
				rockchip,pins = <RK_GPIO3 10 RK_FUNC_1 &pcfg_pull_default>,
						<RK_GPIO3 11 RK_FUNC_1 &pcfg_pull_default>,
						<RK_GPIO3 12 RK_FUNC_1 &pcfg_pull_default>,
						<RK_GPIO3 13 RK_FUNC_1 &pcfg_pull_default>;
			};
		};

		sd1 {
			sd1_clk: sd1-clk {
				rockchip,pins = <RK_GPIO3 21 RK_FUNC_1 &pcfg_pull_default>;
			};

			sd1_cmd: sd1-cmd {
				rockchip,pins = <RK_GPIO3 16 RK_FUNC_1 &pcfg_pull_default>;
			};

			sd1_cd: sd1-cd {
				rockchip,pins = <RK_GPIO3 22 RK_FUNC_1 &pcfg_pull_default>;
			};

			sd1_wp: sd1-wp {
				rockchip,pins = <RK_GPIO3 23 RK_FUNC_1 &pcfg_pull_default>;
			};

			sd1_bus1: sd1-bus-width1 {
				rockchip,pins = <RK_GPIO3 17 RK_FUNC_1 &pcfg_pull_default>;
			};

			sd1_bus4: sd1-bus-width4 {
				rockchip,pins = <RK_GPIO3 17 RK_FUNC_1 &pcfg_pull_default>,
						<RK_GPIO3 18 RK_FUNC_1 &pcfg_pull_default>,
						<RK_GPIO3 19 RK_FUNC_1 &pcfg_pull_default>,
						<RK_GPIO3 20 RK_FUNC_1 &pcfg_pull_default>;
			};
		};
	};
};

&mmc0 {
	pinctrl-names = "default";
	pinctrl-0 = <&sd0_clk &sd0_cmd &sd0_cd &sd0_bus4>;
};

&mmc1 {
	pinctrl-names = "default";
	pinctrl-0 = <&sd1_clk &sd1_cmd &sd1_cd &sd1_bus4>;
};

&uart0 {
	pinctrl-names = "default";
	pinctrl-0 = <&uart0_xfer>;
};

&uart1 {
	pinctrl-names = "default";
	pinctrl-0 = <&uart1_xfer>;
};

&uart2 {
	pinctrl-names = "default";
	pinctrl-0 = <&uart2_xfer>;
};

&uart3 {
	pinctrl-names = "default";
	pinctrl-0 = <&uart3_xfer>;
};
Commit	Line	Data
d63dc051 HS	1	/*
	2	* Copyright (c) 2013 MundoReader S.L.
	3	* Author: Heiko Stuebner <heiko@sntech.de>
	4	*
	5	* This program is free software; you can redistribute it and/or modify
	6	* it under the terms of the GNU General Public License as published by
	7	* the Free Software Foundation; either version 2 of the License, or
	8	* (at your option) any later version.
	9	*
	10	* This program is distributed in the hope that it will be useful,
	11	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	12	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	13	* GNU General Public License for more details.
	14	*/
	15
	16	#include <dt-bindings/gpio/gpio.h>
d63dc051	17	#include <dt-bindings/pinctrl/rockchip.h>
b13d2a7b	18	#include <dt-bindings/clock/rk3066a-cru.h>
f75efdd7	19	#include "rk3xxx.dtsi"
d63dc051 HS	20
	21	/ {
	22	compatible = "rockchip,rk3066a";
d63dc051 HS	23
	24	cpus {
	25	#address-cells = <1>;
	26	#size-cells = <0>;
26ab69cb	27	enable-method = "rockchip,rk3066-smp";
d63dc051 HS	28
	29	cpu@0 {
	30	device_type = "cpu";
	31	compatible = "arm,cortex-a9";
	32	next-level-cache = <&L2>;
	33	reg = <0x0>;
	34	};
	35	cpu@1 {
	36	device_type = "cpu";
	37	compatible = "arm,cortex-a9";
	38	next-level-cache = <&L2>;
	39	reg = <0x1>;
	40	};
	41	};
	42
c3030d30 HS	43	timer@20038000 {
	44	compatible = "snps,dw-apb-timer-osc";
	45	reg = <0x20038000 0x100>;
	46	interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>;
	47	clocks = <&cru SCLK_TIMER0>, <&cru PCLK_TIMER0>;
	48	clock-names = "timer", "pclk";
	49	};
	50
	51	timer@2003a000 {
	52	compatible = "snps,dw-apb-timer-osc";
	53	reg = <0x2003a000 0x100>;
	54	interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;
	55	clocks = <&cru SCLK_TIMER1>, <&cru PCLK_TIMER1>;
	56	clock-names = "timer", "pclk";
	57	};
	58
	59	timer@2000e000 {
	60	compatible = "snps,dw-apb-timer-osc";
	61	reg = <0x2000e000 0x100>;
	62	interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>;
	63	clocks = <&cru SCLK_TIMER2>, <&cru PCLK_TIMER2>;
	64	clock-names = "timer", "pclk";
	65	};
d63dc051	66
c3030d30 HS	67	sram: sram@10080000 {
	68	compatible = "mmio-sram";
	69	reg = <0x10080000 0x10000>;
	70	#address-cells = <1>;
	71	#size-cells = <1>;
	72	ranges = <0 0x10080000 0x10000>;
	73
	74	smp-sram@0 {
	75	compatible = "rockchip,rk3066-smp-sram";
	76	reg = <0x0 0x50>;
d63dc051	77	};
c3030d30 HS	78	};
	79
	80	cru: clock-controller@20000000 {
	81	compatible = "rockchip,rk3066a-cru";
	82	reg = <0x20000000 0x1000>;
	83	rockchip,grf = <&grf>;
	84
	85	#clock-cells = <1>;
	86	#reset-cells = <1>;
	87	};
	88
e40b43d6	89	pinctrl: pinctrl@20008000 {
c3030d30 HS	90	compatible = "rockchip,rk3066a-pinctrl";
	91	rockchip,grf = <&grf>;
	92	#address-cells = <1>;
	93	#size-cells = <1>;
	94	ranges;
d63dc051	95
c3030d30 HS	96	gpio0: gpio0@20034000 {
	97	compatible = "rockchip,gpio-bank";
	98	reg = <0x20034000 0x100>;
	99	interrupts = <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>;
	100	clocks = <&cru PCLK_GPIO0>;
	101
	102	gpio-controller;
	103	#gpio-cells = <2>;
	104
	105	interrupt-controller;
	106	#interrupt-cells = <2>;
d63dc051 HS	107	};
d63dc051 HS	108
c3030d30 HS	109	gpio1: gpio1@2003c000 {
	110	compatible = "rockchip,gpio-bank";
	111	reg = <0x2003c000 0x100>;
	112	interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>;
	113	clocks = <&cru PCLK_GPIO1>;
de18e014	114
c3030d30 HS	115	gpio-controller;
	116	#gpio-cells = <2>;
	117
	118	interrupt-controller;
	119	#interrupt-cells = <2>;
de18e014 HS	120	};
de18e014 HS	121
c3030d30 HS	122	gpio2: gpio2@2003e000 {
	123	compatible = "rockchip,gpio-bank";
	124	reg = <0x2003e000 0x100>;
	125	interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>;
	126	clocks = <&cru PCLK_GPIO2>;
	127
	128	gpio-controller;
	129	#gpio-cells = <2>;
b13d2a7b	130
c3030d30 HS	131	interrupt-controller;
c3030d30 HS	132	#interrupt-cells = <2>;
b13d2a7b HS	133	};
b13d2a7b HS	134
c3030d30 HS	135	gpio3: gpio3@20080000 {
	136	compatible = "rockchip,gpio-bank";
	137	reg = <0x20080000 0x100>;
	138	interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>;
	139	clocks = <&cru PCLK_GPIO3>;
d63dc051	140
c3030d30 HS	141	gpio-controller;
c3030d30 HS	142	#gpio-cells = <2>;
d63dc051	143
c3030d30 HS	144	interrupt-controller;
	145	#interrupt-cells = <2>;
	146	};
d63dc051	147
c3030d30 HS	148	gpio4: gpio4@20084000 {
	149	compatible = "rockchip,gpio-bank";
	150	reg = <0x20084000 0x100>;
	151	interrupts = <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>;
	152	clocks = <&cru PCLK_GPIO4>;
d63dc051	153
c3030d30 HS	154	gpio-controller;
c3030d30 HS	155	#gpio-cells = <2>;
d63dc051	156
c3030d30 HS	157	interrupt-controller;
	158	#interrupt-cells = <2>;
	159	};
d63dc051	160
c3030d30 HS	161	gpio6: gpio6@2000a000 {
	162	compatible = "rockchip,gpio-bank";
	163	reg = <0x2000a000 0x100>;
	164	interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>;
	165	clocks = <&cru PCLK_GPIO6>;
d63dc051	166
c3030d30 HS	167	gpio-controller;
c3030d30 HS	168	#gpio-cells = <2>;
d63dc051	169
c3030d30 HS	170	interrupt-controller;
	171	#interrupt-cells = <2>;
	172	};
d63dc051	173
c3030d30 HS	174	pcfg_pull_default: pcfg_pull_default {
	175	bias-pull-pin-default;
	176	};
d63dc051	177
c3030d30 HS	178	pcfg_pull_none: pcfg_pull_none {
	179	bias-disable;
	180	};
d63dc051	181
c3030d30 HS	182	uart0 {
	183	uart0_xfer: uart0-xfer {
	184	rockchip,pins = <RK_GPIO1 0 RK_FUNC_1 &pcfg_pull_default>,
	185	<RK_GPIO1 1 RK_FUNC_1 &pcfg_pull_default>;
	186	};
d63dc051	187
c3030d30 HS	188	uart0_cts: uart0-cts {
c3030d30 HS	189	rockchip,pins = <RK_GPIO1 2 RK_FUNC_1 &pcfg_pull_default>;
d63dc051 HS	190	};
d63dc051 HS	191
c3030d30 HS	192	uart0_rts: uart0-rts {
	193	rockchip,pins = <RK_GPIO1 3 RK_FUNC_1 &pcfg_pull_default>;
	194	};
	195	};
d63dc051	196
c3030d30 HS	197	uart1 {
	198	uart1_xfer: uart1-xfer {
	199	rockchip,pins = <RK_GPIO1 4 RK_FUNC_1 &pcfg_pull_default>,
	200	<RK_GPIO1 5 RK_FUNC_1 &pcfg_pull_default>;
	201	};
d63dc051	202
c3030d30 HS	203	uart1_cts: uart1-cts {
c3030d30 HS	204	rockchip,pins = <RK_GPIO1 6 RK_FUNC_1 &pcfg_pull_default>;
d63dc051 HS	205	};
d63dc051 HS	206
c3030d30 HS	207	uart1_rts: uart1-rts {
	208	rockchip,pins = <RK_GPIO1 7 RK_FUNC_1 &pcfg_pull_default>;
	209	};
	210	};
d63dc051	211
c3030d30 HS	212	uart2 {
	213	uart2_xfer: uart2-xfer {
	214	rockchip,pins = <RK_GPIO1 8 RK_FUNC_1 &pcfg_pull_default>,
	215	<RK_GPIO1 9 RK_FUNC_1 &pcfg_pull_default>;
	216	};
	217	/* no rts / cts for uart2 */
	218	};
d63dc051	219
c3030d30 HS	220	uart3 {
	221	uart3_xfer: uart3-xfer {
	222	rockchip,pins = <RK_GPIO3 27 RK_FUNC_1 &pcfg_pull_default>,
	223	<RK_GPIO3 28 RK_FUNC_1 &pcfg_pull_default>;
d63dc051 HS	224	};
d63dc051 HS	225
c3030d30 HS	226	uart3_cts: uart3-cts {
c3030d30 HS	227	rockchip,pins = <RK_GPIO3 29 RK_FUNC_1 &pcfg_pull_default>;
d63dc051 HS	228	};
d63dc051 HS	229
c3030d30 HS	230	uart3_rts: uart3-rts {
c3030d30 HS	231	rockchip,pins = <RK_GPIO3 30 RK_FUNC_1 &pcfg_pull_default>;
d63dc051	232	};
c3030d30	233	};
d63dc051	234
c3030d30 HS	235	sd0 {
	236	sd0_clk: sd0-clk {
	237	rockchip,pins = <RK_GPIO3 8 RK_FUNC_1 &pcfg_pull_default>;
	238	};
d63dc051	239
c3030d30 HS	240	sd0_cmd: sd0-cmd {
	241	rockchip,pins = <RK_GPIO3 9 RK_FUNC_1 &pcfg_pull_default>;
	242	};
d63dc051	243
c3030d30 HS	244	sd0_cd: sd0-cd {
c3030d30 HS	245	rockchip,pins = <RK_GPIO3 14 RK_FUNC_1 &pcfg_pull_default>;
d63dc051 HS	246	};
d63dc051 HS	247
c3030d30 HS	248	sd0_wp: sd0-wp {
	249	rockchip,pins = <RK_GPIO3 15 RK_FUNC_1 &pcfg_pull_default>;
	250	};
d63dc051	251
c3030d30 HS	252	sd0_bus1: sd0-bus-width1 {
	253	rockchip,pins = <RK_GPIO3 10 RK_FUNC_1 &pcfg_pull_default>;
	254	};
d63dc051	255
c3030d30 HS	256	sd0_bus4: sd0-bus-width4 {
	257	rockchip,pins = <RK_GPIO3 10 RK_FUNC_1 &pcfg_pull_default>,
	258	<RK_GPIO3 11 RK_FUNC_1 &pcfg_pull_default>,
	259	<RK_GPIO3 12 RK_FUNC_1 &pcfg_pull_default>,
	260	<RK_GPIO3 13 RK_FUNC_1 &pcfg_pull_default>;
d63dc051	261	};
c3030d30	262	};
d63dc051	263
c3030d30 HS	264	sd1 {
	265	sd1_clk: sd1-clk {
	266	rockchip,pins = <RK_GPIO3 21 RK_FUNC_1 &pcfg_pull_default>;
d63dc051 HS	267	};
d63dc051 HS	268
c3030d30 HS	269	sd1_cmd: sd1-cmd {
	270	rockchip,pins = <RK_GPIO3 16 RK_FUNC_1 &pcfg_pull_default>;
	271	};
d63dc051	272
c3030d30 HS	273	sd1_cd: sd1-cd {
	274	rockchip,pins = <RK_GPIO3 22 RK_FUNC_1 &pcfg_pull_default>;
	275	};
d63dc051	276
c3030d30 HS	277	sd1_wp: sd1-wp {
c3030d30 HS	278	rockchip,pins = <RK_GPIO3 23 RK_FUNC_1 &pcfg_pull_default>;
d63dc051 HS	279	};
d63dc051 HS	280
c3030d30 HS	281	sd1_bus1: sd1-bus-width1 {
c3030d30 HS	282	rockchip,pins = <RK_GPIO3 17 RK_FUNC_1 &pcfg_pull_default>;
d63dc051 HS	283	};
d63dc051 HS	284
c3030d30 HS	285	sd1_bus4: sd1-bus-width4 {
	286	rockchip,pins = <RK_GPIO3 17 RK_FUNC_1 &pcfg_pull_default>,
	287	<RK_GPIO3 18 RK_FUNC_1 &pcfg_pull_default>,
	288	<RK_GPIO3 19 RK_FUNC_1 &pcfg_pull_default>,
	289	<RK_GPIO3 20 RK_FUNC_1 &pcfg_pull_default>;
d63dc051 HS	290	};
d63dc051 HS	291	};
d63dc051 HS	292	};
d63dc051 HS	293	};
fcbbf965 HS	294
	295	&mmc0 {
	296	pinctrl-names = "default";
	297	pinctrl-0 = <&sd0_clk &sd0_cmd &sd0_cd &sd0_bus4>;
	298	};
	299
	300	&mmc1 {
	301	pinctrl-names = "default";
	302	pinctrl-0 = <&sd1_clk &sd1_cmd &sd1_cd &sd1_bus4>;
	303	};
	304
	305	&uart0 {
	306	pinctrl-names = "default";
	307	pinctrl-0 = <&uart0_xfer>;
	308	};
	309
	310	&uart1 {
	311	pinctrl-names = "default";
	312	pinctrl-0 = <&uart1_xfer>;
	313	};
	314
	315	&uart2 {
	316	pinctrl-names = "default";
	317	pinctrl-0 = <&uart2_xfer>;
	318	};
	319
	320	&uart3 {
	321	pinctrl-names = "default";
	322	pinctrl-0 = <&uart3_xfer>;
	323	};