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Merge tag 'for-3.16/bcm-soc' of git://github.com/broadcom/mach-bcm into next/soc
[linux-2.6-block.git] / arch / arm / boot / dts / rk3066a.dtsi
CommitLineData
d63dc051
HS		 1/*
2 * Copyright (c) 2013 MundoReader S.L.
3 * Author: Heiko Stuebner <heiko@sntech.de>
4 *
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License as published by
7 * the Free Software Foundation; either version 2 of the License, or
8 * (at your option) any later version.
9 *
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
14 */
15
16#include <dt-bindings/gpio/gpio.h>
d63dc051 17#include <dt-bindings/pinctrl/rockchip.h>
f75efdd7 18#include "rk3xxx.dtsi"
d63dc051
HS		 19#include "rk3066a-clocks.dtsi"
20
21/ {
22 compatible = "rockchip,rk3066a";
d63dc051
HS		 23
24 cpus {
25 #address-cells = <1>;
26 #size-cells = <0>;
27
28 cpu@0 {
29 device_type = "cpu";
30 compatible = "arm,cortex-a9";
31 next-level-cache = <&L2>;
32 reg = <0x0>;
33 };
34 cpu@1 {
35 device_type = "cpu";
36 compatible = "arm,cortex-a9";
37 next-level-cache = <&L2>;
38 reg = <0x1>;
39 };
40 };
41
42 soc {
d63dc051
HS		 43 timer@20038000 {
44 compatible = "snps,dw-apb-timer-osc";
45 reg = <0x20038000 0x100>;
46 interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>;
47 clocks = <&clk_gates1 0>, <&clk_gates7 7>;
48 clock-names = "timer", "pclk";
49 };
50
51 timer@2003a000 {
52 compatible = "snps,dw-apb-timer-osc";
53 reg = <0x2003a000 0x100>;
54 interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;
55 clocks = <&clk_gates1 1>, <&clk_gates7 8>;
56 clock-names = "timer", "pclk";
57 };
58
59 timer@2000e000 {
60 compatible = "snps,dw-apb-timer-osc";
61 reg = <0x2000e000 0x100>;
62 interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>;
63 clocks = <&clk_gates1 2>, <&clk_gates7 9>;
64 clock-names = "timer", "pclk";
65 };
66
de18e014
HS		 67 sram: sram@10080000 {
68 compatible = "mmio-sram";
69 reg = <0x10080000 0x10000>;
70 #address-cells = <1>;
71 #size-cells = <1>;
72 ranges = <0 0x10080000 0x10000>;
73
74 smp-sram@0 {
75 compatible = "rockchip,rk3066-smp-sram";
76 reg = <0x0 0x50>;
77 };
78 };
79
d63dc051
HS		 80 pinctrl@20008000 {
81 compatible = "rockchip,rk3066a-pinctrl";
82 reg = <0x20008000 0x150>;
83 #address-cells = <1>;
84 #size-cells = <1>;
85 ranges;
86
87 gpio0: gpio0@20034000 {
88 compatible = "rockchip,gpio-bank";
89 reg = <0x20034000 0x100>;
90 interrupts = <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>;
91 clocks = <&clk_gates8 9>;
92
93 gpio-controller;
94 #gpio-cells = <2>;
95
96 interrupt-controller;
97 #interrupt-cells = <2>;
98 };
99
100 gpio1: gpio1@2003c000 {
101 compatible = "rockchip,gpio-bank";
102 reg = <0x2003c000 0x100>;
103 interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>;
104 clocks = <&clk_gates8 10>;
105
106 gpio-controller;
107 #gpio-cells = <2>;
108
109 interrupt-controller;
110 #interrupt-cells = <2>;
111 };
112
113 gpio2: gpio2@2003e000 {
114 compatible = "rockchip,gpio-bank";
115 reg = <0x2003e000 0x100>;
116 interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>;
117 clocks = <&clk_gates8 11>;
118
119 gpio-controller;
120 #gpio-cells = <2>;
121
122 interrupt-controller;
123 #interrupt-cells = <2>;
124 };
125
126 gpio3: gpio3@20080000 {
127 compatible = "rockchip,gpio-bank";
128 reg = <0x20080000 0x100>;
129 interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>;
130 clocks = <&clk_gates8 12>;
131
132 gpio-controller;
133 #gpio-cells = <2>;
134
135 interrupt-controller;
136 #interrupt-cells = <2>;
137 };
138
139 gpio4: gpio4@20084000 {
140 compatible = "rockchip,gpio-bank";
141 reg = <0x20084000 0x100>;
142 interrupts = <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>;
143 clocks = <&clk_gates8 13>;
144
145 gpio-controller;
146 #gpio-cells = <2>;
147
148 interrupt-controller;
149 #interrupt-cells = <2>;
150 };
151
152 gpio6: gpio6@2000a000 {
153 compatible = "rockchip,gpio-bank";
154 reg = <0x2000a000 0x100>;
155 interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>;
156 clocks = <&clk_gates8 15>;
157
158 gpio-controller;
159 #gpio-cells = <2>;
160
161 interrupt-controller;
162 #interrupt-cells = <2>;
163 };
164
165 pcfg_pull_default: pcfg_pull_default {
166 bias-pull-pin-default;
167 };
168
169 pcfg_pull_none: pcfg_pull_none {
170 bias-disable;
171 };
172
173 uart0 {
174 uart0_xfer: uart0-xfer {
175 rockchip,pins = <RK_GPIO1 0 RK_FUNC_1 &pcfg_pull_default>,
176 <RK_GPIO1 1 RK_FUNC_1 &pcfg_pull_default>;
d63dc051
HS		 177 };
178
179 uart0_cts: uart0-cts {
180 rockchip,pins = <RK_GPIO1 2 RK_FUNC_1 &pcfg_pull_default>;
d63dc051
HS		 181 };
182
183 uart0_rts: uart0-rts {
184 rockchip,pins = <RK_GPIO1 3 RK_FUNC_1 &pcfg_pull_default>;
d63dc051
HS		 185 };
186 };
187
188 uart1 {
189 uart1_xfer: uart1-xfer {
190 rockchip,pins = <RK_GPIO1 4 RK_FUNC_1 &pcfg_pull_default>,
191 <RK_GPIO1 5 RK_FUNC_1 &pcfg_pull_default>;
d63dc051
HS		 192 };
193
194 uart1_cts: uart1-cts {
195 rockchip,pins = <RK_GPIO1 6 RK_FUNC_1 &pcfg_pull_default>;
d63dc051
HS		 196 };
197
198 uart1_rts: uart1-rts {
199 rockchip,pins = <RK_GPIO1 7 RK_FUNC_1 &pcfg_pull_default>;
d63dc051
HS		 200 };
201 };
202
203 uart2 {
204 uart2_xfer: uart2-xfer {
205 rockchip,pins = <RK_GPIO1 8 RK_FUNC_1 &pcfg_pull_default>,
206 <RK_GPIO1 9 RK_FUNC_1 &pcfg_pull_default>;
d63dc051
HS		 207 };
208 /* no rts / cts for uart2 */
209 };
210
211 uart3 {
212 uart3_xfer: uart3-xfer {
213 rockchip,pins = <RK_GPIO3 27 RK_FUNC_1 &pcfg_pull_default>,
214 <RK_GPIO3 28 RK_FUNC_1 &pcfg_pull_default>;
d63dc051
HS		 215 };
216
217 uart3_cts: uart3-cts {
218 rockchip,pins = <RK_GPIO3 29 RK_FUNC_1 &pcfg_pull_default>;
d63dc051
HS		 219 };
220
221 uart3_rts: uart3-rts {
222 rockchip,pins = <RK_GPIO3 30 RK_FUNC_1 &pcfg_pull_default>;
d63dc051
HS		 223 };
224 };
225
226 sd0 {
227 sd0_clk: sd0-clk {
228 rockchip,pins = <RK_GPIO3 8 RK_FUNC_1 &pcfg_pull_default>;
d63dc051
HS		 229 };
230
231 sd0_cmd: sd0-cmd {
232 rockchip,pins = <RK_GPIO3 9 RK_FUNC_1 &pcfg_pull_default>;
d63dc051
HS		 233 };
234
235 sd0_cd: sd0-cd {
236 rockchip,pins = <RK_GPIO3 14 RK_FUNC_1 &pcfg_pull_default>;
d63dc051
HS		 237 };
238
239 sd0_wp: sd0-wp {
240 rockchip,pins = <RK_GPIO3 15 RK_FUNC_1 &pcfg_pull_default>;
d63dc051
HS		 241 };
242
243 sd0_bus1: sd0-bus-width1 {
244 rockchip,pins = <RK_GPIO3 10 RK_FUNC_1 &pcfg_pull_default>;
d63dc051
HS		 245 };
246
247 sd0_bus4: sd0-bus-width4 {
248 rockchip,pins = <RK_GPIO3 10 RK_FUNC_1 &pcfg_pull_default>,
249 <RK_GPIO3 11 RK_FUNC_1 &pcfg_pull_default>,
250 <RK_GPIO3 12 RK_FUNC_1 &pcfg_pull_default>,
251 <RK_GPIO3 13 RK_FUNC_1 &pcfg_pull_default>;
d63dc051
HS		 252 };
253 };
254
255 sd1 {
256 sd1_clk: sd1-clk {
257 rockchip,pins = <RK_GPIO3 21 RK_FUNC_1 &pcfg_pull_default>;
d63dc051
HS		 258 };
259
260 sd1_cmd: sd1-cmd {
261 rockchip,pins = <RK_GPIO3 16 RK_FUNC_1 &pcfg_pull_default>;
d63dc051
HS		 262 };
263
264 sd1_cd: sd1-cd {
265 rockchip,pins = <RK_GPIO3 22 RK_FUNC_1 &pcfg_pull_default>;
d63dc051
HS		 266 };
267
268 sd1_wp: sd1-wp {
269 rockchip,pins = <RK_GPIO3 23 RK_FUNC_1 &pcfg_pull_default>;
d63dc051
HS		 270 };
271
272 sd1_bus1: sd1-bus-width1 {
273 rockchip,pins = <RK_GPIO3 17 RK_FUNC_1 &pcfg_pull_default>;
d63dc051
HS		 274 };
275
276 sd1_bus4: sd1-bus-width4 {
277 rockchip,pins = <RK_GPIO3 17 RK_FUNC_1 &pcfg_pull_default>,
278 <RK_GPIO3 18 RK_FUNC_1 &pcfg_pull_default>,
279 <RK_GPIO3 19 RK_FUNC_1 &pcfg_pull_default>,
280 <RK_GPIO3 20 RK_FUNC_1 &pcfg_pull_default>;
d63dc051
HS		 281 };
282 };
283 };
d63dc051
HS		 284 };
285};
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