[linux-block.git] / arch / arm / boot / dts / r9a06g032.dtsi

// SPDX-License-Identifier: GPL-2.0
/*
 * Base Device Tree Source for the Renesas RZ/N1D (R9A06G032)
 *
 * Copyright (C) 2018 Renesas Electronics Europe Limited
 *
 */

#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/clock/r9a06g032-sysctrl.h>

/ {
	compatible = "renesas,r9a06g032";
	#address-cells = <1>;
	#size-cells = <1>;

	cpus {
		#address-cells = <1>;
		#size-cells = <0>;

		cpu@0 {
			device_type = "cpu";
			compatible = "arm,cortex-a7";
			reg = <0>;
			clocks = <&sysctrl R9A06G032_CLK_A7MP>;
		};

		cpu@1 {
			device_type = "cpu";
			compatible = "arm,cortex-a7";
			reg = <1>;
			clocks = <&sysctrl R9A06G032_CLK_A7MP>;
			enable-method = "renesas,r9a06g032-smp";
			cpu-release-addr = <0 0x4000c204>;
		};
	};

	ext_jtag_clk: extjtagclk {
		#clock-cells = <0>;
		compatible = "fixed-clock";
		clock-frequency = <0>;
	};

	ext_mclk: extmclk {
		#clock-cells = <0>;
		compatible = "fixed-clock";
		clock-frequency = <40000000>;
	};

	ext_rgmii_ref: extrgmiiref {
		#clock-cells = <0>;
		compatible = "fixed-clock";
		clock-frequency = <0>;
	};

	ext_rtc_clk: extrtcclk {
		#clock-cells = <0>;
		compatible = "fixed-clock";
		clock-frequency = <0>;
	};

	soc {
		compatible = "simple-bus";
		#address-cells = <1>;
		#size-cells = <1>;
		interrupt-parent = <&gic>;
		ranges;

		wdt0: watchdog@40008000 {
			compatible = "renesas,r9a06g032-wdt", "renesas,rzn1-wdt";
			reg = <0x40008000 0x1000>;
			interrupts = <GIC_SPI 73 IRQ_TYPE_EDGE_RISING>;
			clocks = <&sysctrl R9A06G032_CLK_WATCHDOG>;
			status = "disabled";
		};

		wdt1: watchdog@40009000 {
			compatible = "renesas,r9a06g032-wdt", "renesas,rzn1-wdt";
			reg = <0x40009000 0x1000>;
			interrupts = <GIC_SPI 74 IRQ_TYPE_EDGE_RISING>;
			clocks = <&sysctrl R9A06G032_CLK_WATCHDOG>;
			status = "disabled";
		};

		sysctrl: system-controller@4000c000 {
			compatible = "renesas,r9a06g032-sysctrl";
			reg = <0x4000c000 0x1000>;
			status = "okay";
			#clock-cells = <1>;
			#power-domain-cells = <0>;

			clocks = <&ext_mclk>, <&ext_rtc_clk>,
					<&ext_jtag_clk>, <&ext_rgmii_ref>;
			clock-names = "mclk", "rtc", "jtag", "rgmii_ref_ext";
			#address-cells = <1>;
			#size-cells = <1>;

			dmamux: dma-router@a0 {
				compatible = "renesas,rzn1-dmamux";
				reg = <0xa0 4>;
				#dma-cells = <6>;
				dma-requests = <32>;
				dma-masters = <&dma0 &dma1>;
			};
		};

		uart0: serial@40060000 {
			compatible = "renesas,r9a06g032-uart", "renesas,rzn1-uart", "snps,dw-apb-uart";
			reg = <0x40060000 0x400>;
			interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
			reg-shift = <2>;
			reg-io-width = <4>;
			clocks = <&sysctrl R9A06G032_CLK_UART0>, <&sysctrl R9A06G032_HCLK_UART0>;
			clock-names = "baudclk", "apb_pclk";
			status = "disabled";
		};

		uart1: serial@40061000 {
			compatible = "renesas,r9a06g032-uart", "renesas,rzn1-uart", "snps,dw-apb-uart";
			reg = <0x40061000 0x400>;
			interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
			reg-shift = <2>;
			reg-io-width = <4>;
			clocks = <&sysctrl R9A06G032_CLK_UART1>, <&sysctrl R9A06G032_HCLK_UART1>;
			clock-names = "baudclk", "apb_pclk";
			status = "disabled";
		};

		uart2: serial@40062000 {
			compatible = "renesas,r9a06g032-uart", "renesas,rzn1-uart", "snps,dw-apb-uart";
			reg = <0x40062000 0x400>;
			interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
			reg-shift = <2>;
			reg-io-width = <4>;
			clocks = <&sysctrl R9A06G032_CLK_UART2>, <&sysctrl R9A06G032_HCLK_UART2>;
			clock-names = "baudclk", "apb_pclk";
			status = "disabled";
		};

		uart3: serial@50000000 {
			compatible = "renesas,r9a06g032-uart", "renesas,rzn1-uart";
			reg = <0x50000000 0x400>;
			interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
			reg-shift = <2>;
			reg-io-width = <4>;
			clocks = <&sysctrl R9A06G032_CLK_UART3>, <&sysctrl R9A06G032_HCLK_UART3>;
			clock-names = "baudclk", "apb_pclk";
			status = "disabled";
		};

		uart4: serial@50001000 {
			compatible = "renesas,r9a06g032-uart", "renesas,rzn1-uart";
			reg = <0x50001000 0x400>;
			interrupts = <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>;
			reg-shift = <2>;
			reg-io-width = <4>;
			clocks = <&sysctrl R9A06G032_CLK_UART4>, <&sysctrl R9A06G032_HCLK_UART4>;
			clock-names = "baudclk", "apb_pclk";
			status = "disabled";
		};

		uart5: serial@50002000 {
			compatible = "renesas,r9a06g032-uart", "renesas,rzn1-uart";
			reg = <0x50002000 0x400>;
			interrupts = <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>;
			reg-shift = <2>;
			reg-io-width = <4>;
			clocks = <&sysctrl R9A06G032_CLK_UART5>, <&sysctrl R9A06G032_HCLK_UART5>;
			clock-names = "baudclk", "apb_pclk";
			status = "disabled";
		};

		uart6: serial@50003000 {
			compatible = "renesas,r9a06g032-uart", "renesas,rzn1-uart";
			reg = <0x50003000 0x400>;
			interrupts = <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>;
			reg-shift = <2>;
			reg-io-width = <4>;
			clocks = <&sysctrl R9A06G032_CLK_UART6>, <&sysctrl R9A06G032_HCLK_UART6>;
			clock-names = "baudclk", "apb_pclk";
			status = "disabled";
		};

		uart7: serial@50004000 {
			compatible = "renesas,r9a06g032-uart", "renesas,rzn1-uart";
			reg = <0x50004000 0x400>;
			interrupts = <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>;
			reg-shift = <2>;
			reg-io-width = <4>;
			clocks = <&sysctrl R9A06G032_CLK_UART7>, <&sysctrl R9A06G032_HCLK_UART7>;
			clock-names = "baudclk", "apb_pclk";
			status = "disabled";
		};

		pinctrl: pinctrl@40067000 {
			compatible = "renesas,r9a06g032-pinctrl", "renesas,rzn1-pinctrl";
			reg = <0x40067000 0x1000>, <0x51000000 0x480>;
			clocks = <&sysctrl R9A06G032_HCLK_PINCONFIG>;
			clock-names = "bus";
			status = "okay";
		};

		nand_controller: nand-controller@40102000 {
			compatible = "renesas,r9a06g032-nandc", "renesas,rzn1-nandc";
			reg = <0x40102000 0x2000>;
			interrupts = <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&sysctrl R9A06G032_HCLK_NAND>, <&sysctrl R9A06G032_CLK_NAND>;
			clock-names = "hclk", "eclk";
			#address-cells = <1>;
			#size-cells = <0>;
			status = "disabled";
		};

		dma0: dma-controller@40104000 {
			compatible = "renesas,r9a06g032-dma", "renesas,rzn1-dma";
			reg = <0x40104000 0x1000>;
			interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>;
			clock-names = "hclk";
			clocks = <&sysctrl R9A06G032_HCLK_DMA0>;
			dma-channels = <8>;
			dma-requests = <16>;
			dma-masters = <1>;
			#dma-cells = <3>;
			block_size = <0xfff>;
			data-width = <8>;
		};

		dma1: dma-controller@40105000 {
			compatible = "renesas,r9a06g032-dma", "renesas,rzn1-dma";
			reg = <0x40105000 0x1000>;
			interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>;
			clock-names = "hclk";
			clocks = <&sysctrl R9A06G032_HCLK_DMA1>;
			dma-channels = <8>;
			dma-requests = <16>;
			dma-masters = <1>;
			#dma-cells = <3>;
			block_size = <0xfff>;
			data-width = <8>;
		};

		gic: interrupt-controller@44101000 {
			compatible = "arm,gic-400", "arm,cortex-a7-gic";
			interrupt-controller;
			#interrupt-cells = <3>;
			reg = <0x44101000 0x1000>, /* Distributer */
			      <0x44102000 0x2000>, /* CPU interface */
			      <0x44104000 0x2000>, /* Virt interface control */
			      <0x44106000 0x2000>; /* Virt CPU interface */
			interrupts =
				<GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_HIGH)>;
		};
	};

	timer {
		compatible = "arm,armv7-timer";
		interrupt-parent = <&gic>;
		arm,cpu-registers-not-fw-configured;
		always-on;
		interrupts =
			<GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
			<GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
			<GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
			<GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>;
	};
};
Commit	Line	Data
769d7248 MP	1	// SPDX-License-Identifier: GPL-2.0
	2	/*
	3	* Base Device Tree Source for the Renesas RZ/N1D (R9A06G032)
	4	*
	5	* Copyright (C) 2018 Renesas Electronics Europe Limited
	6	*
	7	*/
	8
	9	#include <dt-bindings/interrupt-controller/arm-gic.h>
1926bd6b	10	#include <dt-bindings/clock/r9a06g032-sysctrl.h>
769d7248 MP	11
	12	/ {
	13	compatible = "renesas,r9a06g032";
	14	#address-cells = <1>;
	15	#size-cells = <1>;
	16
	17	cpus {
	18	#address-cells = <1>;
	19	#size-cells = <0>;
	20
	21	cpu@0 {
	22	device_type = "cpu";
	23	compatible = "arm,cortex-a7";
	24	reg = <0>;
1926bd6b	25	clocks = <&sysctrl R9A06G032_CLK_A7MP>;
769d7248 MP	26	};
	27
	28	cpu@1 {
	29	device_type = "cpu";
	30	compatible = "arm,cortex-a7";
	31	reg = <1>;
1926bd6b	32	clocks = <&sysctrl R9A06G032_CLK_A7MP>;
f8fc94db MP	33	enable-method = "renesas,r9a06g032-smp";
f8fc94db MP	34	cpu-release-addr = <0 0x4000c204>;
769d7248 MP	35	};
	36	};
	37
	38	ext_jtag_clk: extjtagclk {
	39	#clock-cells = <0>;
	40	compatible = "fixed-clock";
	41	clock-frequency = <0>;
	42	};
	43
	44	ext_mclk: extmclk {
	45	#clock-cells = <0>;
	46	compatible = "fixed-clock";
	47	clock-frequency = <40000000>;
	48	};
	49
	50	ext_rgmii_ref: extrgmiiref {
	51	#clock-cells = <0>;
	52	compatible = "fixed-clock";
	53	clock-frequency = <0>;
	54	};
	55
	56	ext_rtc_clk: extrtcclk {
	57	#clock-cells = <0>;
	58	compatible = "fixed-clock";
	59	clock-frequency = <0>;
	60	};
	61
	62	soc {
	63	compatible = "simple-bus";
	64	#address-cells = <1>;
	65	#size-cells = <1>;
	66	interrupt-parent = <&gic>;
	67	ranges;
	68
045d0625 JJH	69	wdt0: watchdog@40008000 {
	70	compatible = "renesas,r9a06g032-wdt", "renesas,rzn1-wdt";
	71	reg = <0x40008000 0x1000>;
	72	interrupts = <GIC_SPI 73 IRQ_TYPE_EDGE_RISING>;
	73	clocks = <&sysctrl R9A06G032_CLK_WATCHDOG>;
	74	status = "disabled";
	75	};
	76
	77	wdt1: watchdog@40009000 {
	78	compatible = "renesas,r9a06g032-wdt", "renesas,rzn1-wdt";
	79	reg = <0x40009000 0x1000>;
	80	interrupts = <GIC_SPI 74 IRQ_TYPE_EDGE_RISING>;
	81	clocks = <&sysctrl R9A06G032_CLK_WATCHDOG>;
	82	status = "disabled";
	83	};
	84
769d7248 MP	85	sysctrl: system-controller@4000c000 {
	86	compatible = "renesas,r9a06g032-sysctrl";
	87	reg = <0x4000c000 0x1000>;
	88	status = "okay";
	89	#clock-cells = <1>;
ed66b37f	90	#power-domain-cells = <0>;
769d7248 MP	91
	92	clocks = <&ext_mclk>, <&ext_rtc_clk>,
	93	<&ext_jtag_clk>, <&ext_rgmii_ref>;
	94	clock-names = "mclk", "rtc", "jtag", "rgmii_ref_ext";
6002e2f1 MR	95	#address-cells = <1>;
	96	#size-cells = <1>;
	97
	98	dmamux: dma-router@a0 {
	99	compatible = "renesas,rzn1-dmamux";
	100	reg = <0xa0 4>;
	101	#dma-cells = <6>;
	102	dma-requests = <32>;
	103	dma-masters = <&dma0 &dma1>;
	104	};
769d7248 MP	105	};
	106
	107	uart0: serial@40060000 {
9aa2126f	108	compatible = "renesas,r9a06g032-uart", "renesas,rzn1-uart", "snps,dw-apb-uart";
769d7248 MP	109	reg = <0x40060000 0x400>;
	110	interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
	111	reg-shift = <2>;
	112	reg-io-width = <4>;
9aa2126f PE	113	clocks = <&sysctrl R9A06G032_CLK_UART0>, <&sysctrl R9A06G032_HCLK_UART0>;
	114	clock-names = "baudclk", "apb_pclk";
	115	status = "disabled";
	116	};
	117
	118	uart1: serial@40061000 {
	119	compatible = "renesas,r9a06g032-uart", "renesas,rzn1-uart", "snps,dw-apb-uart";
	120	reg = <0x40061000 0x400>;
	121	interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
	122	reg-shift = <2>;
	123	reg-io-width = <4>;
	124	clocks = <&sysctrl R9A06G032_CLK_UART1>, <&sysctrl R9A06G032_HCLK_UART1>;
	125	clock-names = "baudclk", "apb_pclk";
	126	status = "disabled";
	127	};
	128
	129	uart2: serial@40062000 {
	130	compatible = "renesas,r9a06g032-uart", "renesas,rzn1-uart", "snps,dw-apb-uart";
	131	reg = <0x40062000 0x400>;
	132	interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
	133	reg-shift = <2>;
	134	reg-io-width = <4>;
	135	clocks = <&sysctrl R9A06G032_CLK_UART2>, <&sysctrl R9A06G032_HCLK_UART2>;
	136	clock-names = "baudclk", "apb_pclk";
	137	status = "disabled";
	138	};
	139
	140	uart3: serial@50000000 {
	141	compatible = "renesas,r9a06g032-uart", "renesas,rzn1-uart";
	142	reg = <0x50000000 0x400>;
	143	interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
	144	reg-shift = <2>;
	145	reg-io-width = <4>;
	146	clocks = <&sysctrl R9A06G032_CLK_UART3>, <&sysctrl R9A06G032_HCLK_UART3>;
	147	clock-names = "baudclk", "apb_pclk";
	148	status = "disabled";
	149	};
	150
	151	uart4: serial@50001000 {
	152	compatible = "renesas,r9a06g032-uart", "renesas,rzn1-uart";
	153	reg = <0x50001000 0x400>;
	154	interrupts = <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>;
	155	reg-shift = <2>;
	156	reg-io-width = <4>;
	157	clocks = <&sysctrl R9A06G032_CLK_UART4>, <&sysctrl R9A06G032_HCLK_UART4>;
	158	clock-names = "baudclk", "apb_pclk";
	159	status = "disabled";
	160	};
	161
	162	uart5: serial@50002000 {
	163	compatible = "renesas,r9a06g032-uart", "renesas,rzn1-uart";
	164	reg = <0x50002000 0x400>;
	165	interrupts = <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>;
	166	reg-shift = <2>;
	167	reg-io-width = <4>;
	168	clocks = <&sysctrl R9A06G032_CLK_UART5>, <&sysctrl R9A06G032_HCLK_UART5>;
	169	clock-names = "baudclk", "apb_pclk";
	170	status = "disabled";
	171	};
	172
	173	uart6: serial@50003000 {
	174	compatible = "renesas,r9a06g032-uart", "renesas,rzn1-uart";
	175	reg = <0x50003000 0x400>;
	176	interrupts = <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>;
177	reg-shift = <2>;
178	reg-io-width = <4>;
179	clocks = <&sysctrl R9A06G032_CLK_UART6>, <&sysctrl R9A06G032_HCLK_UART6>;
180	clock-names = "baudclk", "apb_pclk";
181	status = "disabled";
182	};
183
184	uart7: serial@50004000 {
185	compatible = "renesas,r9a06g032-uart", "renesas,rzn1-uart";
186	reg = <0x50004000 0x400>;
187	interrupts = <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>;
188	reg-shift = <2>;
189	reg-io-width = <4>;
190	clocks = <&sysctrl R9A06G032_CLK_UART7>, <&sysctrl R9A06G032_HCLK_UART7>;
191	clock-names = "baudclk", "apb_pclk";
769d7248 MP	192	status = "disabled";
	193	};
	194
d9fd7ff5	195	pinctrl: pinctrl@40067000 {
ddeec86c PE	196	compatible = "renesas,r9a06g032-pinctrl", "renesas,rzn1-pinctrl";
	197	reg = <0x40067000 0x1000>, <0x51000000 0x480>;
	198	clocks = <&sysctrl R9A06G032_HCLK_PINCONFIG>;
	199	clock-names = "bus";
	200	status = "okay";
	201	};
	202
f2ad62a2 MR	203	nand_controller: nand-controller@40102000 {
	204	compatible = "renesas,r9a06g032-nandc", "renesas,rzn1-nandc";
	205	reg = <0x40102000 0x2000>;
	206	interrupts = <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>;
	207	clocks = <&sysctrl R9A06G032_HCLK_NAND>, <&sysctrl R9A06G032_CLK_NAND>;
	208	clock-names = "hclk", "eclk";
	209	#address-cells = <1>;
	210	#size-cells = <0>;
	211	status = "disabled";
	212	};
	213
257d24b3 MR	214	dma0: dma-controller@40104000 {
	215	compatible = "renesas,r9a06g032-dma", "renesas,rzn1-dma";
	216	reg = <0x40104000 0x1000>;
	217	interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>;
	218	clock-names = "hclk";
	219	clocks = <&sysctrl R9A06G032_HCLK_DMA0>;
	220	dma-channels = <8>;
	221	dma-requests = <16>;
	222	dma-masters = <1>;
	223	#dma-cells = <3>;
	224	block_size = <0xfff>;
	225	data-width = <8>;
	226	};
	227
	228	dma1: dma-controller@40105000 {
	229	compatible = "renesas,r9a06g032-dma", "renesas,rzn1-dma";
	230	reg = <0x40105000 0x1000>;
	231	interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>;
	232	clock-names = "hclk";
	233	clocks = <&sysctrl R9A06G032_HCLK_DMA1>;
	234	dma-channels = <8>;
	235	dma-requests = <16>;
	236	dma-masters = <1>;
	237	#dma-cells = <3>;
	238	block_size = <0xfff>;
	239	data-width = <8>;
	240	};
	241
673df60a	242	gic: interrupt-controller@44101000 {
b06424ce	243	compatible = "arm,gic-400", "arm,cortex-a7-gic";
769d7248 MP	244	interrupt-controller;
	245	#interrupt-cells = <3>;
	246	reg = <0x44101000 0x1000>, /* Distributer */
	247	<0x44102000 0x2000>, /* CPU interface */
	248	<0x44104000 0x2000>, /* Virt interface control */
	249	<0x44106000 0x2000>; /* Virt CPU interface */
	250	interrupts =
	251	<GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(2) \| IRQ_TYPE_LEVEL_HIGH)>;
	252	};
	253	};
	254
	255	timer {
aa70cbda	256	compatible = "arm,armv7-timer";
769d7248 MP	257	interrupt-parent = <&gic>;
	258	arm,cpu-registers-not-fw-configured;
	259	always-on;
	260	interrupts =
	261	<GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(2) \| IRQ_TYPE_LEVEL_LOW)>,
	262	<GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(2) \| IRQ_TYPE_LEVEL_LOW)>,
	263	<GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(2) \| IRQ_TYPE_LEVEL_LOW)>,
	264	<GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(2) \| IRQ_TYPE_LEVEL_LOW)>;
	265	};
	266	};