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ARM: shmobile: r8a7794: link PCI USB devices to USB PHY
[linux-2.6-block.git] / arch / arm / boot / dts / r8a7794.dtsi
CommitLineData
0dce5454
UH		 1/*
2 * Device Tree Source for the r8a7794 SoC
3 *
4 * Copyright (C) 2014 Renesas Electronics Corporation
5 * Copyright (C) 2014 Ulrich Hecht
6 *
7 * This file is licensed under the terms of the GNU General Public License
8 * version 2. This program is licensed "as is" without any warranty of any
9 * kind, whether express or implied.
10 */
11
12#include <dt-bindings/clock/r8a7794-clock.h>
13#include <dt-bindings/interrupt-controller/arm-gic.h>
14#include <dt-bindings/interrupt-controller/irq.h>
15
16/ {
17 compatible = "renesas,r8a7794";
18 interrupt-parent = <&gic>;
19 #address-cells = <2>;
20 #size-cells = <2>;
21
740b4a9f 22 aliases {
5428521b
SS		 23 i2c0 = &i2c0;
24 i2c1 = &i2c1;
25 i2c2 = &i2c2;
26 i2c3 = &i2c3;
27 i2c4 = &i2c4;
28 i2c5 = &i2c5;
740b4a9f 29 spi0 = &qspi;
1afe77ca
SS		 30 vin0 = &vin0;
31 vin1 = &vin1;
740b4a9f
SS		 32 };
33
0dce5454
UH		 34 cpus {
35 #address-cells = <1>;
36 #size-cells = <0>;
37
38 cpu0: cpu@0 {
39 device_type = "cpu";
40 compatible = "arm,cortex-a7";
41 reg = <0>;
42 clock-frequency = <1000000000>;
43 };
44
45 cpu1: cpu@1 {
46 device_type = "cpu";
47 compatible = "arm,cortex-a7";
48 reg = <1>;
49 clock-frequency = <1000000000>;
50 };
51 };
52
53 gic: interrupt-controller@f1001000 {
c73ddf42 54 compatible = "arm,gic-400";
0dce5454
UH		 55 #interrupt-cells = <3>;
56 #address-cells = <0>;
57 interrupt-controller;
58 reg = <0 0xf1001000 0 0x1000>,
59 <0 0xf1002000 0 0x1000>,
60 <0 0xf1004000 0 0x2000>,
61 <0 0xf1006000 0 0x2000>;
00add867 62 interrupts = <1 9 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_HIGH)>;
0dce5454
UH		 63 };
64
e8f5de3b
SS		 65 gpio0: gpio@e6050000 {
66 compatible = "renesas,gpio-r8a7794", "renesas,gpio-rcar";
67 reg = <0 0xe6050000 0 0x50>;
68 interrupts = <0 4 IRQ_TYPE_LEVEL_HIGH>;
69 #gpio-cells = <2>;
70 gpio-controller;
71 gpio-ranges = <&pfc 0 0 32>;
72 #interrupt-cells = <2>;
73 interrupt-controller;
74 clocks = <&mstp9_clks R8A7794_CLK_GPIO0>;
75 power-domains = <&cpg_clocks>;
76 };
77
78 gpio1: gpio@e6051000 {
79 compatible = "renesas,gpio-r8a7794", "renesas,gpio-rcar";
80 reg = <0 0xe6051000 0 0x50>;
81 interrupts = <0 5 IRQ_TYPE_LEVEL_HIGH>;
82 #gpio-cells = <2>;
83 gpio-controller;
84 gpio-ranges = <&pfc 0 32 26>;
85 #interrupt-cells = <2>;
86 interrupt-controller;
87 clocks = <&mstp9_clks R8A7794_CLK_GPIO1>;
88 power-domains = <&cpg_clocks>;
89 };
90
91 gpio2: gpio@e6052000 {
92 compatible = "renesas,gpio-r8a7794", "renesas,gpio-rcar";
93 reg = <0 0xe6052000 0 0x50>;
94 interrupts = <0 6 IRQ_TYPE_LEVEL_HIGH>;
95 #gpio-cells = <2>;
96 gpio-controller;
97 gpio-ranges = <&pfc 0 64 32>;
98 #interrupt-cells = <2>;
99 interrupt-controller;
100 clocks = <&mstp9_clks R8A7794_CLK_GPIO2>;
101 power-domains = <&cpg_clocks>;
102 };
103
104 gpio3: gpio@e6053000 {
105 compatible = "renesas,gpio-r8a7794", "renesas,gpio-rcar";
106 reg = <0 0xe6053000 0 0x50>;
107 interrupts = <0 7 IRQ_TYPE_LEVEL_HIGH>;
108 #gpio-cells = <2>;
109 gpio-controller;
110 gpio-ranges = <&pfc 0 96 32>;
111 #interrupt-cells = <2>;
112 interrupt-controller;
113 clocks = <&mstp9_clks R8A7794_CLK_GPIO3>;
114 power-domains = <&cpg_clocks>;
115 };
116
117 gpio4: gpio@e6054000 {
118 compatible = "renesas,gpio-r8a7794", "renesas,gpio-rcar";
119 reg = <0 0xe6054000 0 0x50>;
120 interrupts = <0 8 IRQ_TYPE_LEVEL_HIGH>;
121 #gpio-cells = <2>;
122 gpio-controller;
123 gpio-ranges = <&pfc 0 128 32>;
124 #interrupt-cells = <2>;
125 interrupt-controller;
126 clocks = <&mstp9_clks R8A7794_CLK_GPIO4>;
127 power-domains = <&cpg_clocks>;
128 };
129
130 gpio5: gpio@e6055000 {
131 compatible = "renesas,gpio-r8a7794", "renesas,gpio-rcar";
132 reg = <0 0xe6055000 0 0x50>;
133 interrupts = <0 9 IRQ_TYPE_LEVEL_HIGH>;
134 #gpio-cells = <2>;
135 gpio-controller;
136 gpio-ranges = <&pfc 0 160 28>;
137 #interrupt-cells = <2>;
138 interrupt-controller;
139 clocks = <&mstp9_clks R8A7794_CLK_GPIO5>;
140 power-domains = <&cpg_clocks>;
141 };
142
143 gpio6: gpio@e6055400 {
144 compatible = "renesas,gpio-r8a7794", "renesas,gpio-rcar";
145 reg = <0 0xe6055400 0 0x50>;
146 interrupts = <0 10 IRQ_TYPE_LEVEL_HIGH>;
147 #gpio-cells = <2>;
148 gpio-controller;
149 gpio-ranges = <&pfc 0 192 26>;
150 #interrupt-cells = <2>;
151 interrupt-controller;
152 clocks = <&mstp9_clks R8A7794_CLK_GPIO6>;
153 power-domains = <&cpg_clocks>;
154 };
155
0dce5454
UH		 156 cmt0: timer@ffca0000 {
157 compatible = "renesas,cmt-48-gen2";
158 reg = <0 0xffca0000 0 0x1004>;
159 interrupts = <0 142 IRQ_TYPE_LEVEL_HIGH>,
160 <0 143 IRQ_TYPE_LEVEL_HIGH>;
161 clocks = <&mstp1_clks R8A7794_CLK_CMT0>;
162 clock-names = "fck";
60c0745a 163 power-domains = <&cpg_clocks>;
0dce5454
UH		 164
165 renesas,channels-mask = <0x60>;
166
167 status = "disabled";
168 };
169
170 cmt1: timer@e6130000 {
171 compatible = "renesas,cmt-48-gen2";
172 reg = <0 0xe6130000 0 0x1004>;
173 interrupts = <0 120 IRQ_TYPE_LEVEL_HIGH>,
174 <0 121 IRQ_TYPE_LEVEL_HIGH>,
175 <0 122 IRQ_TYPE_LEVEL_HIGH>,
176 <0 123 IRQ_TYPE_LEVEL_HIGH>,
177 <0 124 IRQ_TYPE_LEVEL_HIGH>,
178 <0 125 IRQ_TYPE_LEVEL_HIGH>,
179 <0 126 IRQ_TYPE_LEVEL_HIGH>,
180 <0 127 IRQ_TYPE_LEVEL_HIGH>;
181 clocks = <&mstp3_clks R8A7794_CLK_CMT1>;
182 clock-names = "fck";
60c0745a 183 power-domains = <&cpg_clocks>;
0dce5454
UH		 184
185 renesas,channels-mask = <0xff>;
186
187 status = "disabled";
188 };
189
da33648c
HN		 190 timer {
191 compatible = "arm,armv7-timer";
00add867
GU		 192 interrupts = <1 13 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
193 <1 14 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
194 <1 11 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
195 <1 10 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>;
da33648c
HN		 196 };
197
0dce5454
UH		 198 irqc0: interrupt-controller@e61c0000 {
199 compatible = "renesas,irqc-r8a7794", "renesas,irqc";
200 #interrupt-cells = <2>;
201 interrupt-controller;
202 reg = <0 0xe61c0000 0 0x200>;
203 interrupts = <0 0 IRQ_TYPE_LEVEL_HIGH>,
204 <0 1 IRQ_TYPE_LEVEL_HIGH>,
205 <0 2 IRQ_TYPE_LEVEL_HIGH>,
206 <0 3 IRQ_TYPE_LEVEL_HIGH>,
207 <0 12 IRQ_TYPE_LEVEL_HIGH>,
208 <0 13 IRQ_TYPE_LEVEL_HIGH>,
209 <0 14 IRQ_TYPE_LEVEL_HIGH>,
210 <0 15 IRQ_TYPE_LEVEL_HIGH>,
211 <0 16 IRQ_TYPE_LEVEL_HIGH>,
212 <0 17 IRQ_TYPE_LEVEL_HIGH>;
1c5ca5db 213 clocks = <&mstp4_clks R8A7794_CLK_IRQC>;
60c0745a 214 power-domains = <&cpg_clocks>;
0dce5454
UH		 215 };
216
fd1683c1
SS		 217 pfc: pin-controller@e6060000 {
218 compatible = "renesas,pfc-r8a7794";
219 reg = <0 0xe6060000 0 0x11c>;
220 #gpio-range-cells = <3>;
221 };
222
bd847485
LP		 223 dmac0: dma-controller@e6700000 {
224 compatible = "renesas,rcar-dmac";
225 reg = <0 0xe6700000 0 0x20000>;
226 interrupts = <0 197 IRQ_TYPE_LEVEL_HIGH
227 0 200 IRQ_TYPE_LEVEL_HIGH
228 0 201 IRQ_TYPE_LEVEL_HIGH
229 0 202 IRQ_TYPE_LEVEL_HIGH
230 0 203 IRQ_TYPE_LEVEL_HIGH
231 0 204 IRQ_TYPE_LEVEL_HIGH
232 0 205 IRQ_TYPE_LEVEL_HIGH
233 0 206 IRQ_TYPE_LEVEL_HIGH
234 0 207 IRQ_TYPE_LEVEL_HIGH
235 0 208 IRQ_TYPE_LEVEL_HIGH
236 0 209 IRQ_TYPE_LEVEL_HIGH
237 0 210 IRQ_TYPE_LEVEL_HIGH
238 0 211 IRQ_TYPE_LEVEL_HIGH
239 0 212 IRQ_TYPE_LEVEL_HIGH
240 0 213 IRQ_TYPE_LEVEL_HIGH
241 0 214 IRQ_TYPE_LEVEL_HIGH>;
242 interrupt-names = "error",
243 "ch0", "ch1", "ch2", "ch3",
244 "ch4", "ch5", "ch6", "ch7",
245 "ch8", "ch9", "ch10", "ch11",
246 "ch12", "ch13", "ch14";
247 clocks = <&mstp2_clks R8A7794_CLK_SYS_DMAC0>;
248 clock-names = "fck";
60c0745a 249 power-domains = <&cpg_clocks>;
bd847485
LP		 250 #dma-cells = <1>;
251 dma-channels = <15>;
252 };
253
254 dmac1: dma-controller@e6720000 {
255 compatible = "renesas,rcar-dmac";
256 reg = <0 0xe6720000 0 0x20000>;
257 interrupts = <0 220 IRQ_TYPE_LEVEL_HIGH
258 0 216 IRQ_TYPE_LEVEL_HIGH
259 0 217 IRQ_TYPE_LEVEL_HIGH
260 0 218 IRQ_TYPE_LEVEL_HIGH
261 0 219 IRQ_TYPE_LEVEL_HIGH
262 0 308 IRQ_TYPE_LEVEL_HIGH
263 0 309 IRQ_TYPE_LEVEL_HIGH
264 0 310 IRQ_TYPE_LEVEL_HIGH
265 0 311 IRQ_TYPE_LEVEL_HIGH
266 0 312 IRQ_TYPE_LEVEL_HIGH
267 0 313 IRQ_TYPE_LEVEL_HIGH
268 0 314 IRQ_TYPE_LEVEL_HIGH
269 0 315 IRQ_TYPE_LEVEL_HIGH
270 0 316 IRQ_TYPE_LEVEL_HIGH
271 0 317 IRQ_TYPE_LEVEL_HIGH
272 0 318 IRQ_TYPE_LEVEL_HIGH>;
273 interrupt-names = "error",
274 "ch0", "ch1", "ch2", "ch3",
275 "ch4", "ch5", "ch6", "ch7",
276 "ch8", "ch9", "ch10", "ch11",
277 "ch12", "ch13", "ch14";
278 clocks = <&mstp2_clks R8A7794_CLK_SYS_DMAC1>;
279 clock-names = "fck";
60c0745a 280 power-domains = <&cpg_clocks>;
bd847485
LP		 281 #dma-cells = <1>;
282 dma-channels = <15>;
283 };
284
0dce5454
UH		 285 scifa0: serial@e6c40000 {
286 compatible = "renesas,scifa-r8a7794", "renesas,scifa";
287 reg = <0 0xe6c40000 0 64>;
288 interrupts = <0 144 IRQ_TYPE_LEVEL_HIGH>;
289 clocks = <&mstp2_clks R8A7794_CLK_SCIFA0>;
290 clock-names = "sci_ick";
8233a0de
GU		 291 dmas = <&dmac0 0x21>, <&dmac0 0x22>;
292 dma-names = "tx", "rx";
60c0745a 293 power-domains = <&cpg_clocks>;
0dce5454
UH		 294 status = "disabled";
295 };
296
297 scifa1: serial@e6c50000 {
298 compatible = "renesas,scifa-r8a7794", "renesas,scifa";
299 reg = <0 0xe6c50000 0 64>;
300 interrupts = <0 145 IRQ_TYPE_LEVEL_HIGH>;
301 clocks = <&mstp2_clks R8A7794_CLK_SCIFA1>;
302 clock-names = "sci_ick";
8233a0de
GU		 303 dmas = <&dmac0 0x25>, <&dmac0 0x26>;
304 dma-names = "tx", "rx";
60c0745a 305 power-domains = <&cpg_clocks>;
0dce5454
UH		 306 status = "disabled";
307 };
308
309 scifa2: serial@e6c60000 {
310 compatible = "renesas,scifa-r8a7794", "renesas,scifa";
311 reg = <0 0xe6c60000 0 64>;
312 interrupts = <0 151 IRQ_TYPE_LEVEL_HIGH>;
313 clocks = <&mstp2_clks R8A7794_CLK_SCIFA2>;
314 clock-names = "sci_ick";
8233a0de
GU		 315 dmas = <&dmac0 0x27>, <&dmac0 0x28>;
316 dma-names = "tx", "rx";
60c0745a 317 power-domains = <&cpg_clocks>;
0dce5454
UH		 318 status = "disabled";
319 };
320
321 scifa3: serial@e6c70000 {
322 compatible = "renesas,scifa-r8a7794", "renesas,scifa";
323 reg = <0 0xe6c70000 0 64>;
324 interrupts = <0 29 IRQ_TYPE_LEVEL_HIGH>;
325 clocks = <&mstp11_clks R8A7794_CLK_SCIFA3>;
326 clock-names = "sci_ick";
8233a0de
GU		 327 dmas = <&dmac0 0x1b>, <&dmac0 0x1c>;
328 dma-names = "tx", "rx";
60c0745a 329 power-domains = <&cpg_clocks>;
0dce5454
UH		 330 status = "disabled";
331 };
332
333 scifa4: serial@e6c78000 {
334 compatible = "renesas,scifa-r8a7794", "renesas,scifa";
335 reg = <0 0xe6c78000 0 64>;
336 interrupts = <0 30 IRQ_TYPE_LEVEL_HIGH>;
337 clocks = <&mstp11_clks R8A7794_CLK_SCIFA4>;
338 clock-names = "sci_ick";
8233a0de
GU		 339 dmas = <&dmac0 0x1f>, <&dmac0 0x20>;
340 dma-names = "tx", "rx";
60c0745a 341 power-domains = <&cpg_clocks>;
0dce5454
UH		 342 status = "disabled";
343 };
344
345 scifa5: serial@e6c80000 {
346 compatible = "renesas,scifa-r8a7794", "renesas,scifa";
347 reg = <0 0xe6c80000 0 64>;
348 interrupts = <0 31 IRQ_TYPE_LEVEL_HIGH>;
349 clocks = <&mstp11_clks R8A7794_CLK_SCIFA5>;
350 clock-names = "sci_ick";
8233a0de
GU		 351 dmas = <&dmac0 0x23>, <&dmac0 0x24>;
352 dma-names = "tx", "rx";
60c0745a 353 power-domains = <&cpg_clocks>;
0dce5454
UH		 354 status = "disabled";
355 };
356
357 scifb0: serial@e6c20000 {
358 compatible = "renesas,scifb-r8a7794", "renesas,scifb";
359 reg = <0 0xe6c20000 0 64>;
360 interrupts = <0 148 IRQ_TYPE_LEVEL_HIGH>;
361 clocks = <&mstp2_clks R8A7794_CLK_SCIFB0>;
362 clock-names = "sci_ick";
8233a0de
GU		 363 dmas = <&dmac0 0x3d>, <&dmac0 0x3e>;
364 dma-names = "tx", "rx";
60c0745a 365 power-domains = <&cpg_clocks>;
0dce5454
UH		 366 status = "disabled";
367 };
368
369 scifb1: serial@e6c30000 {
370 compatible = "renesas,scifb-r8a7794", "renesas,scifb";
371 reg = <0 0xe6c30000 0 64>;
372 interrupts = <0 149 IRQ_TYPE_LEVEL_HIGH>;
373 clocks = <&mstp2_clks R8A7794_CLK_SCIFB1>;
374 clock-names = "sci_ick";
8233a0de
GU		 375 dmas = <&dmac0 0x19>, <&dmac0 0x1a>;
376 dma-names = "tx", "rx";
60c0745a 377 power-domains = <&cpg_clocks>;
0dce5454
UH		 378 status = "disabled";
379 };
380
381 scifb2: serial@e6ce0000 {
382 compatible = "renesas,scifb-r8a7794", "renesas,scifb";
383 reg = <0 0xe6ce0000 0 64>;
384 interrupts = <0 150 IRQ_TYPE_LEVEL_HIGH>;
385 clocks = <&mstp2_clks R8A7794_CLK_SCIFB2>;
386 clock-names = "sci_ick";
8233a0de
GU		 387 dmas = <&dmac0 0x1d>, <&dmac0 0x1e>;
388 dma-names = "tx", "rx";
60c0745a 389 power-domains = <&cpg_clocks>;
0dce5454
UH		 390 status = "disabled";
391 };
392
393 scif0: serial@e6e60000 {
394 compatible = "renesas,scif-r8a7794", "renesas,scif";
395 reg = <0 0xe6e60000 0 64>;
396 interrupts = <0 152 IRQ_TYPE_LEVEL_HIGH>;
397 clocks = <&mstp7_clks R8A7794_CLK_SCIF0>;
398 clock-names = "sci_ick";
8233a0de
GU		 399 dmas = <&dmac0 0x29>, <&dmac0 0x2a>;
400 dma-names = "tx", "rx";
60c0745a 401 power-domains = <&cpg_clocks>;
0dce5454
UH		 402 status = "disabled";
403 };
404
405 scif1: serial@e6e68000 {
406 compatible = "renesas,scif-r8a7794", "renesas,scif";
407 reg = <0 0xe6e68000 0 64>;
408 interrupts = <0 153 IRQ_TYPE_LEVEL_HIGH>;
409 clocks = <&mstp7_clks R8A7794_CLK_SCIF1>;
410 clock-names = "sci_ick";
8233a0de
GU		 411 dmas = <&dmac0 0x2d>, <&dmac0 0x2e>;
412 dma-names = "tx", "rx";
60c0745a 413 power-domains = <&cpg_clocks>;
0dce5454
UH		 414 status = "disabled";
415 };
416
417 scif2: serial@e6e58000 {
418 compatible = "renesas,scif-r8a7794", "renesas,scif";
419 reg = <0 0xe6e58000 0 64>;
420 interrupts = <0 22 IRQ_TYPE_LEVEL_HIGH>;
421 clocks = <&mstp7_clks R8A7794_CLK_SCIF2>;
422 clock-names = "sci_ick";
8233a0de
GU		 423 dmas = <&dmac0 0x2b>, <&dmac0 0x2c>;
424 dma-names = "tx", "rx";
60c0745a 425 power-domains = <&cpg_clocks>;
0dce5454
UH		 426 status = "disabled";
427 };
428
429 scif3: serial@e6ea8000 {
430 compatible = "renesas,scif-r8a7794", "renesas,scif";
431 reg = <0 0xe6ea8000 0 64>;
432 interrupts = <0 23 IRQ_TYPE_LEVEL_HIGH>;
433 clocks = <&mstp7_clks R8A7794_CLK_SCIF3>;
434 clock-names = "sci_ick";
8233a0de
GU		 435 dmas = <&dmac0 0x2f>, <&dmac0 0x30>;
436 dma-names = "tx", "rx";
60c0745a 437 power-domains = <&cpg_clocks>;
0dce5454
UH		 438 status = "disabled";
439 };
440
441 scif4: serial@e6ee0000 {
442 compatible = "renesas,scif-r8a7794", "renesas,scif";
443 reg = <0 0xe6ee0000 0 64>;
444 interrupts = <0 24 IRQ_TYPE_LEVEL_HIGH>;
445 clocks = <&mstp7_clks R8A7794_CLK_SCIF4>;
446 clock-names = "sci_ick";
8233a0de
GU		 447 dmas = <&dmac0 0xfb>, <&dmac0 0xfc>;
448 dma-names = "tx", "rx";
60c0745a 449 power-domains = <&cpg_clocks>;
0dce5454
UH		 450 status = "disabled";
451 };
452
453 scif5: serial@e6ee8000 {
454 compatible = "renesas,scif-r8a7794", "renesas,scif";
455 reg = <0 0xe6ee8000 0 64>;
456 interrupts = <0 25 IRQ_TYPE_LEVEL_HIGH>;
457 clocks = <&mstp7_clks R8A7794_CLK_SCIF5>;
458 clock-names = "sci_ick";
8233a0de
GU		 459 dmas = <&dmac0 0xfd>, <&dmac0 0xfe>;
460 dma-names = "tx", "rx";
60c0745a 461 power-domains = <&cpg_clocks>;
0dce5454
UH		 462 status = "disabled";
463 };
464
465 hscif0: serial@e62c0000 {
466 compatible = "renesas,hscif-r8a7794", "renesas,hscif";
467 reg = <0 0xe62c0000 0 96>;
468 interrupts = <0 154 IRQ_TYPE_LEVEL_HIGH>;
469 clocks = <&mstp7_clks R8A7794_CLK_HSCIF0>;
470 clock-names = "sci_ick";
8233a0de
GU		 471 dmas = <&dmac0 0x39>, <&dmac0 0x3a>;
472 dma-names = "tx", "rx";
60c0745a 473 power-domains = <&cpg_clocks>;
0dce5454
UH		 474 status = "disabled";
475 };
476
477 hscif1: serial@e62c8000 {
478 compatible = "renesas,hscif-r8a7794", "renesas,hscif";
479 reg = <0 0xe62c8000 0 96>;
480 interrupts = <0 155 IRQ_TYPE_LEVEL_HIGH>;
481 clocks = <&mstp7_clks R8A7794_CLK_HSCIF1>;
482 clock-names = "sci_ick";
8233a0de
GU		 483 dmas = <&dmac0 0x4d>, <&dmac0 0x4e>;
484 dma-names = "tx", "rx";
60c0745a 485 power-domains = <&cpg_clocks>;
0dce5454
UH		 486 status = "disabled";
487 };
488
489 hscif2: serial@e62d0000 {
490 compatible = "renesas,hscif-r8a7794", "renesas,hscif";
491 reg = <0 0xe62d0000 0 96>;
492 interrupts = <0 21 IRQ_TYPE_LEVEL_HIGH>;
493 clocks = <&mstp7_clks R8A7794_CLK_HSCIF2>;
494 clock-names = "sci_ick";
8233a0de
GU		 495 dmas = <&dmac0 0x3b>, <&dmac0 0x3c>;
496 dma-names = "tx", "rx";
60c0745a 497 power-domains = <&cpg_clocks>;
0dce5454
UH		 498 status = "disabled";
499 };
500
82818d34
LP		 501 ether: ethernet@ee700000 {
502 compatible = "renesas,ether-r8a7794";
503 reg = <0 0xee700000 0 0x400>;
504 interrupts = <0 162 IRQ_TYPE_LEVEL_HIGH>;
505 clocks = <&mstp8_clks R8A7794_CLK_ETHER>;
60c0745a 506 power-domains = <&cpg_clocks>;
82818d34
LP		 507 phy-mode = "rmii";
508 #address-cells = <1>;
509 #size-cells = <0>;
510 status = "disabled";
511 };
512
5428521b
SS		 513 /* The memory map in the User's Manual maps the cores to bus numbers */
514 i2c0: i2c@e6508000 {
515 compatible = "renesas,i2c-r8a7794";
516 reg = <0 0xe6508000 0 0x40>;
517 interrupts = <0 287 IRQ_TYPE_LEVEL_HIGH>;
518 clocks = <&mstp9_clks R8A7794_CLK_I2C0>;
519 power-domains = <&cpg_clocks>;
520 #address-cells = <1>;
521 #size-cells = <0>;
522 status = "disabled";
523 };
524
525 i2c1: i2c@e6518000 {
526 compatible = "renesas,i2c-r8a7794";
527 reg = <0 0xe6518000 0 0x40>;
528 interrupts = <0 288 IRQ_TYPE_LEVEL_HIGH>;
529 clocks = <&mstp9_clks R8A7794_CLK_I2C1>;
530 power-domains = <&cpg_clocks>;
531 #address-cells = <1>;
532 #size-cells = <0>;
533 status = "disabled";
534 };
535
536 i2c2: i2c@e6530000 {
537 compatible = "renesas,i2c-r8a7794";
538 reg = <0 0xe6530000 0 0x40>;
539 interrupts = <0 286 IRQ_TYPE_LEVEL_HIGH>;
540 clocks = <&mstp9_clks R8A7794_CLK_I2C2>;
541 power-domains = <&cpg_clocks>;
542 #address-cells = <1>;
543 #size-cells = <0>;
544 status = "disabled";
545 };
546
547 i2c3: i2c@e6540000 {
548 compatible = "renesas,i2c-r8a7794";
549 reg = <0 0xe6540000 0 0x40>;
550 interrupts = <0 290 IRQ_TYPE_LEVEL_HIGH>;
551 clocks = <&mstp9_clks R8A7794_CLK_I2C3>;
552 power-domains = <&cpg_clocks>;
553 #address-cells = <1>;
554 #size-cells = <0>;
555 status = "disabled";
556 };
557
558 i2c4: i2c@e6520000 {
559 compatible = "renesas,i2c-r8a7794";
560 reg = <0 0xe6520000 0 0x40>;
561 interrupts = <0 19 IRQ_TYPE_LEVEL_HIGH>;
562 clocks = <&mstp9_clks R8A7794_CLK_I2C4>;
563 power-domains = <&cpg_clocks>;
564 #address-cells = <1>;
565 #size-cells = <0>;
566 status = "disabled";
567 };
568
569 i2c5: i2c@e6528000 {
570 compatible = "renesas,i2c-r8a7794";
571 reg = <0 0xe6528000 0 0x40>;
572 interrupts = <0 20 IRQ_TYPE_LEVEL_HIGH>;
573 clocks = <&mstp9_clks R8A7794_CLK_I2C5>;
574 power-domains = <&cpg_clocks>;
575 #address-cells = <1>;
576 #size-cells = <0>;
577 status = "disabled";
578 };
579
6cdf6ba1
SS		 580 mmcif0: mmc@ee200000 {
581 compatible = "renesas,mmcif-r8a7794", "renesas,sh-mmcif";
582 reg = <0 0xee200000 0 0x80>;
583 interrupts = <0 169 IRQ_TYPE_LEVEL_HIGH>;
584 clocks = <&mstp3_clks R8A7794_CLK_MMCIF0>;
585 dmas = <&dmac0 0xd1>, <&dmac0 0xd2>;
586 dma-names = "tx", "rx";
60c0745a 587 power-domains = <&cpg_clocks>;
6cdf6ba1
SS		 588 reg-io-width = <4>;
589 status = "disabled";
590 };
591
b8e8ea12
SS		 592 sdhi0: sd@ee100000 {
593 compatible = "renesas,sdhi-r8a7794";
594 reg = <0 0xee100000 0 0x200>;
595 interrupts = <0 165 IRQ_TYPE_LEVEL_HIGH>;
596 clocks = <&mstp3_clks R8A7794_CLK_SDHI0>;
60c0745a 597 power-domains = <&cpg_clocks>;
b8e8ea12
SS		 598 status = "disabled";
599 };
600
601 sdhi1: sd@ee140000 {
602 compatible = "renesas,sdhi-r8a7794";
603 reg = <0 0xee140000 0 0x100>;
604 interrupts = <0 167 IRQ_TYPE_LEVEL_HIGH>;
605 clocks = <&mstp3_clks R8A7794_CLK_SDHI1>;
60c0745a 606 power-domains = <&cpg_clocks>;
b8e8ea12
SS		 607 status = "disabled";
608 };
609
610 sdhi2: sd@ee160000 {
611 compatible = "renesas,sdhi-r8a7794";
612 reg = <0 0xee160000 0 0x100>;
613 interrupts = <0 168 IRQ_TYPE_LEVEL_HIGH>;
614 clocks = <&mstp3_clks R8A7794_CLK_SDHI2>;
60c0745a 615 power-domains = <&cpg_clocks>;
b8e8ea12
SS		 616 status = "disabled";
617 };
618
740b4a9f
SS		 619 qspi: spi@e6b10000 {
620 compatible = "renesas,qspi-r8a7794", "renesas,qspi";
621 reg = <0 0xe6b10000 0 0x2c>;
622 interrupts = <0 184 IRQ_TYPE_LEVEL_HIGH>;
623 clocks = <&mstp9_clks R8A7794_CLK_QSPI_MOD>;
624 dmas = <&dmac0 0x17>, <&dmac0 0x18>;
625 dma-names = "tx", "rx";
626 power-domains = <&cpg_clocks>;
627 num-cs = <1>;
628 #address-cells = <1>;
629 #size-cells = <0>;
630 status = "disabled";
631 };
632
1afe77ca
SS		 633 vin0: video@e6ef0000 {
634 compatible = "renesas,vin-r8a7794";
635 reg = <0 0xe6ef0000 0 0x1000>;
636 interrupts = <0 188 IRQ_TYPE_LEVEL_HIGH>;
637 clocks = <&mstp8_clks R8A7794_CLK_VIN0>;
638 power-domains = <&cpg_clocks>;
639 status = "disabled";
640 };
641
642 vin1: video@e6ef1000 {
643 compatible = "renesas,vin-r8a7794";
644 reg = <0 0xe6ef1000 0 0x1000>;
645 interrupts = <0 189 IRQ_TYPE_LEVEL_HIGH>;
646 clocks = <&mstp8_clks R8A7794_CLK_VIN1>;
647 power-domains = <&cpg_clocks>;
648 status = "disabled";
649 };
650
a6a130b3
SS		 651 pci0: pci@ee090000 {
652 compatible = "renesas,pci-r8a7794";
653 device_type = "pci";
654 reg = <0 0xee090000 0 0xc00>,
655 <0 0xee080000 0 0x1100>;
656 interrupts = <0 108 IRQ_TYPE_LEVEL_HIGH>;
657 clocks = <&mstp7_clks R8A7794_CLK_EHCI>;
658 power-domains = <&cpg_clocks>;
659 status = "disabled";
660
661 bus-range = <0 0>;
662 #address-cells = <3>;
663 #size-cells = <2>;
664 #interrupt-cells = <1>;
665 ranges = <0x02000000 0 0xee080000 0 0xee080000 0 0x00010000>;
666 interrupt-map-mask = <0xff00 0 0 0x7>;
667 interrupt-map = <0x0000 0 0 1 &gic 0 108 IRQ_TYPE_LEVEL_HIGH
668 0x0800 0 0 1 &gic 0 108 IRQ_TYPE_LEVEL_HIGH
669 0x1000 0 0 2 &gic 0 108 IRQ_TYPE_LEVEL_HIGH>;
45cb0bd7
SS		 670
671 usb@0,1 {
672 reg = <0x800 0 0 0 0>;
673 device_type = "pci";
674 phys = <&usb0 0>;
675 phy-names = "usb";
676 };
677
678 usb@0,2 {
679 reg = <0x1000 0 0 0 0>;
680 device_type = "pci";
681 phys = <&usb0 0>;
682 phy-names = "usb";
683 };
a6a130b3
SS		 684 };
685
686 pci1: pci@ee0d0000 {
687 compatible = "renesas,pci-r8a7794";
688 device_type = "pci";
689 reg = <0 0xee0d0000 0 0xc00>,
690 <0 0xee0c0000 0 0x1100>;
691 interrupts = <0 113 IRQ_TYPE_LEVEL_HIGH>;
692 clocks = <&mstp7_clks R8A7794_CLK_EHCI>;
693 power-domains = <&cpg_clocks>;
694 status = "disabled";
695
696 bus-range = <1 1>;
697 #address-cells = <3>;
698 #size-cells = <2>;
699 #interrupt-cells = <1>;
700 ranges = <0x02000000 0 0xee0c0000 0 0xee0c0000 0 0x00010000>;
701 interrupt-map-mask = <0xff00 0 0 0x7>;
702 interrupt-map = <0x0000 0 0 1 &gic 0 113 IRQ_TYPE_LEVEL_HIGH
703 0x0800 0 0 1 &gic 0 113 IRQ_TYPE_LEVEL_HIGH
704 0x1000 0 0 2 &gic 0 113 IRQ_TYPE_LEVEL_HIGH>;
45cb0bd7
SS		 705
706 usb@0,1 {
707 reg = <0x800 0 0 0 0>;
708 device_type = "pci";
709 phys = <&usb2 0>;
710 phy-names = "usb";
711 };
712
713 usb@0,2 {
714 reg = <0x1000 0 0 0 0>;
715 device_type = "pci";
716 phys = <&usb2 0>;
717 phy-names = "usb";
718 };
a6a130b3
SS		 719 };
720
74ef4572
SS		 721 usbphy: usb-phy@e6590100 {
722 compatible = "renesas,usb-phy-r8a7794";
723 reg = <0 0xe6590100 0 0x100>;
724 #address-cells = <1>;
725 #size-cells = <0>;
726 clocks = <&mstp7_clks R8A7794_CLK_HSUSB>;
727 clock-names = "usbhs";
728 power-domains = <&cpg_clocks>;
729 status = "disabled";
730
731 usb0: usb-channel@0 {
732 reg = <0>;
733 #phy-cells = <1>;
734 };
735 usb2: usb-channel@2 {
736 reg = <2>;
737 #phy-cells = <1>;
738 };
739 };
740
0dce5454
UH		 741 clocks {
742 #address-cells = <2>;
743 #size-cells = <2>;
744 ranges;
745
746 /* External root clock */
747 extal_clk: extal_clk {
748 compatible = "fixed-clock";
749 #clock-cells = <0>;
750 /* This value must be overriden by the board. */
751 clock-frequency = <0>;
752 clock-output-names = "extal";
753 };
754
755 /* Special CPG clocks */
756 cpg_clocks: cpg_clocks@e6150000 {
757 compatible = "renesas,r8a7794-cpg-clocks",
758 "renesas,rcar-gen2-cpg-clocks";
759 reg = <0 0xe6150000 0 0x1000>;
760 clocks = <&extal_clk>;
761 #clock-cells = <1>;
762 clock-output-names = "main", "pll0", "pll1", "pll3",
763 "lb", "qspi", "sdh", "sd0", "z";
60c0745a 764 #power-domain-cells = <0>;
0dce5454 765 };
8e181633 766 /* Variable factor clocks */
5e7e1554 767 sd2_clk: sd2_clk@e6150078 {
8e181633
SU		 768 compatible = "renesas,r8a7794-div6-clock", "renesas,cpg-div6-clock";
769 reg = <0 0xe6150078 0 4>;
770 clocks = <&pll1_div2_clk>;
771 #clock-cells = <0>;
5e7e1554 772 clock-output-names = "sd2";
8e181633 773 };
5e7e1554 774 sd3_clk: sd3_clk@e615026c {
8e181633 775 compatible = "renesas,r8a7794-div6-clock", "renesas,cpg-div6-clock";
5e7e1554 776 reg = <0 0xe615026c 0 4>;
8e181633
SU		 777 clocks = <&pll1_div2_clk>;
778 #clock-cells = <0>;
5e7e1554 779 clock-output-names = "sd3";
8e181633 780 };
deac150c
SU		 781 mmc0_clk: mmc0_clk@e6150240 {
782 compatible = "renesas,r8a7794-div6-clock", "renesas,cpg-div6-clock";
783 reg = <0 0xe6150240 0 4>;
784 clocks = <&pll1_div2_clk>;
785 #clock-cells = <0>;
786 clock-output-names = "mmc0";
787 };
0dce5454
UH		 788
789 /* Fixed factor clocks */
790 pll1_div2_clk: pll1_div2_clk {
791 compatible = "fixed-factor-clock";
792 clocks = <&cpg_clocks R8A7794_CLK_PLL1>;
793 #clock-cells = <0>;
794 clock-div = <2>;
795 clock-mult = <1>;
796 clock-output-names = "pll1_div2";
797 };
798 zg_clk: zg_clk {
799 compatible = "fixed-factor-clock";
800 clocks = <&cpg_clocks R8A7794_CLK_PLL1>;
801 #clock-cells = <0>;
802 clock-div = <6>;
803 clock-mult = <1>;
804 clock-output-names = "zg";
805 };
806 zx_clk: zx_clk {
807 compatible = "fixed-factor-clock";
808 clocks = <&cpg_clocks R8A7794_CLK_PLL1>;
809 #clock-cells = <0>;
810 clock-div = <3>;
811 clock-mult = <1>;
812 clock-output-names = "zx";
813 };
814 zs_clk: zs_clk {
815 compatible = "fixed-factor-clock";
816 clocks = <&cpg_clocks R8A7794_CLK_PLL1>;
817 #clock-cells = <0>;
818 clock-div = <6>;
819 clock-mult = <1>;
820 clock-output-names = "zs";
821 };
822 hp_clk: hp_clk {
823 compatible = "fixed-factor-clock";
824 clocks = <&cpg_clocks R8A7794_CLK_PLL1>;
825 #clock-cells = <0>;
826 clock-div = <12>;
827 clock-mult = <1>;
828 clock-output-names = "hp";
829 };
830 i_clk: i_clk {
831 compatible = "fixed-factor-clock";
832 clocks = <&cpg_clocks R8A7794_CLK_PLL1>;
833 #clock-cells = <0>;
834 clock-div = <2>;
835 clock-mult = <1>;
836 clock-output-names = "i";
837 };
838 b_clk: b_clk {
839 compatible = "fixed-factor-clock";
840 clocks = <&cpg_clocks R8A7794_CLK_PLL1>;
841 #clock-cells = <0>;
842 clock-div = <12>;
843 clock-mult = <1>;
844 clock-output-names = "b";
845 };
846 p_clk: p_clk {
847 compatible = "fixed-factor-clock";
848 clocks = <&cpg_clocks R8A7794_CLK_PLL1>;
849 #clock-cells = <0>;
850 clock-div = <24>;
851 clock-mult = <1>;
852 clock-output-names = "p";
853 };
854 cl_clk: cl_clk {
855 compatible = "fixed-factor-clock";
856 clocks = <&cpg_clocks R8A7794_CLK_PLL1>;
857 #clock-cells = <0>;
858 clock-div = <48>;
859 clock-mult = <1>;
860 clock-output-names = "cl";
861 };
862 m2_clk: m2_clk {
863 compatible = "fixed-factor-clock";
864 clocks = <&cpg_clocks R8A7794_CLK_PLL1>;
865 #clock-cells = <0>;
866 clock-div = <8>;
867 clock-mult = <1>;
868 clock-output-names = "m2";
869 };
870 imp_clk: imp_clk {
871 compatible = "fixed-factor-clock";
872 clocks = <&cpg_clocks R8A7794_CLK_PLL1>;
873 #clock-cells = <0>;
874 clock-div = <4>;
875 clock-mult = <1>;
876 clock-output-names = "imp";
877 };
878 rclk_clk: rclk_clk {
879 compatible = "fixed-factor-clock";
880 clocks = <&cpg_clocks R8A7794_CLK_PLL1>;
881 #clock-cells = <0>;
882 clock-div = <(48 * 1024)>;
883 clock-mult = <1>;
884 clock-output-names = "rclk";
885 };
886 oscclk_clk: oscclk_clk {
887 compatible = "fixed-factor-clock";
888 clocks = <&cpg_clocks R8A7794_CLK_PLL1>;
889 #clock-cells = <0>;
890 clock-div = <(12 * 1024)>;
891 clock-mult = <1>;
892 clock-output-names = "oscclk";
893 };
894 zb3_clk: zb3_clk {
895 compatible = "fixed-factor-clock";
896 clocks = <&cpg_clocks R8A7794_CLK_PLL3>;
897 #clock-cells = <0>;
898 clock-div = <4>;
899 clock-mult = <1>;
900 clock-output-names = "zb3";
901 };
902 zb3d2_clk: zb3d2_clk {
903 compatible = "fixed-factor-clock";
904 clocks = <&cpg_clocks R8A7794_CLK_PLL3>;
905 #clock-cells = <0>;
906 clock-div = <8>;
907 clock-mult = <1>;
908 clock-output-names = "zb3d2";
909 };
910 ddr_clk: ddr_clk {
911 compatible = "fixed-factor-clock";
912 clocks = <&cpg_clocks R8A7794_CLK_PLL3>;
913 #clock-cells = <0>;
914 clock-div = <8>;
915 clock-mult = <1>;
916 clock-output-names = "ddr";
917 };
918 mp_clk: mp_clk {
919 compatible = "fixed-factor-clock";
920 clocks = <&pll1_div2_clk>;
921 #clock-cells = <0>;
922 clock-div = <15>;
923 clock-mult = <1>;
924 clock-output-names = "mp";
925 };
926 cp_clk: cp_clk {
927 compatible = "fixed-factor-clock";
928 clocks = <&cpg_clocks R8A7794_CLK_PLL1>;
929 #clock-cells = <0>;
930 clock-div = <48>;
931 clock-mult = <1>;
932 clock-output-names = "cp";
933 };
934
935 acp_clk: acp_clk {
936 compatible = "fixed-factor-clock";
937 clocks = <&extal_clk>;
938 #clock-cells = <0>;
939 clock-div = <2>;
940 clock-mult = <1>;
941 clock-output-names = "acp";
942 };
943
944 /* Gate clocks */
945 mstp0_clks: mstp0_clks@e6150130 {
946 compatible = "renesas,r8a7794-mstp-clocks", "renesas,cpg-mstp-clocks";
947 reg = <0 0xe6150130 0 4>, <0 0xe6150030 0 4>;
948 clocks = <&mp_clk>;
949 #clock-cells = <1>;
1045d065 950 clock-indices = <R8A7794_CLK_MSIOF0>;
0dce5454
UH		 951 clock-output-names = "msiof0";
952 };
953 mstp1_clks: mstp1_clks@e6150134 {
954 compatible = "renesas,r8a7794-mstp-clocks", "renesas,cpg-mstp-clocks";
955 reg = <0 0xe6150134 0 4>, <0 0xe6150038 0 4>;
dc3cf93d
YH		 956 clocks = <&zs_clk>, <&zs_clk>, <&p_clk>, <&zg_clk>, <&zs_clk>,
957 <&zs_clk>, <&p_clk>, <&p_clk>, <&rclk_clk>, <&cp_clk>,
958 <&zs_clk>, <&zs_clk>;
0dce5454 959 #clock-cells = <1>;
1045d065 960 clock-indices = <
dc3cf93d
YH		 961 R8A7794_CLK_VCP0 R8A7794_CLK_VPC0 R8A7794_CLK_TMU1
962 R8A7794_CLK_3DG R8A7794_CLK_2DDMAC R8A7794_CLK_FDP1_0
963 R8A7794_CLK_TMU3 R8A7794_CLK_TMU2 R8A7794_CLK_CMT0
964 R8A7794_CLK_TMU0 R8A7794_CLK_VSP1_DU0 R8A7794_CLK_VSP1_S
0dce5454
UH		 965 >;
966 clock-output-names =
dc3cf93d
YH		 967 "vcp0", "vpc0", "tmu1", "3dg", "2ddmac", "fdp1-0",
968 "tmu3", "tmu2", "cmt0", "tmu0", "vsp1-du0", "vsps";
0dce5454
UH		 969 };
970 mstp2_clks: mstp2_clks@e6150138 {
971 compatible = "renesas,r8a7794-mstp-clocks", "renesas,cpg-mstp-clocks";
972 reg = <0 0xe6150138 0 4>, <0 0xe6150040 0 4>;
973 clocks = <&mp_clk>, <&mp_clk>, <&mp_clk>, <&mp_clk>, <&mp_clk>,
be16cd38
HY		 974 <&mp_clk>, <&mp_clk>, <&mp_clk>,
975 <&zs_clk>, <&zs_clk>;
0dce5454 976 #clock-cells = <1>;
1045d065 977 clock-indices = <
0dce5454
UH		 978 R8A7794_CLK_SCIFA2 R8A7794_CLK_SCIFA1 R8A7794_CLK_SCIFA0
979 R8A7794_CLK_MSIOF2 R8A7794_CLK_SCIFB0 R8A7794_CLK_SCIFB1
980 R8A7794_CLK_MSIOF1 R8A7794_CLK_SCIFB2
be16cd38 981 R8A7794_CLK_SYS_DMAC1 R8A7794_CLK_SYS_DMAC0
0dce5454
UH		 982 >;
983 clock-output-names =
984 "scifa2", "scifa1", "scifa0", "msiof2", "scifb0",
be16cd38
HY		 985 "scifb1", "msiof1", "scifb2",
986 "sys-dmac1", "sys-dmac0";
0dce5454
UH		 987 };
988 mstp3_clks: mstp3_clks@e615013c {
989 compatible = "renesas,r8a7794-mstp-clocks", "renesas,cpg-mstp-clocks";
990 reg = <0 0xe615013c 0 4>, <0 0xe6150048 0 4>;
5e7e1554 991 clocks = <&sd3_clk>, <&sd2_clk>, <&cpg_clocks R8A7794_CLK_SD0>,
deac150c 992 <&mmc0_clk>, <&rclk_clk>, <&hp_clk>, <&hp_clk>;
0dce5454 993 #clock-cells = <1>;
1045d065 994 clock-indices = <
8e181633 995 R8A7794_CLK_SDHI2 R8A7794_CLK_SDHI1 R8A7794_CLK_SDHI0
deac150c
SU		 996 R8A7794_CLK_MMCIF0 R8A7794_CLK_CMT1
997 R8A7794_CLK_USBDMAC0 R8A7794_CLK_USBDMAC1
0dce5454
UH		 998 >;
999 clock-output-names =
8e181633 1000 "sdhi2", "sdhi1", "sdhi0",
deac150c 1001 "mmcif0", "cmt1", "usbdmac0", "usbdmac1";
0dce5454 1002 };
1c5ca5db
GU		 1003 mstp4_clks: mstp4_clks@e6150140 {
1004 compatible = "renesas,r8a7794-mstp-clocks", "renesas,cpg-mstp-clocks";
1005 reg = <0 0xe6150140 0 4>, <0 0xe615004c 0 4>;
1006 clocks = <&cp_clk>;
1007 #clock-cells = <1>;
1008 clock-indices = <R8A7794_CLK_IRQC>;
1009 clock-output-names = "irqc";
1010 };
0dce5454
UH		 1011 mstp7_clks: mstp7_clks@e615014c {
1012 compatible = "renesas,r8a7794-mstp-clocks", "renesas,cpg-mstp-clocks";
1013 reg = <0 0xe615014c 0 4>, <0 0xe61501c4 0 4>;
c7bab9f9
SU		 1014 clocks = <&mp_clk>, <&mp_clk>,
1015 <&zs_clk>, <&p_clk>, <&p_clk>, <&zs_clk>,
0dce5454
UH		 1016 <&zs_clk>, <&p_clk>, <&p_clk>, <&p_clk>, <&p_clk>;
1017 #clock-cells = <1>;
1045d065 1018 clock-indices = <
c7bab9f9 1019 R8A7794_CLK_EHCI R8A7794_CLK_HSUSB
0dce5454
UH		 1020 R8A7794_CLK_HSCIF2 R8A7794_CLK_SCIF5
1021 R8A7794_CLK_SCIF4 R8A7794_CLK_HSCIF1 R8A7794_CLK_HSCIF0
1022 R8A7794_CLK_SCIF3 R8A7794_CLK_SCIF2 R8A7794_CLK_SCIF1
1023 R8A7794_CLK_SCIF0
1024 >;
1025 clock-output-names =
c7bab9f9 1026 "ehci", "hsusb",
0dce5454
UH		 1027 "hscif2", "scif5", "scif4", "hscif1", "hscif0",
1028 "scif3", "scif2", "scif1", "scif0";
1029 };
1030 mstp8_clks: mstp8_clks@e6150990 {
1031 compatible = "renesas,r8a7794-mstp-clocks", "renesas,cpg-mstp-clocks";
1032 reg = <0 0xe6150990 0 4>, <0 0xe61509a0 0 4>;
148ebf47 1033 clocks = <&zg_clk>, <&zg_clk>, <&p_clk>;
0dce5454 1034 #clock-cells = <1>;
1045d065 1035 clock-indices = <
148ebf47 1036 R8A7794_CLK_VIN1 R8A7794_CLK_VIN0 R8A7794_CLK_ETHER
0dce5454
UH		 1037 >;
1038 clock-output-names =
148ebf47 1039 "vin1", "vin0", "ether";
0dce5454 1040 };
3281480b
HN		 1041 mstp9_clks: mstp9_clks@e6150994 {
1042 compatible = "renesas,r8a7794-mstp-clocks", "renesas,cpg-mstp-clocks";
1043 reg = <0 0xe6150994 0 4>, <0 0xe61509a4 0 4>;
3f37e018
SS		 1044 clocks = <&cp_clk>, <&cp_clk>, <&cp_clk>, <&cp_clk>,
1045 <&cp_clk>, <&cp_clk>, <&cp_clk>,
1046 <&cpg_clocks R8A7794_CLK_QSPI>, <&hp_clk>, <&hp_clk>,
1047 <&hp_clk>, <&hp_clk>, <&hp_clk>, <&hp_clk>;
3281480b 1048 #clock-cells = <1>;
3f37e018
SS		 1049 clock-indices = <R8A7794_CLK_GPIO6 R8A7794_CLK_GPIO5
1050 R8A7794_CLK_GPIO4 R8A7794_CLK_GPIO3
1051 R8A7794_CLK_GPIO2 R8A7794_CLK_GPIO1
1052 R8A7794_CLK_GPIO0 R8A7794_CLK_QSPI_MOD
1053 R8A7794_CLK_I2C5 R8A7794_CLK_I2C4
1054 R8A7794_CLK_I2C3 R8A7794_CLK_I2C2
1055 R8A7794_CLK_I2C1 R8A7794_CLK_I2C0>;
c5d82c99 1056 clock-output-names =
3f37e018
SS		 1057 "gpio6", "gpio5", "gpio4", "gpio3", "gpio2",
1058 "gpio1", "gpio0", "qspi_mod",
1059 "i2c5", "i2c4", "i2c3", "i2c2", "i2c1", "i2c0";
3281480b 1060 };
0dce5454
UH		 1061 mstp11_clks: mstp11_clks@e615099c {
1062 compatible = "renesas,r8a7794-mstp-clocks", "renesas,cpg-mstp-clocks";
1063 reg = <0 0xe615099c 0 4>, <0 0xe61509ac 0 4>;
1064 clocks = <&mp_clk>, <&mp_clk>, <&mp_clk>;
1065 #clock-cells = <1>;
1045d065 1066 clock-indices = <
0dce5454
UH		 1067 R8A7794_CLK_SCIFA3 R8A7794_CLK_SCIFA4 R8A7794_CLK_SCIFA5
1068 >;
1069 clock-output-names = "scifa3", "scifa4", "scifa5";
1070 };
1071 };
1cb2794f
LP		 1072
1073 ipmmu_sy0: mmu@e6280000 {
1074 compatible = "renesas,ipmmu-vmsa";
1075 reg = <0 0xe6280000 0 0x1000>;
1076 interrupts = <0 223 IRQ_TYPE_LEVEL_HIGH>,
1077 <0 224 IRQ_TYPE_LEVEL_HIGH>;
1078 #iommu-cells = <1>;
1079 status = "disabled";
1080 };
1081
1082 ipmmu_sy1: mmu@e6290000 {
1083 compatible = "renesas,ipmmu-vmsa";
1084 reg = <0 0xe6290000 0 0x1000>;
1085 interrupts = <0 225 IRQ_TYPE_LEVEL_HIGH>;
1086 #iommu-cells = <1>;
1087 status = "disabled";
1088 };
1089
1090 ipmmu_ds: mmu@e6740000 {
1091 compatible = "renesas,ipmmu-vmsa";
1092 reg = <0 0xe6740000 0 0x1000>;
1093 interrupts = <0 198 IRQ_TYPE_LEVEL_HIGH>,
1094 <0 199 IRQ_TYPE_LEVEL_HIGH>;
1095 #iommu-cells = <1>;
1096 };
1097
1098 ipmmu_mp: mmu@ec680000 {
1099 compatible = "renesas,ipmmu-vmsa";
1100 reg = <0 0xec680000 0 0x1000>;
1101 interrupts = <0 226 IRQ_TYPE_LEVEL_HIGH>;
1102 #iommu-cells = <1>;
1103 status = "disabled";
1104 };
1105
1106 ipmmu_mx: mmu@fe951000 {
1107 compatible = "renesas,ipmmu-vmsa";
1108 reg = <0 0xfe951000 0 0x1000>;
1109 interrupts = <0 222 IRQ_TYPE_LEVEL_HIGH>,
1110 <0 221 IRQ_TYPE_LEVEL_HIGH>;
1111 #iommu-cells = <1>;
1112 };
1113
1114 ipmmu_gp: mmu@e62a0000 {
1115 compatible = "renesas,ipmmu-vmsa";
1116 reg = <0 0xe62a0000 0 0x1000>;
1117 interrupts = <0 260 IRQ_TYPE_LEVEL_HIGH>,
1118 <0 261 IRQ_TYPE_LEVEL_HIGH>;
1119 #iommu-cells = <1>;
1120 status = "disabled";
1121 };
0dce5454 1122};
Linux 6.x block layer and io_uring tree(s)