Commit | Line | Data |
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a742795b UH |
1 | /* |
2 | * Device Tree Source for the Alt board | |
3 | * | |
4 | * Copyright (C) 2014 Renesas Electronics Corporation | |
5 | * | |
6 | * This file is licensed under the terms of the GNU General Public License | |
7 | * version 2. This program is licensed "as is" without any warranty of any | |
8 | * kind, whether express or implied. | |
9 | */ | |
10 | ||
11 | /dts-v1/; | |
12 | #include "r8a7794.dtsi" | |
2b41091b | 13 | #include <dt-bindings/gpio/gpio.h> |
a742795b UH |
14 | |
15 | / { | |
16 | model = "Alt"; | |
17 | compatible = "renesas,alt", "renesas,r8a7794"; | |
18 | ||
19 | aliases { | |
20 | serial0 = &scif2; | |
21 | }; | |
22 | ||
23 | chosen { | |
89aeff99 | 24 | bootargs = "ignore_loglevel rw root=/dev/nfs ip=dhcp"; |
b575f994 | 25 | stdout-path = "serial0:115200n8"; |
a742795b UH |
26 | }; |
27 | ||
28 | memory@40000000 { | |
29 | device_type = "memory"; | |
30 | reg = <0 0x40000000 0 0x40000000>; | |
31 | }; | |
32 | ||
e6ed3f53 SH |
33 | d3_3v: regulator-d3-3v { |
34 | compatible = "regulator-fixed"; | |
35 | regulator-name = "D3.3V"; | |
36 | regulator-min-microvolt = <3300000>; | |
37 | regulator-max-microvolt = <3300000>; | |
38 | regulator-boot-on; | |
39 | regulator-always-on; | |
40 | }; | |
41 | ||
2b41091b SH |
42 | vcc_sdhi0: regulator-vcc-sdhi0 { |
43 | compatible = "regulator-fixed"; | |
44 | ||
45 | regulator-name = "SDHI0 Vcc"; | |
46 | regulator-min-microvolt = <3300000>; | |
47 | regulator-max-microvolt = <3300000>; | |
48 | ||
49 | gpio = <&gpio2 26 GPIO_ACTIVE_HIGH>; | |
50 | enable-active-high; | |
51 | }; | |
52 | ||
53 | vccq_sdhi0: regulator-vccq-sdhi0 { | |
54 | compatible = "regulator-gpio"; | |
55 | ||
56 | regulator-name = "SDHI0 VccQ"; | |
57 | regulator-min-microvolt = <1800000>; | |
58 | regulator-max-microvolt = <3300000>; | |
59 | ||
60 | gpios = <&gpio2 29 GPIO_ACTIVE_HIGH>; | |
61 | gpios-states = <1>; | |
62 | states = <3300000 1 | |
63 | 1800000 0>; | |
64 | }; | |
65 | ||
66 | vcc_sdhi1: regulator-vcc-sdhi1 { | |
67 | compatible = "regulator-fixed"; | |
68 | ||
69 | regulator-name = "SDHI1 Vcc"; | |
70 | regulator-min-microvolt = <3300000>; | |
71 | regulator-max-microvolt = <3300000>; | |
72 | ||
73 | gpio = <&gpio4 26 GPIO_ACTIVE_HIGH>; | |
74 | enable-active-high; | |
75 | }; | |
76 | ||
77 | vccq_sdhi1: regulator-vccq-sdhi1 { | |
78 | compatible = "regulator-gpio"; | |
79 | ||
80 | regulator-name = "SDHI1 VccQ"; | |
81 | regulator-min-microvolt = <1800000>; | |
82 | regulator-max-microvolt = <3300000>; | |
83 | ||
84 | gpios = <&gpio4 29 GPIO_ACTIVE_HIGH>; | |
85 | gpios-states = <1>; | |
86 | states = <3300000 1 | |
87 | 1800000 0>; | |
88 | }; | |
89 | ||
a742795b UH |
90 | lbsc { |
91 | #address-cells = <1>; | |
92 | #size-cells = <1>; | |
93 | }; | |
876e7fb9 MD |
94 | |
95 | vga-encoder { | |
96 | compatible = "adi,adv7123"; | |
97 | ||
98 | ports { | |
99 | #address-cells = <1>; | |
100 | #size-cells = <0>; | |
101 | ||
102 | port@0 { | |
103 | reg = <0>; | |
104 | adv7123_in: endpoint { | |
105 | remote-endpoint = <&du_out_rgb1>; | |
106 | }; | |
107 | }; | |
108 | port@1 { | |
109 | reg = <1>; | |
110 | adv7123_out: endpoint { | |
111 | remote-endpoint = <&vga_in>; | |
112 | }; | |
113 | }; | |
114 | }; | |
115 | }; | |
116 | ||
117 | vga { | |
118 | compatible = "vga-connector"; | |
119 | ||
120 | port { | |
121 | vga_in: endpoint { | |
122 | remote-endpoint = <&adv7123_out>; | |
123 | }; | |
124 | }; | |
125 | }; | |
126 | ||
127 | x2_clk: x2-clock { | |
128 | compatible = "fixed-clock"; | |
129 | #clock-cells = <0>; | |
130 | clock-frequency = <74250000>; | |
131 | }; | |
132 | ||
133 | x13_clk: x13-clock { | |
134 | compatible = "fixed-clock"; | |
135 | #clock-cells = <0>; | |
136 | clock-frequency = <148500000>; | |
137 | }; | |
138 | }; | |
139 | ||
140 | &du { | |
13b8b8e8 MD |
141 | pinctrl-0 = <&du_pins>; |
142 | pinctrl-names = "default"; | |
876e7fb9 MD |
143 | status = "okay"; |
144 | ||
145 | clocks = <&mstp7_clks R8A7794_CLK_DU0>, | |
146 | <&mstp7_clks R8A7794_CLK_DU0>, | |
147 | <&x13_clk>, <&x2_clk>; | |
148 | clock-names = "du.0", "du.1", "dclkin.0", "dclkin.1"; | |
149 | ||
150 | ports { | |
151 | port@1 { | |
152 | endpoint { | |
153 | remote-endpoint = <&adv7123_in>; | |
154 | }; | |
155 | }; | |
156 | }; | |
a742795b UH |
157 | }; |
158 | ||
159 | &extal_clk { | |
160 | clock-frequency = <20000000>; | |
161 | }; | |
162 | ||
22b16071 | 163 | &pfc { |
8a758a94 GU |
164 | pinctrl-0 = <&scif_clk_pins>; |
165 | pinctrl-names = "default"; | |
166 | ||
13b8b8e8 | 167 | du_pins: du { |
be7359dd SH |
168 | groups = "du1_rgb666", "du1_sync", "du1_disp", "du1_dotclkout0"; |
169 | function = "du"; | |
13b8b8e8 MD |
170 | }; |
171 | ||
d88f5bc4 | 172 | scif2_pins: scif2 { |
be7359dd SH |
173 | groups = "scif2_data"; |
174 | function = "scif2"; | |
22b16071 SH |
175 | }; |
176 | ||
8a758a94 | 177 | scif_clk_pins: scif_clk { |
be7359dd SH |
178 | groups = "scif_clk"; |
179 | function = "scif_clk"; | |
8a758a94 GU |
180 | }; |
181 | ||
22b16071 | 182 | ether_pins: ether { |
be7359dd SH |
183 | groups = "eth_link", "eth_mdio", "eth_rmii"; |
184 | function = "eth"; | |
22b16071 SH |
185 | }; |
186 | ||
c175e7ab | 187 | phy1_pins: phy1 { |
be7359dd SH |
188 | groups = "intc_irq8"; |
189 | function = "intc"; | |
22b16071 | 190 | }; |
7f81bf72 UH |
191 | |
192 | i2c1_pins: i2c1 { | |
be7359dd SH |
193 | groups = "i2c1"; |
194 | function = "i2c1"; | |
7f81bf72 | 195 | }; |
d537543b UH |
196 | |
197 | vin0_pins: vin0 { | |
be7359dd SH |
198 | groups = "vin0_data8", "vin0_clk"; |
199 | function = "vin0"; | |
d537543b | 200 | }; |
2b41091b | 201 | |
e6ed3f53 SH |
202 | mmcif0_pins: mmcif0 { |
203 | groups = "mmc_data8", "mmc_ctrl"; | |
204 | function = "mmc"; | |
205 | }; | |
206 | ||
2b41091b SH |
207 | sdhi0_pins: sd0 { |
208 | groups = "sdhi0_data4", "sdhi0_ctrl"; | |
209 | function = "sdhi0"; | |
9510f349 SH |
210 | power-source = <3300>; |
211 | }; | |
212 | ||
213 | sdhi0_pins_uhs: sd0_uhs { | |
214 | groups = "sdhi0_data4", "sdhi0_ctrl"; | |
215 | function = "sdhi0"; | |
216 | power-source = <1800>; | |
2b41091b SH |
217 | }; |
218 | ||
219 | sdhi1_pins: sd1 { | |
220 | groups = "sdhi1_data4", "sdhi1_ctrl"; | |
221 | function = "sdhi1"; | |
9510f349 SH |
222 | power-source = <3300>; |
223 | }; | |
224 | ||
225 | sdhi1_pins_uhs: sd1_uhs { | |
226 | groups = "sdhi1_data4", "sdhi1_ctrl"; | |
227 | function = "sdhi1"; | |
228 | power-source = <1800>; | |
2b41091b | 229 | }; |
22b16071 SH |
230 | }; |
231 | ||
a742795b | 232 | &cmt0 { |
38e02908 | 233 | status = "okay"; |
a742795b UH |
234 | }; |
235 | ||
6b78e6ae | 236 | &pfc { |
fc10f3c9 | 237 | qspi_pins: qspi { |
be7359dd SH |
238 | groups = "qspi_ctrl", "qspi_data4"; |
239 | function = "qspi"; | |
6b78e6ae SH |
240 | }; |
241 | }; | |
242 | ||
a895b7cd | 243 | ðer { |
c175e7ab SH |
244 | pinctrl-0 = <ðer_pins &phy1_pins>; |
245 | pinctrl-names = "default"; | |
246 | ||
a895b7cd LP |
247 | phy-handle = <&phy1>; |
248 | renesas,ether-link-active-low; | |
249 | status = "okay"; | |
250 | ||
251 | phy1: ethernet-phy@1 { | |
252 | reg = <1>; | |
253 | interrupt-parent = <&irqc0>; | |
1fc58015 | 254 | interrupts = <8 IRQ_TYPE_LEVEL_LOW>; |
a895b7cd LP |
255 | micrel,led-mode = <1>; |
256 | }; | |
257 | }; | |
258 | ||
e6ed3f53 SH |
259 | &mmcif0 { |
260 | pinctrl-0 = <&mmcif0_pins>; | |
261 | pinctrl-names = "default"; | |
262 | ||
263 | vmmc-supply = <&d3_3v>; | |
264 | vqmmc-supply = <&d3_3v>; | |
265 | bus-width = <8>; | |
266 | non-removable; | |
267 | status = "okay"; | |
268 | }; | |
269 | ||
2b41091b SH |
270 | &sdhi0 { |
271 | pinctrl-0 = <&sdhi0_pins>; | |
9510f349 SH |
272 | pinctrl-1 = <&sdhi0_pins_uhs>; |
273 | pinctrl-names = "default", "state_uhs"; | |
2b41091b SH |
274 | |
275 | vmmc-supply = <&vcc_sdhi0>; | |
276 | vqmmc-supply = <&vccq_sdhi0>; | |
277 | cd-gpios = <&gpio6 6 GPIO_ACTIVE_LOW>; | |
278 | wp-gpios = <&gpio6 7 GPIO_ACTIVE_LOW>; | |
9510f349 | 279 | sd-uhs-sdr50; |
2b41091b SH |
280 | status = "okay"; |
281 | }; | |
282 | ||
283 | &sdhi1 { | |
284 | pinctrl-0 = <&sdhi1_pins>; | |
9510f349 SH |
285 | pinctrl-1 = <&sdhi1_pins_uhs>; |
286 | pinctrl-names = "default", "state_uhs"; | |
2b41091b SH |
287 | |
288 | vmmc-supply = <&vcc_sdhi1>; | |
289 | vqmmc-supply = <&vccq_sdhi1>; | |
290 | cd-gpios = <&gpio6 14 GPIO_ACTIVE_LOW>; | |
291 | wp-gpios = <&gpio6 15 GPIO_ACTIVE_LOW>; | |
9510f349 | 292 | sd-uhs-sdr50; |
2b41091b SH |
293 | status = "okay"; |
294 | }; | |
295 | ||
7f81bf72 UH |
296 | &i2c1 { |
297 | pinctrl-0 = <&i2c1_pins>; | |
298 | pinctrl-names = "default"; | |
299 | ||
300 | status = "okay"; | |
301 | clock-frequency = <400000>; | |
d537543b UH |
302 | |
303 | composite-in@20 { | |
304 | compatible = "adi,adv7180"; | |
305 | reg = <0x20>; | |
306 | remote = <&vin0>; | |
307 | ||
308 | port { | |
309 | adv7180: endpoint { | |
310 | bus-width = <8>; | |
311 | remote-endpoint = <&vin0ep>; | |
312 | }; | |
313 | }; | |
314 | }; | |
315 | }; | |
316 | ||
317 | &vin0 { | |
318 | status = "okay"; | |
319 | pinctrl-0 = <&vin0_pins>; | |
320 | pinctrl-names = "default"; | |
321 | ||
322 | port { | |
323 | #address-cells = <1>; | |
324 | #size-cells = <0>; | |
325 | ||
326 | vin0ep: endpoint { | |
327 | remote-endpoint = <&adv7180>; | |
328 | bus-width = <8>; | |
329 | }; | |
330 | }; | |
7f81bf72 UH |
331 | }; |
332 | ||
a742795b | 333 | &scif2 { |
7256587c SH |
334 | pinctrl-0 = <&scif2_pins>; |
335 | pinctrl-names = "default"; | |
336 | ||
38e02908 | 337 | status = "okay"; |
a742795b | 338 | }; |
6b78e6ae | 339 | |
8a758a94 GU |
340 | &scif_clk { |
341 | clock-frequency = <14745600>; | |
342 | status = "okay"; | |
343 | }; | |
344 | ||
6b78e6ae SH |
345 | &qspi { |
346 | pinctrl-0 = <&qspi_pins>; | |
347 | pinctrl-names = "default"; | |
348 | ||
349 | status = "okay"; | |
350 | ||
351 | flash@0 { | |
352 | compatible = "spansion,s25fl512s", "jedec,spi-nor"; | |
353 | reg = <0>; | |
354 | spi-max-frequency = <30000000>; | |
355 | spi-tx-bus-width = <4>; | |
356 | spi-rx-bus-width = <4>; | |
357 | spi-cpol; | |
358 | spi-cpha; | |
359 | m25p,fast-read; | |
360 | ||
361 | partitions { | |
362 | compatible = "fixed-partitions"; | |
363 | #address-cells = <1>; | |
364 | #size-cells = <1>; | |
365 | ||
366 | partition@0 { | |
367 | label = "loader"; | |
368 | reg = <0x00000000 0x00040000>; | |
369 | read-only; | |
370 | }; | |
371 | partition@40000 { | |
372 | label = "system"; | |
373 | reg = <0x00040000 0x00040000>; | |
374 | read-only; | |
375 | }; | |
376 | partition@80000 { | |
377 | label = "user"; | |
378 | reg = <0x00080000 0x03f80000>; | |
379 | }; | |
380 | }; | |
381 | }; | |
382 | }; |