[linux-2.6-block.git] / arch / arm / boot / dts / r8a7794-alt.dts

/*
 * Device Tree Source for the Alt board
 *
 * Copyright (C) 2014 Renesas Electronics Corporation
 *
 * This file is licensed under the terms of the GNU General Public License
 * version 2.  This program is licensed "as is" without any warranty of any
 * kind, whether express or implied.
 */

/dts-v1/;
#include "r8a7794.dtsi"
#include <dt-bindings/gpio/gpio.h>

/ {
	model = "Alt";
	compatible = "renesas,alt", "renesas,r8a7794";

	aliases {
		serial0 = &scif2;
		i2c10 = &gpioi2c4;
		i2c12 = &i2cexio4;
	};

	chosen {
		bootargs = "ignore_loglevel rw root=/dev/nfs ip=dhcp";
		stdout-path = "serial0:115200n8";
	};

	memory@40000000 {
		device_type = "memory";
		reg = <0 0x40000000 0 0x40000000>;
	};

	d3_3v: regulator-d3-3v {
		compatible = "regulator-fixed";
		regulator-name = "D3.3V";
		regulator-min-microvolt = <3300000>;
		regulator-max-microvolt = <3300000>;
		regulator-boot-on;
		regulator-always-on;
	};

	vcc_sdhi0: regulator-vcc-sdhi0 {
		compatible = "regulator-fixed";

		regulator-name = "SDHI0 Vcc";
		regulator-min-microvolt = <3300000>;
		regulator-max-microvolt = <3300000>;

		gpio = <&gpio2 26 GPIO_ACTIVE_HIGH>;
		enable-active-high;
	};

	vccq_sdhi0: regulator-vccq-sdhi0 {
		compatible = "regulator-gpio";

		regulator-name = "SDHI0 VccQ";
		regulator-min-microvolt = <1800000>;
		regulator-max-microvolt = <3300000>;

		gpios = <&gpio2 29 GPIO_ACTIVE_HIGH>;
		gpios-states = <1>;
		states = <3300000 1
			  1800000 0>;
	};

	vcc_sdhi1: regulator-vcc-sdhi1 {
		compatible = "regulator-fixed";

		regulator-name = "SDHI1 Vcc";
		regulator-min-microvolt = <3300000>;
		regulator-max-microvolt = <3300000>;

		gpio = <&gpio4 26 GPIO_ACTIVE_HIGH>;
		enable-active-high;
	};

	vccq_sdhi1: regulator-vccq-sdhi1 {
		compatible = "regulator-gpio";

		regulator-name = "SDHI1 VccQ";
		regulator-min-microvolt = <1800000>;
		regulator-max-microvolt = <3300000>;

		gpios = <&gpio4 29 GPIO_ACTIVE_HIGH>;
		gpios-states = <1>;
		states = <3300000 1
			  1800000 0>;
	};

	lbsc {
		#address-cells = <1>;
		#size-cells = <1>;
	};

	vga-encoder {
		compatible = "adi,adv7123";

		ports {
			#address-cells = <1>;
			#size-cells = <0>;

			port@0 {
				reg = <0>;
				adv7123_in: endpoint {
					remote-endpoint = <&du_out_rgb1>;
				};
			};
			port@1 {
				reg = <1>;
				adv7123_out: endpoint {
					remote-endpoint = <&vga_in>;
				};
			};
		};
	};

	vga {
		compatible = "vga-connector";

		port {
			vga_in: endpoint {
				remote-endpoint = <&adv7123_out>;
			};
		};
	};

	x2_clk: x2-clock {
		compatible = "fixed-clock";
		#clock-cells = <0>;
		clock-frequency = <74250000>;
	};

	x13_clk: x13-clock {
		compatible = "fixed-clock";
		#clock-cells = <0>;
		clock-frequency = <148500000>;
	};

	gpioi2c4: i2c-10 {
		#address-cells = <1>;
		#size-cells = <0>;
		compatible = "i2c-gpio";
		status = "disabled";
		gpios = <&gpio4 9 GPIO_ACTIVE_HIGH /* sda */
			 &gpio4 8 GPIO_ACTIVE_HIGH /* scl */
			>;
		i2c-gpio,delay-us = <5>;
	};

	/*
	 * I2C4 is routed to EXIO connector B, pins 73 (SCL) + 74 (SDA).
	 * A fallback to GPIO is provided.
	 */
	i2cexio4: i2c-14 {
		compatible = "i2c-demux-pinctrl";
		i2c-parent = <&i2c4>, <&gpioi2c4>;
		i2c-bus-name = "i2c-exio4";
		#address-cells = <1>;
		#size-cells = <0>;
	};
};

&du {
	pinctrl-0 = <&du_pins>;
	pinctrl-names = "default";
	status = "okay";

	clocks = <&mstp7_clks R8A7794_CLK_DU0>,
		 <&mstp7_clks R8A7794_CLK_DU1>,
		 <&x13_clk>, <&x2_clk>;
	clock-names = "du.0", "du.1", "dclkin.0", "dclkin.1";

	ports {
		port@1 {
			endpoint {
				remote-endpoint = <&adv7123_in>;
			};
		};
	};
};

&extal_clk {
	clock-frequency = <20000000>;
};

&pfc {
	pinctrl-0 = <&scif_clk_pins>;
	pinctrl-names = "default";

	du_pins: du {
		groups = "du1_rgb666", "du1_sync", "du1_disp", "du1_clk0_out";
		function = "du1";
	};

	scif2_pins: scif2 {
		groups = "scif2_data";
		function = "scif2";
	};

	scif_clk_pins: scif_clk {
		groups = "scif_clk";
		function = "scif_clk";
	};

	ether_pins: ether {
		groups = "eth_link", "eth_mdio", "eth_rmii";
		function = "eth";
	};

	phy1_pins: phy1 {
		groups = "intc_irq8";
		function = "intc";
	};

	i2c1_pins: i2c1 {
		groups = "i2c1";
		function = "i2c1";
	};

	i2c4_pins: i2c4 {
		groups = "i2c4";
		function = "i2c4";
	};

	vin0_pins: vin0 {
		groups = "vin0_data8", "vin0_clk";
		function = "vin0";
	};

	mmcif0_pins: mmcif0 {
		groups = "mmc_data8", "mmc_ctrl";
		function = "mmc";
	};

	sdhi0_pins: sd0 {
		groups = "sdhi0_data4", "sdhi0_ctrl";
		function = "sdhi0";
		power-source = <3300>;
	};

	sdhi0_pins_uhs: sd0_uhs {
		groups = "sdhi0_data4", "sdhi0_ctrl";
		function = "sdhi0";
		power-source = <1800>;
	};

	sdhi1_pins: sd1 {
		groups = "sdhi1_data4", "sdhi1_ctrl";
		function = "sdhi1";
		power-source = <3300>;
	};

	sdhi1_pins_uhs: sd1_uhs {
		groups = "sdhi1_data4", "sdhi1_ctrl";
		function = "sdhi1";
		power-source = <1800>;
	};
};

&cmt0 {
	status = "okay";
};

&pfc {
	qspi_pins: qspi {
		groups = "qspi_ctrl", "qspi_data4";
		function = "qspi";
	};
};

&ether {
	pinctrl-0 = <&ether_pins &phy1_pins>;
	pinctrl-names = "default";

	phy-handle = <&phy1>;
	renesas,ether-link-active-low;
	status = "okay";

	phy1: ethernet-phy@1 {
		reg = <1>;
		interrupt-parent = <&irqc0>;
		interrupts = <8 IRQ_TYPE_LEVEL_LOW>;
		micrel,led-mode = <1>;
	};
};

&mmcif0 {
	pinctrl-0 = <&mmcif0_pins>;
	pinctrl-names = "default";

	vmmc-supply = <&d3_3v>;
	vqmmc-supply = <&d3_3v>;
	bus-width = <8>;
	non-removable;
	status = "okay";
};

&sdhi0 {
	pinctrl-0 = <&sdhi0_pins>;
	pinctrl-1 = <&sdhi0_pins_uhs>;
	pinctrl-names = "default", "state_uhs";

	vmmc-supply = <&vcc_sdhi0>;
	vqmmc-supply = <&vccq_sdhi0>;
	cd-gpios = <&gpio6 6 GPIO_ACTIVE_LOW>;
	wp-gpios = <&gpio6 7 GPIO_ACTIVE_LOW>;
	sd-uhs-sdr50;
	sd-uhs-sdr104;
	status = "okay";
};

&sdhi1 {
	pinctrl-0 = <&sdhi1_pins>;
	pinctrl-1 = <&sdhi1_pins_uhs>;
	pinctrl-names = "default", "state_uhs";

	vmmc-supply = <&vcc_sdhi1>;
	vqmmc-supply = <&vccq_sdhi1>;
	cd-gpios = <&gpio6 14 GPIO_ACTIVE_LOW>;
	wp-gpios = <&gpio6 15 GPIO_ACTIVE_LOW>;
	sd-uhs-sdr50;
	status = "okay";
};

&i2c1 {
	pinctrl-0 = <&i2c1_pins>;
	pinctrl-names = "default";

	status = "okay";
	clock-frequency = <400000>;

	composite-in@20 {
		compatible = "adi,adv7180";
		reg = <0x20>;
		remote = <&vin0>;

		port {
			adv7180: endpoint {
				bus-width = <8>;
				remote-endpoint = <&vin0ep>;
			};
		};
	};
};

&i2c4 {
	pinctrl-0 = <&i2c4_pins>;
	pinctrl-names = "i2c-exio4";
};

&vin0 {
	status = "okay";
	pinctrl-0 = <&vin0_pins>;
	pinctrl-names = "default";

	port {
		#address-cells = <1>;
		#size-cells = <0>;

		vin0ep: endpoint {
			remote-endpoint = <&adv7180>;
			bus-width = <8>;
		};
	};
};

&scif2 {
	pinctrl-0 = <&scif2_pins>;
	pinctrl-names = "default";

	status = "okay";
};

&scif_clk {
	clock-frequency = <14745600>;
};

&qspi {
	pinctrl-0 = <&qspi_pins>;
	pinctrl-names = "default";

	status = "okay";

	flash@0 {
		compatible = "spansion,s25fl512s", "jedec,spi-nor";
		reg = <0>;
		spi-max-frequency = <30000000>;
		spi-tx-bus-width = <4>;
		spi-rx-bus-width = <4>;
		spi-cpol;
		spi-cpha;
		m25p,fast-read;

		partitions {
			compatible = "fixed-partitions";
			#address-cells = <1>;
			#size-cells = <1>;

			partition@0 {
				label = "loader";
				reg = <0x00000000 0x00040000>;
				read-only;
			};
			partition@40000 {
				label = "system";
				reg = <0x00040000 0x00040000>;
				read-only;
			};
			partition@80000 {
				label = "user";
				reg = <0x00080000 0x03f80000>;
			};
		};
	};
};
Commit	Line	Data
a742795b UH	1	/*
	2	* Device Tree Source for the Alt board
	3	*
	4	* Copyright (C) 2014 Renesas Electronics Corporation
	5	*
	6	* This file is licensed under the terms of the GNU General Public License
	7	* version 2. This program is licensed "as is" without any warranty of any
	8	* kind, whether express or implied.
	9	*/
	10
	11	/dts-v1/;
	12	#include "r8a7794.dtsi"
2b41091b	13	#include <dt-bindings/gpio/gpio.h>
a742795b UH	14
	15	/ {
	16	model = "Alt";
	17	compatible = "renesas,alt", "renesas,r8a7794";
	18
	19	aliases {
	20	serial0 = &scif2;
e60a19f0 SH	21	i2c10 = &gpioi2c4;
e60a19f0 SH	22	i2c12 = &i2cexio4;
a742795b UH	23	};
	24
	25	chosen {
89aeff99	26	bootargs = "ignore_loglevel rw root=/dev/nfs ip=dhcp";
b575f994	27	stdout-path = "serial0:115200n8";
a742795b UH	28	};
	29
	30	memory@40000000 {
	31	device_type = "memory";
	32	reg = <0 0x40000000 0 0x40000000>;
	33	};
	34
e6ed3f53 SH	35	d3_3v: regulator-d3-3v {
	36	compatible = "regulator-fixed";
	37	regulator-name = "D3.3V";
	38	regulator-min-microvolt = <3300000>;
	39	regulator-max-microvolt = <3300000>;
	40	regulator-boot-on;
	41	regulator-always-on;
	42	};
	43
2b41091b SH	44	vcc_sdhi0: regulator-vcc-sdhi0 {
	45	compatible = "regulator-fixed";
	46
	47	regulator-name = "SDHI0 Vcc";
	48	regulator-min-microvolt = <3300000>;
	49	regulator-max-microvolt = <3300000>;
	50
	51	gpio = <&gpio2 26 GPIO_ACTIVE_HIGH>;
	52	enable-active-high;
	53	};
	54
	55	vccq_sdhi0: regulator-vccq-sdhi0 {
	56	compatible = "regulator-gpio";
	57
	58	regulator-name = "SDHI0 VccQ";
	59	regulator-min-microvolt = <1800000>;
	60	regulator-max-microvolt = <3300000>;
	61
	62	gpios = <&gpio2 29 GPIO_ACTIVE_HIGH>;
	63	gpios-states = <1>;
	64	states = <3300000 1
	65	1800000 0>;
	66	};
	67
	68	vcc_sdhi1: regulator-vcc-sdhi1 {
	69	compatible = "regulator-fixed";
	70
	71	regulator-name = "SDHI1 Vcc";
	72	regulator-min-microvolt = <3300000>;
	73	regulator-max-microvolt = <3300000>;
	74
	75	gpio = <&gpio4 26 GPIO_ACTIVE_HIGH>;
	76	enable-active-high;
	77	};
	78
	79	vccq_sdhi1: regulator-vccq-sdhi1 {
	80	compatible = "regulator-gpio";
	81
	82	regulator-name = "SDHI1 VccQ";
	83	regulator-min-microvolt = <1800000>;
	84	regulator-max-microvolt = <3300000>;
	85
	86	gpios = <&gpio4 29 GPIO_ACTIVE_HIGH>;
	87	gpios-states = <1>;
	88	states = <3300000 1
	89	1800000 0>;
	90	};
	91
a742795b UH	92	lbsc {
	93	#address-cells = <1>;
	94	#size-cells = <1>;
	95	};
876e7fb9 MD	96
	97	vga-encoder {
	98	compatible = "adi,adv7123";
	99
	100	ports {
	101	#address-cells = <1>;
	102	#size-cells = <0>;
	103
	104	port@0 {
	105	reg = <0>;
	106	adv7123_in: endpoint {
	107	remote-endpoint = <&du_out_rgb1>;
	108	};
	109	};
	110	port@1 {
	111	reg = <1>;
	112	adv7123_out: endpoint {
	113	remote-endpoint = <&vga_in>;
	114	};
	115	};
	116	};
	117	};
	118
	119	vga {
	120	compatible = "vga-connector";
	121
	122	port {
	123	vga_in: endpoint {
	124	remote-endpoint = <&adv7123_out>;
	125	};
	126	};
	127	};
	128
	129	x2_clk: x2-clock {
	130	compatible = "fixed-clock";
	131	#clock-cells = <0>;
	132	clock-frequency = <74250000>;
	133	};
	134
	135	x13_clk: x13-clock {
	136	compatible = "fixed-clock";
	137	#clock-cells = <0>;
	138	clock-frequency = <148500000>;
	139	};
e60a19f0 SH	140
	141	gpioi2c4: i2c-10 {
	142	#address-cells = <1>;
	143	#size-cells = <0>;
	144	compatible = "i2c-gpio";
	145	status = "disabled";
	146	gpios = <&gpio4 9 GPIO_ACTIVE_HIGH /* sda */
	147	&gpio4 8 GPIO_ACTIVE_HIGH /* scl */
	148	>;
	149	i2c-gpio,delay-us = <5>;
	150	};
	151
	152	/*
	153	* I2C4 is routed to EXIO connector B, pins 73 (SCL) + 74 (SDA).
	154	* A fallback to GPIO is provided.
	155	*/
	156	i2cexio4: i2c-14 {
	157	compatible = "i2c-demux-pinctrl";
	158	i2c-parent = <&i2c4>, <&gpioi2c4>;
	159	i2c-bus-name = "i2c-exio4";
	160	#address-cells = <1>;
	161	#size-cells = <0>;
	162	};
876e7fb9 MD	163	};
	164
	165	&du {
13b8b8e8 MD	166	pinctrl-0 = <&du_pins>;
13b8b8e8 MD	167	pinctrl-names = "default";
876e7fb9 MD	168	status = "okay";
	169
	170	clocks = <&mstp7_clks R8A7794_CLK_DU0>,
7f698bf6	171	<&mstp7_clks R8A7794_CLK_DU1>,
876e7fb9 MD	172	<&x13_clk>, <&x2_clk>;
	173	clock-names = "du.0", "du.1", "dclkin.0", "dclkin.1";
	174
	175	ports {
	176	port@1 {
	177	endpoint {
	178	remote-endpoint = <&adv7123_in>;
	179	};
	180	};
	181	};
a742795b UH	182	};
	183
	184	&extal_clk {
	185	clock-frequency = <20000000>;
	186	};
	187
22b16071	188	&pfc {
8a758a94 GU	189	pinctrl-0 = <&scif_clk_pins>;
	190	pinctrl-names = "default";
	191
13b8b8e8	192	du_pins: du {
5591aa42 JM	193	groups = "du1_rgb666", "du1_sync", "du1_disp", "du1_clk0_out";
5591aa42 JM	194	function = "du1";
13b8b8e8 MD	195	};
13b8b8e8 MD	196
d88f5bc4	197	scif2_pins: scif2 {
be7359dd SH	198	groups = "scif2_data";
be7359dd SH	199	function = "scif2";
22b16071 SH	200	};
22b16071 SH	201
8a758a94	202	scif_clk_pins: scif_clk {
be7359dd SH	203	groups = "scif_clk";
be7359dd SH	204	function = "scif_clk";
8a758a94 GU	205	};
8a758a94 GU	206
22b16071	207	ether_pins: ether {
be7359dd SH	208	groups = "eth_link", "eth_mdio", "eth_rmii";
be7359dd SH	209	function = "eth";
22b16071 SH	210	};
22b16071 SH	211
c175e7ab	212	phy1_pins: phy1 {
be7359dd SH	213	groups = "intc_irq8";
be7359dd SH	214	function = "intc";
22b16071	215	};
7f81bf72 UH	216
7f81bf72 UH	217	i2c1_pins: i2c1 {
be7359dd SH	218	groups = "i2c1";
be7359dd SH	219	function = "i2c1";
7f81bf72	220	};
d537543b	221
e60a19f0 SH	222	i2c4_pins: i2c4 {
	223	groups = "i2c4";
	224	function = "i2c4";
	225	};
	226
d537543b	227	vin0_pins: vin0 {
be7359dd SH	228	groups = "vin0_data8", "vin0_clk";
be7359dd SH	229	function = "vin0";
d537543b	230	};
2b41091b	231
e6ed3f53 SH	232	mmcif0_pins: mmcif0 {
	233	groups = "mmc_data8", "mmc_ctrl";
	234	function = "mmc";
	235	};
	236
2b41091b SH	237	sdhi0_pins: sd0 {
	238	groups = "sdhi0_data4", "sdhi0_ctrl";
	239	function = "sdhi0";
9510f349 SH	240	power-source = <3300>;
	241	};
	242
	243	sdhi0_pins_uhs: sd0_uhs {
	244	groups = "sdhi0_data4", "sdhi0_ctrl";
	245	function = "sdhi0";
	246	power-source = <1800>;
2b41091b SH	247	};
	248
	249	sdhi1_pins: sd1 {
	250	groups = "sdhi1_data4", "sdhi1_ctrl";
	251	function = "sdhi1";
9510f349 SH	252	power-source = <3300>;
	253	};
	254
	255	sdhi1_pins_uhs: sd1_uhs {
	256	groups = "sdhi1_data4", "sdhi1_ctrl";
	257	function = "sdhi1";
	258	power-source = <1800>;
2b41091b	259	};
22b16071 SH	260	};
22b16071 SH	261
a742795b	262	&cmt0 {
38e02908	263	status = "okay";
a742795b UH	264	};
a742795b UH	265
6b78e6ae	266	&pfc {
fc10f3c9	267	qspi_pins: qspi {
be7359dd SH	268	groups = "qspi_ctrl", "qspi_data4";
be7359dd SH	269	function = "qspi";
6b78e6ae SH	270	};
	271	};
	272
a895b7cd	273	&ether {
c175e7ab SH	274	pinctrl-0 = <&ether_pins &phy1_pins>;
	275	pinctrl-names = "default";
	276
a895b7cd LP	277	phy-handle = <&phy1>;
	278	renesas,ether-link-active-low;
	279	status = "okay";
	280
	281	phy1: ethernet-phy@1 {
	282	reg = <1>;
	283	interrupt-parent = <&irqc0>;
1fc58015	284	interrupts = <8 IRQ_TYPE_LEVEL_LOW>;
a895b7cd LP	285	micrel,led-mode = <1>;
	286	};
	287	};
	288
e6ed3f53 SH	289	&mmcif0 {
	290	pinctrl-0 = <&mmcif0_pins>;
	291	pinctrl-names = "default";
	292
	293	vmmc-supply = <&d3_3v>;
	294	vqmmc-supply = <&d3_3v>;
	295	bus-width = <8>;
	296	non-removable;
	297	status = "okay";
	298	};
	299
2b41091b SH	300	&sdhi0 {
2b41091b SH	301	pinctrl-0 = <&sdhi0_pins>;
9510f349 SH	302	pinctrl-1 = <&sdhi0_pins_uhs>;
9510f349 SH	303	pinctrl-names = "default", "state_uhs";
2b41091b SH	304
	305	vmmc-supply = <&vcc_sdhi0>;
	306	vqmmc-supply = <&vccq_sdhi0>;
	307	cd-gpios = <&gpio6 6 GPIO_ACTIVE_LOW>;
	308	wp-gpios = <&gpio6 7 GPIO_ACTIVE_LOW>;
9510f349	309	sd-uhs-sdr50;
f9f2fc0b	310	sd-uhs-sdr104;
2b41091b SH	311	status = "okay";
	312	};
	313
	314	&sdhi1 {
	315	pinctrl-0 = <&sdhi1_pins>;
9510f349 SH	316	pinctrl-1 = <&sdhi1_pins_uhs>;
9510f349 SH	317	pinctrl-names = "default", "state_uhs";
2b41091b SH	318
	319	vmmc-supply = <&vcc_sdhi1>;
	320	vqmmc-supply = <&vccq_sdhi1>;
	321	cd-gpios = <&gpio6 14 GPIO_ACTIVE_LOW>;
	322	wp-gpios = <&gpio6 15 GPIO_ACTIVE_LOW>;
9510f349	323	sd-uhs-sdr50;
2b41091b SH	324	status = "okay";
	325	};
	326
7f81bf72 UH	327	&i2c1 {
	328	pinctrl-0 = <&i2c1_pins>;
	329	pinctrl-names = "default";
	330
	331	status = "okay";
	332	clock-frequency = <400000>;
d537543b UH	333
	334	composite-in@20 {
	335	compatible = "adi,adv7180";
	336	reg = <0x20>;
	337	remote = <&vin0>;
	338
	339	port {
	340	adv7180: endpoint {
	341	bus-width = <8>;
	342	remote-endpoint = <&vin0ep>;
	343	};
	344	};
	345	};
	346	};
	347
e60a19f0 SH	348	&i2c4 {
	349	pinctrl-0 = <&i2c4_pins>;
	350	pinctrl-names = "i2c-exio4";
	351	};
	352
d537543b UH	353	&vin0 {
	354	status = "okay";
	355	pinctrl-0 = <&vin0_pins>;
	356	pinctrl-names = "default";
	357
	358	port {
	359	#address-cells = <1>;
	360	#size-cells = <0>;
	361
	362	vin0ep: endpoint {
	363	remote-endpoint = <&adv7180>;
	364	bus-width = <8>;
	365	};
	366	};
7f81bf72 UH	367	};
7f81bf72 UH	368
a742795b	369	&scif2 {
7256587c SH	370	pinctrl-0 = <&scif2_pins>;
	371	pinctrl-names = "default";
	372
38e02908	373	status = "okay";
a742795b	374	};
6b78e6ae	375
8a758a94 GU	376	&scif_clk {
8a758a94 GU	377	clock-frequency = <14745600>;
8a758a94 GU	378	};
8a758a94 GU	379
6b78e6ae SH	380	&qspi {
	381	pinctrl-0 = <&qspi_pins>;
	382	pinctrl-names = "default";
	383
	384	status = "okay";
	385
	386	flash@0 {
	387	compatible = "spansion,s25fl512s", "jedec,spi-nor";
	388	reg = <0>;
	389	spi-max-frequency = <30000000>;
	390	spi-tx-bus-width = <4>;
	391	spi-rx-bus-width = <4>;
	392	spi-cpol;
	393	spi-cpha;
	394	m25p,fast-read;
	395
	396	partitions {
	397	compatible = "fixed-partitions";
	398	#address-cells = <1>;
	399	#size-cells = <1>;
	400
	401	partition@0 {
	402	label = "loader";
	403	reg = <0x00000000 0x00040000>;
	404	read-only;
	405	};
	406	partition@40000 {
	407	label = "system";
	408	reg = <0x00040000 0x00040000>;
	409	read-only;
	410	};
	411	partition@80000 {
	412	label = "user";
	413	reg = <0x00080000 0x03f80000>;
	414	};
	415	};
	416	};
	417	};