Commit | Line | Data |
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e3da5b36 MD |
1 | /* |
2 | * Device Tree Source for the r7s72100 SoC | |
3 | * | |
b6face40 WS |
4 | * Copyright (C) 2013-14 Renesas Solutions Corp. |
5 | * Copyright (C) 2014 Wolfram Sang, Sang Engineering <wsa@sang-engineering.com> | |
e3da5b36 MD |
6 | * |
7 | * This file is licensed under the terms of the GNU General Public License | |
8 | * version 2. This program is licensed "as is" without any warranty of any | |
9 | * kind, whether express or implied. | |
10 | */ | |
11 | ||
b6face40 | 12 | #include <dt-bindings/clock/r7s72100-clock.h> |
16af4e97 | 13 | #include <dt-bindings/interrupt-controller/arm-gic.h> |
4b18e83f GU |
14 | #include <dt-bindings/interrupt-controller/irq.h> |
15 | ||
e3da5b36 MD |
16 | / { |
17 | compatible = "renesas,r7s72100"; | |
18 | interrupt-parent = <&gic>; | |
19 | #address-cells = <1>; | |
20 | #size-cells = <1>; | |
21 | ||
4b18e83f | 22 | aliases { |
c81a4d3d WS |
23 | i2c0 = &i2c0; |
24 | i2c1 = &i2c1; | |
25 | i2c2 = &i2c2; | |
26 | i2c3 = &i2c3; | |
4b18e83f GU |
27 | spi0 = &spi0; |
28 | spi1 = &spi1; | |
29 | spi2 = &spi2; | |
30 | spi3 = &spi3; | |
31 | spi4 = &spi4; | |
32 | }; | |
33 | ||
b6face40 WS |
34 | clocks { |
35 | ranges; | |
36 | #address-cells = <1>; | |
37 | #size-cells = <1>; | |
38 | ||
39 | /* External clocks */ | |
21f18970 | 40 | extal_clk: extal { |
b6face40 WS |
41 | #clock-cells = <0>; |
42 | compatible = "fixed-clock"; | |
43 | /* If clk present, value must be set by board */ | |
44 | clock-frequency = <0>; | |
b6face40 WS |
45 | }; |
46 | ||
21f18970 | 47 | usb_x1_clk: usb_x1 { |
b6face40 WS |
48 | #clock-cells = <0>; |
49 | compatible = "fixed-clock"; | |
50 | /* If clk present, value must be set by board */ | |
51 | clock-frequency = <0>; | |
b6face40 WS |
52 | }; |
53 | ||
b6face40 | 54 | /* Fixed factor clocks */ |
21f18970 | 55 | b_clk: b { |
b6face40 WS |
56 | #clock-cells = <0>; |
57 | compatible = "fixed-factor-clock"; | |
58 | clocks = <&cpg_clocks R7S72100_CLK_PLL>; | |
59 | clock-mult = <1>; | |
60 | clock-div = <3>; | |
b6face40 | 61 | }; |
21f18970 | 62 | p1_clk: p1 { |
b6face40 WS |
63 | #clock-cells = <0>; |
64 | compatible = "fixed-factor-clock"; | |
65 | clocks = <&cpg_clocks R7S72100_CLK_PLL>; | |
66 | clock-mult = <1>; | |
67 | clock-div = <6>; | |
b6face40 | 68 | }; |
21f18970 | 69 | p0_clk: p0 { |
b6face40 WS |
70 | #clock-cells = <0>; |
71 | compatible = "fixed-factor-clock"; | |
72 | clocks = <&cpg_clocks R7S72100_CLK_PLL>; | |
73 | clock-mult = <1>; | |
74 | clock-div = <12>; | |
b6face40 WS |
75 | }; |
76 | ||
005980c0 UH |
77 | /* Special CPG clocks */ |
78 | cpg_clocks: cpg_clocks@fcfe0000 { | |
79 | #clock-cells = <1>; | |
80 | compatible = "renesas,r7s72100-cpg-clocks", | |
81 | "renesas,rz-cpg-clocks"; | |
82 | reg = <0xfcfe0000 0x18>; | |
83 | clocks = <&extal_clk>, <&usb_x1_clk>; | |
84 | clock-output-names = "pll", "i", "g"; | |
cbe1f838 | 85 | #power-domain-cells = <0>; |
005980c0 UH |
86 | }; |
87 | ||
b6face40 WS |
88 | /* MSTP clocks */ |
89 | mstp3_clks: mstp3_clks@fcfe0420 { | |
90 | #clock-cells = <1>; | |
91 | compatible = "renesas,r7s72100-mstp-clocks", "renesas,cpg-mstp-clocks"; | |
92 | reg = <0xfcfe0420 4>; | |
93 | clocks = <&p0_clk>; | |
94 | clock-indices = <R7S72100_CLK_MTU2>; | |
95 | clock-output-names = "mtu2"; | |
96 | }; | |
97 | ||
98 | mstp4_clks: mstp4_clks@fcfe0424 { | |
99 | #clock-cells = <1>; | |
100 | compatible = "renesas,r7s72100-mstp-clocks", "renesas,cpg-mstp-clocks"; | |
101 | reg = <0xfcfe0424 4>; | |
102 | clocks = <&p1_clk>, <&p1_clk>, <&p1_clk>, <&p1_clk>, | |
103 | <&p1_clk>, <&p1_clk>, <&p1_clk>, <&p1_clk>; | |
104 | clock-indices = < | |
105 | R7S72100_CLK_SCIF0 R7S72100_CLK_SCIF1 R7S72100_CLK_SCIF2 R7S72100_CLK_SCIF3 | |
106 | R7S72100_CLK_SCIF4 R7S72100_CLK_SCIF5 R7S72100_CLK_SCIF6 R7S72100_CLK_SCIF7 | |
107 | >; | |
108 | clock-output-names = "scif0", "scif1", "scif2", "scif3", "scif4", "scif5", "scif6", "scif7"; | |
109 | }; | |
d165566b | 110 | |
969244f9 CB |
111 | mstp7_clks: mstp7_clks@fcfe0430 { |
112 | #clock-cells = <1>; | |
113 | compatible = "renesas,r7s72100-mstp-clocks", "renesas,cpg-mstp-clocks"; | |
114 | reg = <0xfcfe0430 4>; | |
115 | clocks = <&p0_clk>; | |
116 | clock-indices = <R7S72100_CLK_ETHER>; | |
117 | clock-output-names = "ether"; | |
118 | }; | |
119 | ||
6c35a666 CB |
120 | mstp8_clks: mstp8_clks@fcfe0434 { |
121 | #clock-cells = <1>; | |
122 | compatible = "renesas,r7s72100-mstp-clocks", "renesas,cpg-mstp-clocks"; | |
123 | reg = <0xfcfe0434 4>; | |
124 | clocks = <&p1_clk>; | |
125 | clock-indices = <R7S72100_CLK_MMCIF>; | |
126 | clock-output-names = "mmcif"; | |
127 | }; | |
128 | ||
d165566b WS |
129 | mstp9_clks: mstp9_clks@fcfe0438 { |
130 | #clock-cells = <1>; | |
131 | compatible = "renesas,r7s72100-mstp-clocks", "renesas,cpg-mstp-clocks"; | |
132 | reg = <0xfcfe0438 4>; | |
133 | clocks = <&p0_clk>, <&p0_clk>, <&p0_clk>, <&p0_clk>; | |
134 | clock-indices = < | |
135 | R7S72100_CLK_I2C0 R7S72100_CLK_I2C1 R7S72100_CLK_I2C2 R7S72100_CLK_I2C3 | |
136 | >; | |
137 | clock-output-names = "i2c0", "i2c1", "i2c2", "i2c3"; | |
138 | }; | |
52eed4f5 WS |
139 | |
140 | mstp10_clks: mstp10_clks@fcfe043c { | |
141 | #clock-cells = <1>; | |
142 | compatible = "renesas,r7s72100-mstp-clocks", "renesas,cpg-mstp-clocks"; | |
143 | reg = <0xfcfe043c 4>; | |
144 | clocks = <&p1_clk>, <&p1_clk>, <&p1_clk>, <&p1_clk>, | |
145 | <&p1_clk>; | |
146 | clock-indices = < | |
147 | R7S72100_CLK_SPI0 R7S72100_CLK_SPI1 R7S72100_CLK_SPI2 R7S72100_CLK_SPI3 | |
148 | R7S72100_CLK_SPI4 | |
149 | >; | |
150 | clock-output-names = "spi0", "spi1", "spi2", "spi3", "spi4"; | |
151 | }; | |
7c8522b7 CB |
152 | mstp12_clks: mstp12_clks@fcfe0444 { |
153 | #clock-cells = <1>; | |
154 | compatible = "renesas,r7s72100-mstp-clocks", "renesas,cpg-mstp-clocks"; | |
155 | reg = <0xfcfe0444 4>; | |
156 | clocks = <&p1_clk>, <&p1_clk>; | |
157 | clock-indices = <R7S72100_CLK_SDHI1 R7S72100_CLK_SDHI0>; | |
158 | clock-output-names = "sdhi1", "sdhi0"; | |
159 | }; | |
b6face40 WS |
160 | }; |
161 | ||
e3da5b36 MD |
162 | cpus { |
163 | #address-cells = <1>; | |
164 | #size-cells = <0>; | |
165 | ||
166 | cpu@0 { | |
167 | device_type = "cpu"; | |
168 | compatible = "arm,cortex-a9"; | |
169 | reg = <0>; | |
005407fd | 170 | clock-frequency = <400000000>; |
e3da5b36 MD |
171 | }; |
172 | }; | |
173 | ||
4c84c1b3 WS |
174 | scif0: serial@e8007000 { |
175 | compatible = "renesas,scif-r7s72100", "renesas,scif"; | |
176 | reg = <0xe8007000 64>; | |
16af4e97 SH |
177 | interrupts = <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>, |
178 | <GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH>, | |
179 | <GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>, | |
180 | <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>; | |
4c84c1b3 | 181 | clocks = <&mstp4_clks R7S72100_CLK_SCIF0>; |
92489120 | 182 | clock-names = "fck"; |
cbe1f838 | 183 | power-domains = <&cpg_clocks>; |
4c84c1b3 WS |
184 | status = "disabled"; |
185 | }; | |
186 | ||
187 | scif1: serial@e8007800 { | |
188 | compatible = "renesas,scif-r7s72100", "renesas,scif"; | |
189 | reg = <0xe8007800 64>; | |
16af4e97 SH |
190 | interrupts = <GIC_SPI 194 IRQ_TYPE_LEVEL_HIGH>, |
191 | <GIC_SPI 195 IRQ_TYPE_LEVEL_HIGH>, | |
192 | <GIC_SPI 196 IRQ_TYPE_LEVEL_HIGH>, | |
193 | <GIC_SPI 193 IRQ_TYPE_LEVEL_HIGH>; | |
4c84c1b3 | 194 | clocks = <&mstp4_clks R7S72100_CLK_SCIF1>; |
92489120 | 195 | clock-names = "fck"; |
cbe1f838 | 196 | power-domains = <&cpg_clocks>; |
4c84c1b3 WS |
197 | status = "disabled"; |
198 | }; | |
199 | ||
200 | scif2: serial@e8008000 { | |
201 | compatible = "renesas,scif-r7s72100", "renesas,scif"; | |
202 | reg = <0xe8008000 64>; | |
16af4e97 SH |
203 | interrupts = <GIC_SPI 198 IRQ_TYPE_LEVEL_HIGH>, |
204 | <GIC_SPI 199 IRQ_TYPE_LEVEL_HIGH>, | |
205 | <GIC_SPI 200 IRQ_TYPE_LEVEL_HIGH>, | |
206 | <GIC_SPI 197 IRQ_TYPE_LEVEL_HIGH>; | |
4c84c1b3 | 207 | clocks = <&mstp4_clks R7S72100_CLK_SCIF2>; |
92489120 | 208 | clock-names = "fck"; |
cbe1f838 | 209 | power-domains = <&cpg_clocks>; |
4c84c1b3 WS |
210 | status = "disabled"; |
211 | }; | |
212 | ||
213 | scif3: serial@e8008800 { | |
214 | compatible = "renesas,scif-r7s72100", "renesas,scif"; | |
215 | reg = <0xe8008800 64>; | |
16af4e97 SH |
216 | interrupts = <GIC_SPI 202 IRQ_TYPE_LEVEL_HIGH>, |
217 | <GIC_SPI 203 IRQ_TYPE_LEVEL_HIGH>, | |
218 | <GIC_SPI 204 IRQ_TYPE_LEVEL_HIGH>, | |
219 | <GIC_SPI 201 IRQ_TYPE_LEVEL_HIGH>; | |
4c84c1b3 | 220 | clocks = <&mstp4_clks R7S72100_CLK_SCIF3>; |
92489120 | 221 | clock-names = "fck"; |
cbe1f838 | 222 | power-domains = <&cpg_clocks>; |
4c84c1b3 WS |
223 | status = "disabled"; |
224 | }; | |
225 | ||
226 | scif4: serial@e8009000 { | |
227 | compatible = "renesas,scif-r7s72100", "renesas,scif"; | |
228 | reg = <0xe8009000 64>; | |
16af4e97 SH |
229 | interrupts = <GIC_SPI 206 IRQ_TYPE_LEVEL_HIGH>, |
230 | <GIC_SPI 207 IRQ_TYPE_LEVEL_HIGH>, | |
231 | <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>, | |
232 | <GIC_SPI 205 IRQ_TYPE_LEVEL_HIGH>; | |
4c84c1b3 | 233 | clocks = <&mstp4_clks R7S72100_CLK_SCIF4>; |
92489120 | 234 | clock-names = "fck"; |
cbe1f838 | 235 | power-domains = <&cpg_clocks>; |
4c84c1b3 WS |
236 | status = "disabled"; |
237 | }; | |
238 | ||
239 | scif5: serial@e8009800 { | |
240 | compatible = "renesas,scif-r7s72100", "renesas,scif"; | |
241 | reg = <0xe8009800 64>; | |
16af4e97 SH |
242 | interrupts = <GIC_SPI 210 IRQ_TYPE_LEVEL_HIGH>, |
243 | <GIC_SPI 211 IRQ_TYPE_LEVEL_HIGH>, | |
244 | <GIC_SPI 212 IRQ_TYPE_LEVEL_HIGH>, | |
245 | <GIC_SPI 209 IRQ_TYPE_LEVEL_HIGH>; | |
4c84c1b3 | 246 | clocks = <&mstp4_clks R7S72100_CLK_SCIF5>; |
92489120 | 247 | clock-names = "fck"; |
cbe1f838 | 248 | power-domains = <&cpg_clocks>; |
4c84c1b3 WS |
249 | status = "disabled"; |
250 | }; | |
251 | ||
252 | scif6: serial@e800a000 { | |
253 | compatible = "renesas,scif-r7s72100", "renesas,scif"; | |
254 | reg = <0xe800a000 64>; | |
16af4e97 SH |
255 | interrupts = <GIC_SPI 214 IRQ_TYPE_LEVEL_HIGH>, |
256 | <GIC_SPI 215 IRQ_TYPE_LEVEL_HIGH>, | |
257 | <GIC_SPI 216 IRQ_TYPE_LEVEL_HIGH>, | |
258 | <GIC_SPI 213 IRQ_TYPE_LEVEL_HIGH>; | |
4c84c1b3 | 259 | clocks = <&mstp4_clks R7S72100_CLK_SCIF6>; |
92489120 | 260 | clock-names = "fck"; |
cbe1f838 | 261 | power-domains = <&cpg_clocks>; |
4c84c1b3 WS |
262 | status = "disabled"; |
263 | }; | |
264 | ||
265 | scif7: serial@e800a800 { | |
266 | compatible = "renesas,scif-r7s72100", "renesas,scif"; | |
267 | reg = <0xe800a800 64>; | |
16af4e97 SH |
268 | interrupts = <GIC_SPI 218 IRQ_TYPE_LEVEL_HIGH>, |
269 | <GIC_SPI 219 IRQ_TYPE_LEVEL_HIGH>, | |
270 | <GIC_SPI 220 IRQ_TYPE_LEVEL_HIGH>, | |
271 | <GIC_SPI 217 IRQ_TYPE_LEVEL_HIGH>; | |
4c84c1b3 | 272 | clocks = <&mstp4_clks R7S72100_CLK_SCIF7>; |
92489120 | 273 | clock-names = "fck"; |
cbe1f838 | 274 | power-domains = <&cpg_clocks>; |
4c84c1b3 WS |
275 | status = "disabled"; |
276 | }; | |
277 | ||
4b18e83f GU |
278 | spi0: spi@e800c800 { |
279 | compatible = "renesas,rspi-r7s72100", "renesas,rspi-rz"; | |
280 | reg = <0xe800c800 0x24>; | |
16af4e97 SH |
281 | interrupts = <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, |
282 | <GIC_SPI 239 IRQ_TYPE_LEVEL_HIGH>, | |
283 | <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>; | |
4b18e83f | 284 | interrupt-names = "error", "rx", "tx"; |
52eed4f5 | 285 | clocks = <&mstp10_clks R7S72100_CLK_SPI0>; |
cbe1f838 | 286 | power-domains = <&cpg_clocks>; |
4b18e83f GU |
287 | num-cs = <1>; |
288 | #address-cells = <1>; | |
289 | #size-cells = <0>; | |
290 | status = "disabled"; | |
291 | }; | |
292 | ||
293 | spi1: spi@e800d000 { | |
294 | compatible = "renesas,rspi-r7s72100", "renesas,rspi-rz"; | |
295 | reg = <0xe800d000 0x24>; | |
16af4e97 SH |
296 | interrupts = <GIC_SPI 241 IRQ_TYPE_LEVEL_HIGH>, |
297 | <GIC_SPI 242 IRQ_TYPE_LEVEL_HIGH>, | |
298 | <GIC_SPI 243 IRQ_TYPE_LEVEL_HIGH>; | |
4b18e83f | 299 | interrupt-names = "error", "rx", "tx"; |
52eed4f5 | 300 | clocks = <&mstp10_clks R7S72100_CLK_SPI1>; |
cbe1f838 | 301 | power-domains = <&cpg_clocks>; |
4b18e83f GU |
302 | num-cs = <1>; |
303 | #address-cells = <1>; | |
304 | #size-cells = <0>; | |
305 | status = "disabled"; | |
306 | }; | |
307 | ||
308 | spi2: spi@e800d800 { | |
309 | compatible = "renesas,rspi-r7s72100", "renesas,rspi-rz"; | |
310 | reg = <0xe800d800 0x24>; | |
16af4e97 SH |
311 | interrupts = <GIC_SPI 244 IRQ_TYPE_LEVEL_HIGH>, |
312 | <GIC_SPI 245 IRQ_TYPE_LEVEL_HIGH>, | |
313 | <GIC_SPI 246 IRQ_TYPE_LEVEL_HIGH>; | |
4b18e83f | 314 | interrupt-names = "error", "rx", "tx"; |
52eed4f5 | 315 | clocks = <&mstp10_clks R7S72100_CLK_SPI2>; |
cbe1f838 | 316 | power-domains = <&cpg_clocks>; |
4b18e83f GU |
317 | num-cs = <1>; |
318 | #address-cells = <1>; | |
319 | #size-cells = <0>; | |
320 | status = "disabled"; | |
321 | }; | |
322 | ||
323 | spi3: spi@e800e000 { | |
324 | compatible = "renesas,rspi-r7s72100", "renesas,rspi-rz"; | |
325 | reg = <0xe800e000 0x24>; | |
16af4e97 SH |
326 | interrupts = <GIC_SPI 247 IRQ_TYPE_LEVEL_HIGH>, |
327 | <GIC_SPI 248 IRQ_TYPE_LEVEL_HIGH>, | |
328 | <GIC_SPI 249 IRQ_TYPE_LEVEL_HIGH>; | |
4b18e83f | 329 | interrupt-names = "error", "rx", "tx"; |
52eed4f5 | 330 | clocks = <&mstp10_clks R7S72100_CLK_SPI3>; |
cbe1f838 | 331 | power-domains = <&cpg_clocks>; |
4b18e83f GU |
332 | num-cs = <1>; |
333 | #address-cells = <1>; | |
334 | #size-cells = <0>; | |
335 | status = "disabled"; | |
336 | }; | |
337 | ||
338 | spi4: spi@e800e800 { | |
339 | compatible = "renesas,rspi-r7s72100", "renesas,rspi-rz"; | |
340 | reg = <0xe800e800 0x24>; | |
16af4e97 SH |
341 | interrupts = <GIC_SPI 250 IRQ_TYPE_LEVEL_HIGH>, |
342 | <GIC_SPI 251 IRQ_TYPE_LEVEL_HIGH>, | |
343 | <GIC_SPI 252 IRQ_TYPE_LEVEL_HIGH>; | |
4b18e83f | 344 | interrupt-names = "error", "rx", "tx"; |
52eed4f5 | 345 | clocks = <&mstp10_clks R7S72100_CLK_SPI4>; |
cbe1f838 | 346 | power-domains = <&cpg_clocks>; |
4b18e83f GU |
347 | num-cs = <1>; |
348 | #address-cells = <1>; | |
349 | #size-cells = <0>; | |
350 | status = "disabled"; | |
351 | }; | |
005980c0 UH |
352 | |
353 | gic: interrupt-controller@e8201000 { | |
d9e1a0ef | 354 | compatible = "arm,pl390"; |
005980c0 UH |
355 | #interrupt-cells = <3>; |
356 | #address-cells = <0>; | |
357 | interrupt-controller; | |
358 | reg = <0xe8201000 0x1000>, | |
359 | <0xe8202000 0x1000>; | |
360 | }; | |
361 | ||
362 | i2c0: i2c@fcfee000 { | |
363 | #address-cells = <1>; | |
364 | #size-cells = <0>; | |
365 | compatible = "renesas,riic-r7s72100", "renesas,riic-rz"; | |
366 | reg = <0xfcfee000 0x44>; | |
16af4e97 SH |
367 | interrupts = <GIC_SPI 157 IRQ_TYPE_LEVEL_HIGH>, |
368 | <GIC_SPI 158 IRQ_TYPE_EDGE_RISING>, | |
369 | <GIC_SPI 159 IRQ_TYPE_EDGE_RISING>, | |
370 | <GIC_SPI 160 IRQ_TYPE_LEVEL_HIGH>, | |
371 | <GIC_SPI 161 IRQ_TYPE_LEVEL_HIGH>, | |
372 | <GIC_SPI 162 IRQ_TYPE_LEVEL_HIGH>, | |
373 | <GIC_SPI 163 IRQ_TYPE_LEVEL_HIGH>, | |
374 | <GIC_SPI 164 IRQ_TYPE_LEVEL_HIGH>; | |
005980c0 UH |
375 | clocks = <&mstp9_clks R7S72100_CLK_I2C0>; |
376 | clock-frequency = <100000>; | |
cbe1f838 | 377 | power-domains = <&cpg_clocks>; |
005980c0 UH |
378 | status = "disabled"; |
379 | }; | |
380 | ||
381 | i2c1: i2c@fcfee400 { | |
382 | #address-cells = <1>; | |
383 | #size-cells = <0>; | |
384 | compatible = "renesas,riic-r7s72100", "renesas,riic-rz"; | |
385 | reg = <0xfcfee400 0x44>; | |
16af4e97 SH |
386 | interrupts = <GIC_SPI 165 IRQ_TYPE_LEVEL_HIGH>, |
387 | <GIC_SPI 166 IRQ_TYPE_EDGE_RISING>, | |
388 | <GIC_SPI 167 IRQ_TYPE_EDGE_RISING>, | |
389 | <GIC_SPI 168 IRQ_TYPE_LEVEL_HIGH>, | |
390 | <GIC_SPI 169 IRQ_TYPE_LEVEL_HIGH>, | |
391 | <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, | |
392 | <GIC_SPI 171 IRQ_TYPE_LEVEL_HIGH>, | |
393 | <GIC_SPI 172 IRQ_TYPE_LEVEL_HIGH>; | |
005980c0 UH |
394 | clocks = <&mstp9_clks R7S72100_CLK_I2C1>; |
395 | clock-frequency = <100000>; | |
cbe1f838 | 396 | power-domains = <&cpg_clocks>; |
005980c0 UH |
397 | status = "disabled"; |
398 | }; | |
399 | ||
400 | i2c2: i2c@fcfee800 { | |
401 | #address-cells = <1>; | |
402 | #size-cells = <0>; | |
403 | compatible = "renesas,riic-r7s72100", "renesas,riic-rz"; | |
404 | reg = <0xfcfee800 0x44>; | |
16af4e97 SH |
405 | interrupts = <GIC_SPI 173 IRQ_TYPE_LEVEL_HIGH>, |
406 | <GIC_SPI 174 IRQ_TYPE_EDGE_RISING>, | |
407 | <GIC_SPI 175 IRQ_TYPE_EDGE_RISING>, | |
408 | <GIC_SPI 176 IRQ_TYPE_LEVEL_HIGH>, | |
409 | <GIC_SPI 177 IRQ_TYPE_LEVEL_HIGH>, | |
410 | <GIC_SPI 178 IRQ_TYPE_LEVEL_HIGH>, | |
411 | <GIC_SPI 179 IRQ_TYPE_LEVEL_HIGH>, | |
412 | <GIC_SPI 180 IRQ_TYPE_LEVEL_HIGH>; | |
005980c0 UH |
413 | clocks = <&mstp9_clks R7S72100_CLK_I2C2>; |
414 | clock-frequency = <100000>; | |
cbe1f838 | 415 | power-domains = <&cpg_clocks>; |
005980c0 UH |
416 | status = "disabled"; |
417 | }; | |
418 | ||
419 | i2c3: i2c@fcfeec00 { | |
420 | #address-cells = <1>; | |
421 | #size-cells = <0>; | |
422 | compatible = "renesas,riic-r7s72100", "renesas,riic-rz"; | |
423 | reg = <0xfcfeec00 0x44>; | |
16af4e97 SH |
424 | interrupts = <GIC_SPI 181 IRQ_TYPE_LEVEL_HIGH>, |
425 | <GIC_SPI 182 IRQ_TYPE_EDGE_RISING>, | |
426 | <GIC_SPI 183 IRQ_TYPE_EDGE_RISING>, | |
427 | <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>, | |
428 | <GIC_SPI 185 IRQ_TYPE_LEVEL_HIGH>, | |
429 | <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>, | |
430 | <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>, | |
431 | <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>; | |
005980c0 UH |
432 | clocks = <&mstp9_clks R7S72100_CLK_I2C3>; |
433 | clock-frequency = <100000>; | |
cbe1f838 | 434 | power-domains = <&cpg_clocks>; |
005980c0 UH |
435 | status = "disabled"; |
436 | }; | |
437 | ||
438 | mtu2: timer@fcff0000 { | |
439 | compatible = "renesas,mtu2-r7s72100", "renesas,mtu2"; | |
440 | reg = <0xfcff0000 0x400>; | |
16af4e97 | 441 | interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>; |
005980c0 UH |
442 | interrupt-names = "tgi0a"; |
443 | clocks = <&mstp3_clks R7S72100_CLK_MTU2>; | |
444 | clock-names = "fck"; | |
cbe1f838 | 445 | power-domains = <&cpg_clocks>; |
005980c0 UH |
446 | status = "disabled"; |
447 | }; | |
e5482401 CB |
448 | |
449 | ether: ethernet@e8203000 { | |
450 | compatible = "renesas,ether-r7s72100"; | |
451 | reg = <0xe8203000 0x800>, | |
452 | <0xe8204800 0x200>; | |
453 | interrupts = <GIC_SPI 327 IRQ_TYPE_LEVEL_HIGH>; | |
454 | clocks = <&mstp7_clks R7S72100_CLK_ETHER>; | |
455 | power-domains = <&cpg_clocks>; | |
456 | phy-mode = "mii"; | |
457 | #address-cells = <1>; | |
458 | #size-cells = <0>; | |
459 | status = "disabled"; | |
460 | }; | |
88786222 CB |
461 | |
462 | mmcif: mmc@e804c800 { | |
463 | compatible = "renesas,mmcif-r7s72100", "renesas,sh-mmcif"; | |
464 | reg = <0xe804c800 0x80>; | |
465 | interrupts = <GIC_SPI 268 IRQ_TYPE_LEVEL_HIGH | |
466 | GIC_SPI 269 IRQ_TYPE_LEVEL_HIGH | |
467 | GIC_SPI 267 IRQ_TYPE_LEVEL_HIGH>; | |
468 | clocks = <&mstp8_clks R7S72100_CLK_MMCIF>; | |
469 | reg-io-width = <4>; | |
470 | bus-width = <8>; | |
471 | status = "disabled"; | |
472 | }; | |
66474697 CB |
473 | |
474 | sdhi0: sd@e804e000 { | |
475 | compatible = "renesas,sdhi-r7s72100"; | |
476 | reg = <0xe804e000 0x100>; | |
477 | interrupts = <GIC_SPI 270 IRQ_TYPE_LEVEL_HIGH | |
478 | GIC_SPI 271 IRQ_TYPE_LEVEL_HIGH | |
479 | GIC_SPI 272 IRQ_TYPE_LEVEL_HIGH>; | |
480 | ||
481 | clocks = <&mstp12_clks R7S72100_CLK_SDHI0>; | |
482 | cap-sd-highspeed; | |
483 | cap-sdio-irq; | |
484 | status = "disabled"; | |
485 | }; | |
486 | ||
487 | sdhi1: sd@e804e800 { | |
488 | compatible = "renesas,sdhi-r7s72100"; | |
489 | reg = <0xe804e800 0x100>; | |
490 | interrupts = <GIC_SPI 273 IRQ_TYPE_LEVEL_HIGH | |
491 | GIC_SPI 274 IRQ_TYPE_LEVEL_HIGH | |
492 | GIC_SPI 275 IRQ_TYPE_LEVEL_HIGH>; | |
493 | ||
494 | clocks = <&mstp12_clks R7S72100_CLK_SDHI1>; | |
495 | cap-sd-highspeed; | |
496 | cap-sdio-irq; | |
497 | status = "disabled"; | |
498 | }; | |
e3da5b36 | 499 | }; |