projects / linux-2.6-block.git / blame
| Commit | Line | Data |
|---|---|---|
| 9d038b2e MS |
1 | // SPDX-License-Identifier: BSD-3-Clause |
| 2 | /* | |
| 3 | * SDX55 SoC device tree source | |
| 4 | * | |
| 5 | * Copyright (c) 2018, The Linux Foundation. All rights reserved. | |
| 6 | * Copyright (c) 2020, Linaro Ltd. | |
| 7 | */ | |
| 8 | ||
| 9 | #include <dt-bindings/clock/qcom,rpmh.h> | |
| 10 | #include <dt-bindings/interrupt-controller/arm-gic.h> | |
| 11 | #include <dt-bindings/soc/qcom,rpmh-rsc.h> | |
| 12 | ||
| 13 | / { | |
| 14 | #address-cells = <1>; | |
| 15 | #size-cells = <1>; | |
| 16 | qcom,msm-id = <357 0x10000>, <368 0x10000>, <418 0x10000>; | |
| 17 | interrupt-parent = <&intc>; | |
| 18 | ||
| 19 | memory { | |
| 20 | device_type = "memory"; | |
| 21 | reg = <0 0>; | |
| 22 | }; | |
| 23 | ||
| 24 | clocks { | |
| 25 | xo_board: xo-board { | |
| 26 | compatible = "fixed-clock"; | |
| 27 | #clock-cells = <0>; | |
| 28 | clock-frequency = <38400000>; | |
| 29 | clock-output-names = "xo_board"; | |
| 30 | }; | |
| 31 | ||
| 32 | sleep_clk: sleep-clk { | |
| 33 | compatible = "fixed-clock"; | |
| 34 | #clock-cells = <0>; | |
| 35 | clock-frequency = <32000>; | |
| 36 | }; | |
| 37 | }; | |
| 38 | ||
| 39 | cpus { | |
| 40 | #address-cells = <1>; | |
| 41 | #size-cells = <0>; | |
| 42 | ||
| 43 | cpu0: cpu@0 { | |
| 44 | device_type = "cpu"; | |
| 45 | compatible = "arm,cortex-a7"; | |
| 46 | reg = <0x0>; | |
| 47 | enable-method = "psci"; | |
| 48 | }; | |
| 49 | }; | |
| 50 | ||
| 51 | psci { | |
| 52 | compatible = "arm,psci-1.0"; | |
| 53 | method = "smc"; | |
| 54 | }; | |
| 55 | ||
| 56 | soc: soc { | |
| 57 | #address-cells = <1>; | |
| 58 | #size-cells = <1>; | |
| 59 | ranges; | |
| 60 | compatible = "simple-bus"; | |
| 61 | ||
| 62 | gcc: clock-controller@100000 { | |
| 63 | compatible = "qcom,gcc-sdx55"; | |
| 64 | reg = <0x100000 0x1f0000>; | |
| 65 | #clock-cells = <1>; | |
| 66 | #reset-cells = <1>; | |
| 67 | clock-names = "bi_tcxo", "sleep_clk"; | |
| 68 | clocks = <&rpmhcc RPMH_CXO_CLK>, <&sleep_clk>; | |
| 69 | }; | |
| 70 | ||
| 71 | blsp1_uart3: serial@831000 { | |
| 72 | compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm"; | |
| 73 | reg = <0x00831000 0x200>; | |
| 74 | interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_LOW>; | |
| 75 | clocks = <&gcc 30>, | |
| 76 | <&gcc 9>; | |
| 77 | clock-names = "core", "iface"; | |
| 78 | status = "disabled"; | |
| 79 | }; | |
| 80 | ||
| 81 | pdc: interrupt-controller@b210000 { | |
| 82 | compatible = "qcom,sdx55-pdc", "qcom,pdc"; | |
| 83 | reg = <0x0b210000 0x30000>; | |
| 84 | qcom,pdc-ranges = <0 179 52>; | |
| 85 | #interrupt-cells = <3>; | |
| 86 | interrupt-parent = <&intc>; | |
| 87 | interrupt-controller; | |
| 88 | }; | |
| 89 | ||
| 90 | intc: interrupt-controller@17800000 { | |
| 91 | compatible = "qcom,msm-qgic2"; | |
| 92 | interrupt-controller; | |
| 93 | interrupt-parent = <&intc>; | |
| 94 | #interrupt-cells = <3>; | |
| 95 | reg = <0x17800000 0x1000>, | |
| 96 | <0x17802000 0x1000>; | |
| 97 | }; | |
| 98 | ||
| 99 | timer@17820000 { | |
| 100 | #address-cells = <1>; | |
| 101 | #size-cells = <1>; | |
| 102 | ranges; | |
| 103 | compatible = "arm,armv7-timer-mem"; | |
| 104 | reg = <0x17820000 0x1000>; | |
| 105 | clock-frequency = <19200000>; | |
| 106 | ||
| 107 | frame@17821000 { | |
| 108 | frame-number = <0>; | |
| 109 | interrupts = <GIC_SPI 7 0x4>, | |
| 110 | <GIC_SPI 6 0x4>; | |
| 111 | reg = <0x17821000 0x1000>, | |
| 112 | <0x17822000 0x1000>; | |
| 113 | }; | |
| 114 | ||
| 115 | frame@17823000 { | |
| 116 | frame-number = <1>; | |
| 117 | interrupts = <GIC_SPI 8 0x4>; | |
| 118 | reg = <0x17823000 0x1000>; | |
| 119 | status = "disabled"; | |
| 120 | }; | |
| 121 | ||
| 122 | frame@17824000 { | |
| 123 | frame-number = <2>; | |
| 124 | interrupts = <GIC_SPI 9 0x4>; | |
| 125 | reg = <0x17824000 0x1000>; | |
| 126 | status = "disabled"; | |
| 127 | }; | |
| 128 | ||
| 129 | frame@17825000 { | |
| 130 | frame-number = <3>; | |
| 131 | interrupts = <GIC_SPI 10 0x4>; | |
| 132 | reg = <0x17825000 0x1000>; | |
| 133 | status = "disabled"; | |
| 134 | }; | |
| 135 | ||
| 136 | frame@17826000 { | |
| 137 | frame-number = <4>; | |
| 138 | interrupts = <GIC_SPI 11 0x4>; | |
| 139 | reg = <0x17826000 0x1000>; | |
| 140 | status = "disabled"; | |
| 141 | }; | |
| 142 | ||
| 143 | frame@17827000 { | |
| 144 | frame-number = <5>; | |
| 145 | interrupts = <GIC_SPI 12 0x4>; | |
| 146 | reg = <0x17827000 0x1000>; | |
| 147 | status = "disabled"; | |
| 148 | }; | |
| 149 | ||
| 150 | frame@17828000 { | |
| 151 | frame-number = <6>; | |
| 152 | interrupts = <GIC_SPI 13 0x4>; | |
| 153 | reg = <0x17828000 0x1000>; | |
| 154 | status = "disabled"; | |
| 155 | }; | |
| 156 | ||
| 157 | frame@17829000 { | |
| 158 | frame-number = <7>; | |
| 159 | interrupts = <GIC_SPI 14 0x4>; | |
| 160 | reg = <0x17829000 0x1000>; | |
| 161 | status = "disabled"; | |
| 162 | }; | |
| 163 | }; | |
| 164 | ||
| 165 | apps_rsc: rsc@17840000 { | |
| 166 | compatible = "qcom,rpmh-rsc"; | |
| 167 | reg = <0x17830000 0x10000>, <0x17840000 0x10000>; | |
| 168 | reg-names = "drv-0", "drv-1"; | |
| 169 | interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>, | |
| 170 | <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>; | |
| 171 | qcom,tcs-offset = <0xd00>; | |
| 172 | qcom,drv-id = <1>; | |
| 173 | qcom,tcs-config = <ACTIVE_TCS 2>, <SLEEP_TCS 2>, | |
| 174 | <WAKE_TCS 2>, <CONTROL_TCS 1>; | |
| 175 | ||
| 176 | rpmhcc: clock-controller { | |
| 177 | compatible = "qcom,sdx55-rpmh-clk"; | |
| 178 | #clock-cells = <1>; | |
| 179 | clock-names = "xo"; | |
| 180 | clocks = <&xo_board>; | |
| 181 | }; | |
| 182 | }; | |
| 183 | }; | |
| 184 | ||
| 185 | timer { | |
| 186 | compatible = "arm,armv7-timer"; | |
| 187 | interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, | |
| 188 | <GIC_PPI 12 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, | |
| 189 | <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, | |
| 190 | <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>; | |
| 191 | clock-frequency = <19200000>; | |
| 192 | }; | |
| 193 | }; |