[linux-2.6-block.git] / arch / arm / boot / dts / qcom-sdx55.dtsi

// SPDX-License-Identifier: BSD-3-Clause
/*
 * SDX55 SoC device tree source
 *
 * Copyright (c) 2018, The Linux Foundation. All rights reserved.
 * Copyright (c) 2020, Linaro Ltd.
 */

#include <dt-bindings/clock/qcom,gcc-sdx55.h>
#include <dt-bindings/clock/qcom,rpmh.h>
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/interconnect/qcom,sdx55.h>
#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/power/qcom-rpmpd.h>
#include <dt-bindings/soc/qcom,rpmh-rsc.h>

/ {
	#address-cells = <1>;
	#size-cells = <1>;
	qcom,msm-id = <357 0x10000>, <368 0x10000>, <418 0x10000>;
	interrupt-parent = <&intc>;

	memory {
		device_type = "memory";
		reg = <0 0>;
	};

	clocks {
		xo_board: xo-board {
			compatible = "fixed-clock";
			#clock-cells = <0>;
			clock-frequency = <38400000>;
			clock-output-names = "xo_board";
		};

		sleep_clk: sleep-clk {
			compatible = "fixed-clock";
			#clock-cells = <0>;
			clock-frequency = <32000>;
		};

		nand_clk_dummy: nand-clk-dummy {
			compatible = "fixed-clock";
			#clock-cells = <0>;
			clock-frequency = <32000>;
		};
	};

	cpus {
		#address-cells = <1>;
		#size-cells = <0>;

		cpu0: cpu@0 {
			device_type = "cpu";
			compatible = "arm,cortex-a7";
			reg = <0x0>;
			enable-method = "psci";
			clocks = <&apcs>;
			power-domains = <&rpmhpd SDX55_CX>;
			power-domain-names = "rpmhpd";
			operating-points-v2 = <&cpu_opp_table>;
		};
	};

	cpu_opp_table: cpu-opp-table {
		compatible = "operating-points-v2";
		opp-shared;

		opp-345600000 {
			opp-hz = /bits/ 64 <345600000>;
			required-opps = <&rpmhpd_opp_low_svs>;
		};

		opp-576000000 {
			opp-hz = /bits/ 64 <576000000>;
			required-opps = <&rpmhpd_opp_svs>;
		};

		opp-1094400000 {
			opp-hz = /bits/ 64 <1094400000>;
			required-opps = <&rpmhpd_opp_nom>;
		};

		opp-1555200000 {
			opp-hz = /bits/ 64 <1555200000>;
			required-opps = <&rpmhpd_opp_turbo>;
		};
	};

	firmware {
		scm {
			compatible = "qcom,scm-sdx55", "qcom,scm";
		};
	};

	psci {
		compatible = "arm,psci-1.0";
		method = "smc";
	};

	reserved-memory {
		#address-cells = <1>;
		#size-cells = <1>;
		ranges;

		hyp_mem: memory@8fc00000 {
			no-map;
			reg = <0x8fc00000 0x80000>;
		};

		ac_db_mem: memory@8fc80000 {
			no-map;
			reg = <0x8fc80000 0x40000>;
		};

		secdata_mem: memory@8fcfd000 {
			no-map;
			reg = <0x8fcfd000 0x1000>;
		};

		sbl_mem: memory@8fd00000 {
			no-map;
			reg = <0x8fd00000 0x100000>;
		};

		aop_image: memory@8fe00000 {
			no-map;
			reg = <0x8fe00000 0x20000>;
		};

		aop_cmd_db: memory@8fe20000 {
			compatible = "qcom,cmd-db";
			reg = <0x8fe20000 0x20000>;
			no-map;
		};

		smem_mem: memory@8fe40000 {
			no-map;
			reg = <0x8fe40000 0xc0000>;
		};

		tz_mem: memory@8ff00000 {
			no-map;
			reg = <0x8ff00000 0x100000>;
		};

		tz_apps_mem: memory@90000000 {
			no-map;
			reg = <0x90000000 0x500000>;
		};
	};

	smem {
		compatible = "qcom,smem";
		memory-region = <&smem_mem>;
		hwlocks = <&tcsr_mutex 3>;
	};

	smp2p-mpss {
		compatible = "qcom,smp2p";
		qcom,smem = <435>, <428>;
		interrupts = <GIC_SPI 113 IRQ_TYPE_EDGE_RISING>;
		mboxes = <&apcs 14>;
		qcom,local-pid = <0>;
		qcom,remote-pid = <1>;

		modem_smp2p_out: master-kernel {
			qcom,entry-name = "master-kernel";
			#qcom,smem-state-cells = <1>;
		};

		modem_smp2p_in: slave-kernel {
			qcom,entry-name = "slave-kernel";
			interrupt-controller;
			#interrupt-cells = <2>;
		};

		ipa_smp2p_out: ipa-ap-to-modem {
			qcom,entry-name = "ipa";
			#qcom,smem-state-cells = <1>;
		};

		ipa_smp2p_in: ipa-modem-to-ap {
			qcom,entry-name = "ipa";
			interrupt-controller;
			#interrupt-cells = <2>;
		};
	};

	soc: soc {
		#address-cells = <1>;
		#size-cells = <1>;
		ranges;
		compatible = "simple-bus";

		gcc: clock-controller@100000 {
			compatible = "qcom,gcc-sdx55";
			reg = <0x100000 0x1f0000>;
			#clock-cells = <1>;
			#reset-cells = <1>;
			#power-domain-cells = <1>;
			clock-names = "bi_tcxo", "sleep_clk";
			clocks = <&rpmhcc RPMH_CXO_CLK>, <&sleep_clk>;
		};

		blsp1_uart3: serial@831000 {
			compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
			reg = <0x00831000 0x200>;
			interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_LOW>;
			clocks = <&gcc 30>,
				 <&gcc 9>;
			clock-names = "core", "iface";
			status = "disabled";
		};

		usb_hsphy: phy@ff4000 {
			compatible = "qcom,usb-snps-hs-7nm-phy";
			reg = <0x00ff4000 0x114>;
			status = "disabled";
			#phy-cells = <0>;

			clocks = <&rpmhcc RPMH_CXO_CLK>;
			clock-names = "ref";

			resets = <&gcc GCC_QUSB2PHY_BCR>;
		};

		usb_qmpphy: phy@ff6000 {
			compatible = "qcom,sdx55-qmp-usb3-uni-phy";
			reg = <0x00ff6000 0x1c0>;
			status = "disabled";
			#address-cells = <1>;
			#size-cells = <1>;
			ranges;

			clocks = <&gcc GCC_USB3_PHY_AUX_CLK>,
				 <&gcc GCC_USB_PHY_CFG_AHB2PHY_CLK>,
				 <&gcc GCC_USB3_PRIM_CLKREF_CLK>;
			clock-names = "aux", "cfg_ahb", "ref";

			resets = <&gcc GCC_USB3PHY_PHY_BCR>,
				 <&gcc GCC_USB3_PHY_BCR>;
			reset-names = "phy", "common";

			usb_ssphy: phy@ff6200 {
				reg = <0x00ff6200 0x170>,
				      <0x00ff6400 0x200>,
				      <0x00ff6800 0x800>;
				#phy-cells = <0>;
				#clock-cells = <0>;
				clocks = <&gcc GCC_USB3_PHY_PIPE_CLK>;
				clock-names = "pipe0";
				clock-output-names = "usb3_uni_phy_pipe_clk_src";
			};
		};

		mc_virt: interconnect@1100000 {
			compatible = "qcom,sdx55-mc-virt";
			reg = <0x01100000 0x400000>;
			#interconnect-cells = <1>;
			qcom,bcm-voters = <&apps_bcm_voter>;
		};

		mem_noc: interconnect@9680000 {
			compatible = "qcom,sdx55-mem-noc";
			reg = <0x09680000 0x40000>;
			#interconnect-cells = <1>;
			qcom,bcm-voters = <&apps_bcm_voter>;
		};

		system_noc: interconnect@162c000 {
			compatible = "qcom,sdx55-system-noc";
			reg = <0x0162c000 0x31200>;
			#interconnect-cells = <1>;
			qcom,bcm-voters = <&apps_bcm_voter>;
		};

		ipa_virt: interconnect@1e00000 {
			compatible = "qcom,sdx55-ipa-virt";
			reg = <0x01e00000 0x100000>;
			#interconnect-cells = <1>;
			qcom,bcm-voters = <&apps_bcm_voter>;
		};

		qpic_bam: dma-controller@1b04000 {
			compatible = "qcom,bam-v1.7.0";
			reg = <0x01b04000 0x1c000>;
			interrupts = <GIC_SPI 135 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&rpmhcc RPMH_QPIC_CLK>;
			clock-names = "bam_clk";
			#dma-cells = <1>;
			qcom,ee = <0>;
			qcom,controlled-remotely;
			status = "disabled";
		};

		qpic_nand: nand-controller@1b30000 {
			compatible = "qcom,sdx55-nand";
			reg = <0x01b30000 0x10000>;
			#address-cells = <1>;
			#size-cells = <0>;
			clocks = <&rpmhcc RPMH_QPIC_CLK>,
				 <&nand_clk_dummy>;
			clock-names = "core", "aon";

			dmas = <&qpic_bam 0>,
			       <&qpic_bam 1>,
			       <&qpic_bam 2>;
			dma-names = "tx", "rx", "cmd";
			status = "disabled";
		};

		pcie0_phy: phy@1c07000 {
			compatible = "qcom,sdx55-qmp-pcie-phy";
			reg = <0x01c07000 0x1c4>;
			#address-cells = <1>;
			#size-cells = <1>;
			ranges;
			clocks = <&gcc GCC_PCIE_AUX_PHY_CLK_SRC>,
				 <&gcc GCC_PCIE_CFG_AHB_CLK>,
				 <&gcc GCC_PCIE_0_CLKREF_CLK>,
				 <&gcc GCC_PCIE_RCHNG_PHY_CLK>;
			clock-names = "aux", "cfg_ahb", "ref", "refgen";

			resets = <&gcc GCC_PCIE_PHY_BCR>;
			reset-names = "phy";

			assigned-clocks = <&gcc GCC_PCIE_RCHNG_PHY_CLK>;
			assigned-clock-rates = <100000000>;

			status = "disabled";

			pcie0_lane: lanes@1c06000 {
				reg = <0x01c06000 0x104>, /* tx0 */
				      <0x01c06200 0x328>, /* rx0 */
				      <0x01c07200 0x1e8>, /* pcs */
				      <0x01c06800 0x104>, /* tx1 */
				      <0x01c06a00 0x328>, /* rx1 */
				      <0x01c07600 0x800>; /* pcs_misc */
				clocks = <&gcc GCC_PCIE_PIPE_CLK>;
				clock-names = "pipe0";

				#phy-cells = <0>;
				clock-output-names = "pcie_pipe_clk";
			};
		};

		ipa: ipa@1e40000 {
			compatible = "qcom,sdx55-ipa";

			iommus = <&apps_smmu 0x5e0 0x0>,
				 <&apps_smmu 0x5e2 0x0>;
			reg = <0x1e40000 0x7000>,
			      <0x1e50000 0x4b20>,
			      <0x1e04000 0x2c000>;
			reg-names = "ipa-reg",
				    "ipa-shared",
				    "gsi";

			interrupts-extended = <&intc GIC_SPI 241 IRQ_TYPE_EDGE_RISING>,
					      <&intc GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>,
					      <&ipa_smp2p_in 0 IRQ_TYPE_EDGE_RISING>,
					      <&ipa_smp2p_in 1 IRQ_TYPE_EDGE_RISING>;
			interrupt-names = "ipa",
					  "gsi",
					  "ipa-clock-query",
					  "ipa-setup-ready";

			clocks = <&rpmhcc RPMH_IPA_CLK>;
			clock-names = "core";

			interconnects = <&system_noc MASTER_IPA &mc_virt SLAVE_EBI_CH0>,
					<&system_noc MASTER_IPA &system_noc SLAVE_OCIMEM>,
					<&mem_noc MASTER_AMPSS_M0 &system_noc SLAVE_IPA_CFG>;
			interconnect-names = "memory",
					     "imem",
					     "config";

			qcom,smem-states = <&ipa_smp2p_out 0>,
					   <&ipa_smp2p_out 1>;
			qcom,smem-state-names = "ipa-clock-enabled-valid",
						"ipa-clock-enabled";

			status = "disabled";
		};

		tcsr_mutex: hwlock@1f40000 {
			compatible = "qcom,tcsr-mutex";
			reg = <0x01f40000 0x40000>;
			#hwlock-cells = <1>;
		};

		tcsr: syscon@1fcb000 {
			compatible = "syscon";
			reg = <0x01fc0000 0x1000>;
		};

		sdhc_1: sdhci@8804000 {
			compatible = "qcom,sdx55-sdhci", "qcom,sdhci-msm-v5";
			reg = <0x08804000 0x1000>;
			interrupts = <GIC_SPI 210 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 227 IRQ_TYPE_LEVEL_HIGH>;
			interrupt-names = "hc_irq", "pwr_irq";
			clocks = <&gcc GCC_SDCC1_AHB_CLK>,
				 <&gcc GCC_SDCC1_APPS_CLK>;
			clock-names = "iface", "core";
			status = "disabled";
		};

		pcie_ep: pcie-ep@40000000 {
			compatible = "qcom,sdx55-pcie-ep";
			reg = <0x01c00000 0x3000>,
			      <0x40000000 0xf1d>,
			      <0x40000f20 0xc8>,
			      <0x40001000 0x1000>,
			      <0x40002000 0x10000>,
			      <0x01c03000 0x3000>;
			reg-names = "parf", "dbi", "elbi", "atu", "addr_space",
				    "mmio";

			qcom,perst-regs = <&tcsr 0xb258 0xb270>;

			clocks = <&gcc GCC_PCIE_AUX_CLK>,
				 <&gcc GCC_PCIE_CFG_AHB_CLK>,
				 <&gcc GCC_PCIE_MSTR_AXI_CLK>,
				 <&gcc GCC_PCIE_SLV_AXI_CLK>,
				 <&gcc GCC_PCIE_SLV_Q2A_AXI_CLK>,
				 <&gcc GCC_PCIE_SLEEP_CLK>,
				 <&gcc GCC_PCIE_0_CLKREF_CLK>;
			clock-names = "aux", "cfg", "bus_master", "bus_slave",
				      "slave_q2a", "sleep", "ref";

			interrupts = <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>;
			interrupt-names = "global", "doorbell";
			reset-gpios = <&tlmm 57 GPIO_ACTIVE_LOW>;
			wake-gpios = <&tlmm 53 GPIO_ACTIVE_LOW>;
			resets = <&gcc GCC_PCIE_BCR>;
			reset-names = "core";
			power-domains = <&gcc PCIE_GDSC>;
			phys = <&pcie0_lane>;
			phy-names = "pciephy";
			max-link-speed = <3>;
			num-lanes = <2>;

			status = "disabled";
		};

		remoteproc_mpss: remoteproc@4080000 {
			compatible = "qcom,sdx55-mpss-pas";
			reg = <0x04080000 0x4040>;

			interrupts-extended = <&intc GIC_SPI 250 IRQ_TYPE_EDGE_RISING>,
					      <&modem_smp2p_in 0 IRQ_TYPE_EDGE_RISING>,
					      <&modem_smp2p_in 1 IRQ_TYPE_EDGE_RISING>,
					      <&modem_smp2p_in 2 IRQ_TYPE_EDGE_RISING>,
					      <&modem_smp2p_in 3 IRQ_TYPE_EDGE_RISING>,
					      <&modem_smp2p_in 7 IRQ_TYPE_EDGE_RISING>;
			interrupt-names = "wdog", "fatal", "ready", "handover",
					  "stop-ack", "shutdown-ack";

			clocks = <&rpmhcc RPMH_CXO_CLK>;
			clock-names = "xo";

			power-domains = <&rpmhpd SDX55_CX>,
					<&rpmhpd SDX55_MSS>;
			power-domain-names = "cx", "mss";

			qcom,smem-states = <&modem_smp2p_out 0>;
			qcom,smem-state-names = "stop";

			status = "disabled";

			glink-edge {
				interrupts = <GIC_SPI 114 IRQ_TYPE_EDGE_RISING>;
				label = "mpss";
				qcom,remote-pid = <1>;
				mboxes = <&apcs 15>;
			};
		};

		usb: usb@a6f8800 {
			compatible = "qcom,sdx55-dwc3", "qcom,dwc3";
			reg = <0x0a6f8800 0x400>;
			status = "disabled";
			#address-cells = <1>;
			#size-cells = <1>;
			ranges;

			clocks = <&gcc GCC_USB30_SLV_AHB_CLK>,
				 <&gcc GCC_USB30_MASTER_CLK>,
				 <&gcc GCC_USB30_MSTR_AXI_CLK>,
				 <&gcc GCC_USB30_MOCK_UTMI_CLK>,
				 <&gcc GCC_USB30_SLEEP_CLK>;
			clock-names = "cfg_noc", "core", "iface", "mock_utmi",
				      "sleep";

			assigned-clocks = <&gcc GCC_USB30_MOCK_UTMI_CLK>,
					  <&gcc GCC_USB30_MASTER_CLK>;
			assigned-clock-rates = <19200000>, <200000000>;

			interrupts = <GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 198 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 158 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 157 IRQ_TYPE_LEVEL_HIGH>;
			interrupt-names = "hs_phy_irq", "ss_phy_irq",
					  "dm_hs_phy_irq", "dp_hs_phy_irq";

			power-domains = <&gcc USB30_GDSC>;

			resets = <&gcc GCC_USB30_BCR>;

			usb_dwc3: dwc3@a600000 {
				compatible = "snps,dwc3";
				reg = <0x0a600000 0xcd00>;
				interrupts = <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>;
				iommus = <&apps_smmu 0x1a0 0x0>;
				snps,dis_u2_susphy_quirk;
				snps,dis_enblslpm_quirk;
				phys = <&usb_hsphy>, <&usb_ssphy>;
				phy-names = "usb2-phy", "usb3-phy";
			};
		};

		pdc: interrupt-controller@b210000 {
			compatible = "qcom,sdx55-pdc", "qcom,pdc";
			reg = <0x0b210000 0x30000>;
			qcom,pdc-ranges = <0 179 52>;
			#interrupt-cells = <3>;
			interrupt-parent = <&intc>;
			interrupt-controller;
		};

		restart@c264000 {
			compatible = "qcom,pshold";
			reg = <0x0c264000 0x1000>;
		};

		spmi_bus: spmi@c440000 {
			compatible = "qcom,spmi-pmic-arb";
			reg = <0x0c440000 0x0000d00>,
			      <0x0c600000 0x2000000>,
			      <0x0e600000 0x0100000>,
			      <0x0e700000 0x00a0000>,
			      <0x0c40a000 0x0000700>;
			reg-names = "core", "chnls", "obsrvr", "intr", "cnfg";
			interrupt-names = "periph_irq";
			interrupts = <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>;
			qcom,ee = <0>;
			qcom,channel = <0>;
			#address-cells = <2>;
			#size-cells = <0>;
			interrupt-controller;
			#interrupt-cells = <4>;
			cell-index = <0>;
		};

		tlmm: pinctrl@f100000 {
			compatible = "qcom,sdx55-pinctrl";
			reg = <0xf100000 0x300000>;
			interrupts = <GIC_SPI 212 IRQ_TYPE_LEVEL_HIGH>;
			gpio-controller;
			#gpio-cells = <2>;
			interrupt-controller;
			#interrupt-cells = <2>;
		};

		imem@1468f000 {
			compatible = "simple-mfd";
			reg = <0x1468f000 0x1000>;

			#address-cells = <1>;
			#size-cells = <1>;

			ranges = <0x0 0x1468f000 0x1000>;

			pil-reloc@94c {
				compatible = "qcom,pil-reloc-info";
				reg = <0x94c 0x200>;
			};
		};

		apps_smmu: iommu@15000000 {
			compatible = "qcom,sdx55-smmu-500", "arm,mmu-500";
			reg = <0x15000000 0x20000>;
			#iommu-cells = <2>;
			#global-interrupts = <1>;
			interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>;
		};

		intc: interrupt-controller@17800000 {
			compatible = "qcom,msm-qgic2";
			interrupt-controller;
			interrupt-parent = <&intc>;
			#interrupt-cells = <3>;
			reg = <0x17800000 0x1000>,
			      <0x17802000 0x1000>;
		};

		a7pll: clock@17808000 {
			compatible = "qcom,sdx55-a7pll";
			reg = <0x17808000 0x1000>;
			clocks = <&rpmhcc RPMH_CXO_CLK>;
			clock-names = "bi_tcxo";
			#clock-cells = <0>;
		};

		apcs: mailbox@17810000 {
			compatible = "qcom,sdx55-apcs-gcc", "syscon";
			reg = <0x17810000 0x2000>;
			#mbox-cells = <1>;
			clocks = <&rpmhcc RPMH_CXO_CLK>, <&a7pll>, <&gcc GPLL0>;
			clock-names = "ref", "pll", "aux";
			#clock-cells = <0>;
		};

		watchdog@17817000 {
			compatible = "qcom,apss-wdt-sdx55", "qcom,kpss-wdt";
			reg = <0x17817000 0x1000>;
			clocks = <&sleep_clk>;
		};

		timer@17820000 {
			#address-cells = <1>;
			#size-cells = <1>;
			ranges;
			compatible = "arm,armv7-timer-mem";
			reg = <0x17820000 0x1000>;
			clock-frequency = <19200000>;

			frame@17821000 {
				frame-number = <0>;
				interrupts = <GIC_SPI 7 0x4>,
					     <GIC_SPI 6 0x4>;
				reg = <0x17821000 0x1000>,
				      <0x17822000 0x1000>;
			};

			frame@17823000 {
				frame-number = <1>;
				interrupts = <GIC_SPI 8 0x4>;
				reg = <0x17823000 0x1000>;
				status = "disabled";
			};

			frame@17824000 {
				frame-number = <2>;
				interrupts = <GIC_SPI 9 0x4>;
				reg = <0x17824000 0x1000>;
				status = "disabled";
			};

			frame@17825000 {
				frame-number = <3>;
				interrupts = <GIC_SPI 10 0x4>;
				reg = <0x17825000 0x1000>;
				status = "disabled";
			};

			frame@17826000 {
				frame-number = <4>;
				interrupts = <GIC_SPI 11 0x4>;
				reg = <0x17826000 0x1000>;
				status = "disabled";
			};

			frame@17827000 {
				frame-number = <5>;
				interrupts = <GIC_SPI 12 0x4>;
				reg = <0x17827000 0x1000>;
				status = "disabled";
			};

			frame@17828000 {
				frame-number = <6>;
				interrupts = <GIC_SPI 13 0x4>;
				reg = <0x17828000 0x1000>;
				status = "disabled";
			};

			frame@17829000 {
				frame-number = <7>;
				interrupts = <GIC_SPI 14 0x4>;
				reg = <0x17829000 0x1000>;
				status = "disabled";
			};
		};

		apps_rsc: rsc@17840000 {
			compatible = "qcom,rpmh-rsc";
			reg = <0x17830000 0x10000>, <0x17840000 0x10000>;
			reg-names = "drv-0", "drv-1";
			interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
			qcom,tcs-offset = <0xd00>;
			qcom,drv-id = <1>;
			qcom,tcs-config = <ACTIVE_TCS  2>, <SLEEP_TCS   2>,
					  <WAKE_TCS    2>, <CONTROL_TCS 1>;

			rpmhcc: clock-controller {
				compatible = "qcom,sdx55-rpmh-clk";
				#clock-cells = <1>;
				clock-names = "xo";
				clocks = <&xo_board>;
			};

			rpmhpd: power-controller {
				compatible = "qcom,sdx55-rpmhpd";
				#power-domain-cells = <1>;
				operating-points-v2 = <&rpmhpd_opp_table>;

				rpmhpd_opp_table: opp-table {
					compatible = "operating-points-v2";

					rpmhpd_opp_ret: opp1 {
						opp-level = <RPMH_REGULATOR_LEVEL_RETENTION>;
					};

					rpmhpd_opp_min_svs: opp2 {
						opp-level = <RPMH_REGULATOR_LEVEL_MIN_SVS>;
					};

					rpmhpd_opp_low_svs: opp3 {
						opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>;
					};

					rpmhpd_opp_svs: opp4 {
						opp-level = <RPMH_REGULATOR_LEVEL_SVS>;
					};

					rpmhpd_opp_svs_l1: opp5 {
						opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>;
					};

					rpmhpd_opp_nom: opp6 {
						opp-level = <RPMH_REGULATOR_LEVEL_NOM>;
					};

					rpmhpd_opp_nom_l1: opp7 {
						opp-level = <RPMH_REGULATOR_LEVEL_NOM_L1>;
					};

					rpmhpd_opp_nom_l2: opp8 {
						opp-level = <RPMH_REGULATOR_LEVEL_NOM_L2>;
					};

					rpmhpd_opp_turbo: opp9 {
						opp-level = <RPMH_REGULATOR_LEVEL_TURBO>;
					};

					rpmhpd_opp_turbo_l1: opp10 {
						opp-level = <RPMH_REGULATOR_LEVEL_TURBO_L1>;
					};
				};
			};

			apps_bcm_voter: bcm_voter {
				compatible = "qcom,bcm-voter";
			};
		};
	};

	timer {
		compatible = "arm,armv7-timer";
		interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
			     <GIC_PPI 12 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
			     <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
			     <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
		clock-frequency = <19200000>;
	};
};
Commit	Line	Data
9d038b2e MS	1	// SPDX-License-Identifier: BSD-3-Clause
	2	/*
	3	* SDX55 SoC device tree source
	4	*
	5	* Copyright (c) 2018, The Linux Foundation. All rights reserved.
	6	* Copyright (c) 2020, Linaro Ltd.
	7	*/
	8
f036549f	9	#include <dt-bindings/clock/qcom,gcc-sdx55.h>
9d038b2e	10	#include <dt-bindings/clock/qcom,rpmh.h>
e6b69813	11	#include <dt-bindings/gpio/gpio.h>
ce5a28d1	12	#include <dt-bindings/interconnect/qcom,sdx55.h>
9d038b2e	13	#include <dt-bindings/interrupt-controller/arm-gic.h>
3cef2d55	14	#include <dt-bindings/power/qcom-rpmpd.h>
9d038b2e MS	15	#include <dt-bindings/soc/qcom,rpmh-rsc.h>
	16
	17	/ {
	18	#address-cells = <1>;
	19	#size-cells = <1>;
	20	qcom,msm-id = <357 0x10000>, <368 0x10000>, <418 0x10000>;
	21	interrupt-parent = <&intc>;
	22
	23	memory {
	24	device_type = "memory";
	25	reg = <0 0>;
	26	};
	27
	28	clocks {
	29	xo_board: xo-board {
	30	compatible = "fixed-clock";
	31	#clock-cells = <0>;
	32	clock-frequency = <38400000>;
	33	clock-output-names = "xo_board";
	34	};
	35
	36	sleep_clk: sleep-clk {
	37	compatible = "fixed-clock";
	38	#clock-cells = <0>;
	39	clock-frequency = <32000>;
	40	};
4bd7bfb4 MS	41
	42	nand_clk_dummy: nand-clk-dummy {
	43	compatible = "fixed-clock";
	44	#clock-cells = <0>;
	45	clock-frequency = <32000>;
	46	};
9d038b2e MS	47	};
	48
	49	cpus {
	50	#address-cells = <1>;
	51	#size-cells = <0>;
	52
	53	cpu0: cpu@0 {
	54	device_type = "cpu";
	55	compatible = "arm,cortex-a7";
	56	reg = <0x0>;
	57	enable-method = "psci";
0ec7bde7 MS	58	clocks = <&apcs>;
	59	power-domains = <&rpmhpd SDX55_CX>;
	60	power-domain-names = "rpmhpd";
	61	operating-points-v2 = <&cpu_opp_table>;
	62	};
	63	};
	64
	65	cpu_opp_table: cpu-opp-table {
	66	compatible = "operating-points-v2";
	67	opp-shared;
	68
	69	opp-345600000 {
	70	opp-hz = /bits/ 64 <345600000>;
	71	required-opps = <&rpmhpd_opp_low_svs>;
	72	};
	73
	74	opp-576000000 {
	75	opp-hz = /bits/ 64 <576000000>;
	76	required-opps = <&rpmhpd_opp_svs>;
	77	};
	78
	79	opp-1094400000 {
	80	opp-hz = /bits/ 64 <1094400000>;
	81	required-opps = <&rpmhpd_opp_nom>;
	82	};
	83
	84	opp-1555200000 {
	85	opp-hz = /bits/ 64 <1555200000>;
	86	required-opps = <&rpmhpd_opp_turbo>;
9d038b2e MS	87	};
	88	};
	89
6bf6655d MS	90	firmware {
	91	scm {
	92	compatible = "qcom,scm-sdx55", "qcom,scm";
	93	};
	94	};
	95
9d038b2e MS	96	psci {
	97	compatible = "arm,psci-1.0";
	98	method = "smc";
	99	};
	100
ec99770d VK	101	reserved-memory {
	102	#address-cells = <1>;
	103	#size-cells = <1>;
	104	ranges;
	105
	106	hyp_mem: memory@8fc00000 {
	107	no-map;
	108	reg = <0x8fc00000 0x80000>;
	109	};
	110
	111	ac_db_mem: memory@8fc80000 {
	112	no-map;
	113	reg = <0x8fc80000 0x40000>;
	114	};
	115
	116	secdata_mem: memory@8fcfd000 {
	117	no-map;
	118	reg = <0x8fcfd000 0x1000>;
	119	};
	120
	121	sbl_mem: memory@8fd00000 {
	122	no-map;
	123	reg = <0x8fd00000 0x100000>;
	124	};
	125
	126	aop_image: memory@8fe00000 {
	127	no-map;
	128	reg = <0x8fe00000 0x20000>;
	129	};
	130
	131	aop_cmd_db: memory@8fe20000 {
	132	compatible = "qcom,cmd-db";
	133	reg = <0x8fe20000 0x20000>;
	134	no-map;
	135	};
	136
	137	smem_mem: memory@8fe40000 {
	138	no-map;
	139	reg = <0x8fe40000 0xc0000>;
	140	};
	141
	142	tz_mem: memory@8ff00000 {
	143	no-map;
	144	reg = <0x8ff00000 0x100000>;
	145	};
	146
9e62ec0e	147	tz_apps_mem: memory@90000000 {
ec99770d VK	148	no-map;
	149	reg = <0x90000000 0x500000>;
	150	};
	151	};
	152
8cf74d05 MS	153	smem {
	154	compatible = "qcom,smem";
	155	memory-region = <&smem_mem>;
	156	hwlocks = <&tcsr_mutex 3>;
	157	};
	158
21e6e1dc MS	159	smp2p-mpss {
	160	compatible = "qcom,smp2p";
	161	qcom,smem = <435>, <428>;
	162	interrupts = <GIC_SPI 113 IRQ_TYPE_EDGE_RISING>;
	163	mboxes = <&apcs 14>;
	164	qcom,local-pid = <0>;
	165	qcom,remote-pid = <1>;
	166
	167	modem_smp2p_out: master-kernel {
	168	qcom,entry-name = "master-kernel";
	169	#qcom,smem-state-cells = <1>;
	170	};
	171
	172	modem_smp2p_in: slave-kernel {
	173	qcom,entry-name = "slave-kernel";
	174	interrupt-controller;
	175	#interrupt-cells = <2>;
	176	};
	177
	178	ipa_smp2p_out: ipa-ap-to-modem {
	179	qcom,entry-name = "ipa";
	180	#qcom,smem-state-cells = <1>;
	181	};
	182
	183	ipa_smp2p_in: ipa-modem-to-ap {
	184	qcom,entry-name = "ipa";
	185	interrupt-controller;
	186	#interrupt-cells = <2>;
	187	};
	188	};
	189
9d038b2e MS	190	soc: soc {
	191	#address-cells = <1>;
	192	#size-cells = <1>;
	193	ranges;
	194	compatible = "simple-bus";
	195
	196	gcc: clock-controller@100000 {
	197	compatible = "qcom,gcc-sdx55";
	198	reg = <0x100000 0x1f0000>;
	199	#clock-cells = <1>;
	200	#reset-cells = <1>;
fea4b410	201	#power-domain-cells = <1>;
9d038b2e MS	202	clock-names = "bi_tcxo", "sleep_clk";
	203	clocks = <&rpmhcc RPMH_CXO_CLK>, <&sleep_clk>;
	204	};
	205
	206	blsp1_uart3: serial@831000 {
	207	compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
	208	reg = <0x00831000 0x200>;
	209	interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_LOW>;
	210	clocks = <&gcc 30>,
	211	<&gcc 9>;
	212	clock-names = "core", "iface";
	213	status = "disabled";
	214	};
	215
fea4b410 MS	216	usb_hsphy: phy@ff4000 {
	217	compatible = "qcom,usb-snps-hs-7nm-phy";
	218	reg = <0x00ff4000 0x114>;
	219	status = "disabled";
	220	#phy-cells = <0>;
	221
	222	clocks = <&rpmhcc RPMH_CXO_CLK>;
	223	clock-names = "ref";
	224
	225	resets = <&gcc GCC_QUSB2PHY_BCR>;
	226	};
	227
	228	usb_qmpphy: phy@ff6000 {
	229	compatible = "qcom,sdx55-qmp-usb3-uni-phy";
	230	reg = <0x00ff6000 0x1c0>;
	231	status = "disabled";
fea4b410 MS	232	#address-cells = <1>;
	233	#size-cells = <1>;
	234	ranges;
	235
	236	clocks = <&gcc GCC_USB3_PHY_AUX_CLK>,
	237	<&gcc GCC_USB_PHY_CFG_AHB2PHY_CLK>,
	238	<&gcc GCC_USB3_PRIM_CLKREF_CLK>;
	239	clock-names = "aux", "cfg_ahb", "ref";
	240
	241	resets = <&gcc GCC_USB3PHY_PHY_BCR>,
	242	<&gcc GCC_USB3_PHY_BCR>;
	243	reset-names = "phy", "common";
	244
	245	usb_ssphy: phy@ff6200 {
	246	reg = <0x00ff6200 0x170>,
	247	<0x00ff6400 0x200>,
	248	<0x00ff6800 0x800>;
	249	#phy-cells = <0>;
	250	#clock-cells = <0>;
	251	clocks = <&gcc GCC_USB3_PHY_PIPE_CLK>;
	252	clock-names = "pipe0";
	253	clock-output-names = "usb3_uni_phy_pipe_clk_src";
	254	};
	255	};
	256
ce5a28d1 MS	257	mc_virt: interconnect@1100000 {
	258	compatible = "qcom,sdx55-mc-virt";
	259	reg = <0x01100000 0x400000>;
	260	#interconnect-cells = <1>;
	261	qcom,bcm-voters = <&apps_bcm_voter>;
	262	};
	263
	264	mem_noc: interconnect@9680000 {
	265	compatible = "qcom,sdx55-mem-noc";
	266	reg = <0x09680000 0x40000>;
	267	#interconnect-cells = <1>;
	268	qcom,bcm-voters = <&apps_bcm_voter>;
	269	};
	270
	271	system_noc: interconnect@162c000 {
	272	compatible = "qcom,sdx55-system-noc";
	273	reg = <0x0162c000 0x31200>;
	274	#interconnect-cells = <1>;
	275	qcom,bcm-voters = <&apps_bcm_voter>;
	276	};
	277
	278	ipa_virt: interconnect@1e00000 {
	279	compatible = "qcom,sdx55-ipa-virt";
	280	reg = <0x01e00000 0x100000>;
	281	#interconnect-cells = <1>;
	282	qcom,bcm-voters = <&apps_bcm_voter>;
	283	};
	284
24709418 MS	285	qpic_bam: dma-controller@1b04000 {
	286	compatible = "qcom,bam-v1.7.0";
	287	reg = <0x01b04000 0x1c000>;
	288	interrupts = <GIC_SPI 135 IRQ_TYPE_LEVEL_HIGH>;
	289	clocks = <&rpmhcc RPMH_QPIC_CLK>;
	290	clock-names = "bam_clk";
	291	#dma-cells = <1>;
	292	qcom,ee = <0>;
	293	qcom,controlled-remotely;
	294	status = "disabled";
	295	};
	296
9e1e00f1	297	qpic_nand: nand-controller@1b30000 {
4bd7bfb4 MS	298	compatible = "qcom,sdx55-nand";
	299	reg = <0x01b30000 0x10000>;
	300	#address-cells = <1>;
	301	#size-cells = <0>;
	302	clocks = <&rpmhcc RPMH_QPIC_CLK>,
	303	<&nand_clk_dummy>;
	304	clock-names = "core", "aon";
	305
	306	dmas = <&qpic_bam 0>,
	307	<&qpic_bam 1>,
	308	<&qpic_bam 2>;
	309	dma-names = "tx", "rx", "cmd";
	310	status = "disabled";
	311	};
	312
254a2758 MS	313	pcie0_phy: phy@1c07000 {
	314	compatible = "qcom,sdx55-qmp-pcie-phy";
	315	reg = <0x01c07000 0x1c4>;
	316	#address-cells = <1>;
	317	#size-cells = <1>;
	318	ranges;
	319	clocks = <&gcc GCC_PCIE_AUX_PHY_CLK_SRC>,
	320	<&gcc GCC_PCIE_CFG_AHB_CLK>,
	321	<&gcc GCC_PCIE_0_CLKREF_CLK>,
	322	<&gcc GCC_PCIE_RCHNG_PHY_CLK>;
	323	clock-names = "aux", "cfg_ahb", "ref", "refgen";
	324
	325	resets = <&gcc GCC_PCIE_PHY_BCR>;
	326	reset-names = "phy";
	327
	328	assigned-clocks = <&gcc GCC_PCIE_RCHNG_PHY_CLK>;
	329	assigned-clock-rates = <100000000>;
	330
	331	status = "disabled";
	332
	333	pcie0_lane: lanes@1c06000 {
	334	reg = <0x01c06000 0x104>, /* tx0 */
	335	<0x01c06200 0x328>, /* rx0 */
	336	<0x01c07200 0x1e8>, /* pcs */
	337	<0x01c06800 0x104>, /* tx1 */
	338	<0x01c06a00 0x328>, /* rx1 */
	339	<0x01c07600 0x800>; /* pcs_misc */
	340	clocks = <&gcc GCC_PCIE_PIPE_CLK>;
	341	clock-names = "pipe0";
	342
	343	#phy-cells = <0>;
	344	clock-output-names = "pcie_pipe_clk";
	345	};
	346	};
	347
06ad53ef AE	348	ipa: ipa@1e40000 {
	349	compatible = "qcom,sdx55-ipa";
	350
	351	iommus = <&apps_smmu 0x5e0 0x0>,
	352	<&apps_smmu 0x5e2 0x0>;
	353	reg = <0x1e40000 0x7000>,
	354	<0x1e50000 0x4b20>,
	355	<0x1e04000 0x2c000>;
	356	reg-names = "ipa-reg",
	357	"ipa-shared",
	358	"gsi";
	359
	360	interrupts-extended = <&intc GIC_SPI 241 IRQ_TYPE_EDGE_RISING>,
	361	<&intc GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>,
	362	<&ipa_smp2p_in 0 IRQ_TYPE_EDGE_RISING>,
	363	<&ipa_smp2p_in 1 IRQ_TYPE_EDGE_RISING>;
	364	interrupt-names = "ipa",
	365	"gsi",
	366	"ipa-clock-query",
	367	"ipa-setup-ready";
	368
	369	clocks = <&rpmhcc RPMH_IPA_CLK>;
	370	clock-names = "core";
	371
c0d6316c	372	interconnects = <&system_noc MASTER_IPA &mc_virt SLAVE_EBI_CH0>,
06ad53ef AE	373	<&system_noc MASTER_IPA &system_noc SLAVE_OCIMEM>,
06ad53ef AE	374	<&mem_noc MASTER_AMPSS_M0 &system_noc SLAVE_IPA_CFG>;
c0d6316c	375	interconnect-names = "memory",
06ad53ef AE	376	"imem",
	377	"config";
	378
	379	qcom,smem-states = <&ipa_smp2p_out 0>,
	380	<&ipa_smp2p_out 1>;
	381	qcom,smem-state-names = "ipa-clock-enabled-valid",
	382	"ipa-clock-enabled";
	383
	384	status = "disabled";
	385	};
	386
985eef1d MS	387	tcsr_mutex: hwlock@1f40000 {
	388	compatible = "qcom,tcsr-mutex";
	389	reg = <0x01f40000 0x40000>;
	390	#hwlock-cells = <1>;
	391	};
	392
e6b69813 MS	393	tcsr: syscon@1fcb000 {
	394	compatible = "syscon";
	395	reg = <0x01fc0000 0x1000>;
	396	};
	397
f036549f MS	398	sdhc_1: sdhci@8804000 {
	399	compatible = "qcom,sdx55-sdhci", "qcom,sdhci-msm-v5";
	400	reg = <0x08804000 0x1000>;
	401	interrupts = <GIC_SPI 210 IRQ_TYPE_LEVEL_HIGH>,
	402	<GIC_SPI 227 IRQ_TYPE_LEVEL_HIGH>;
	403	interrupt-names = "hc_irq", "pwr_irq";
	404	clocks = <&gcc GCC_SDCC1_AHB_CLK>,
	405	<&gcc GCC_SDCC1_APPS_CLK>;
	406	clock-names = "iface", "core";
	407	status = "disabled";
	408	};
	409
e6b69813 MS	410	pcie_ep: pcie-ep@40000000 {
	411	compatible = "qcom,sdx55-pcie-ep";
	412	reg = <0x01c00000 0x3000>,
	413	<0x40000000 0xf1d>,
	414	<0x40000f20 0xc8>,
	415	<0x40001000 0x1000>,
	416	<0x40002000 0x10000>,
	417	<0x01c03000 0x3000>;
	418	reg-names = "parf", "dbi", "elbi", "atu", "addr_space",
	419	"mmio";
	420
	421	qcom,perst-regs = <&tcsr 0xb258 0xb270>;
	422
	423	clocks = <&gcc GCC_PCIE_AUX_CLK>,
	424	<&gcc GCC_PCIE_CFG_AHB_CLK>,
	425	<&gcc GCC_PCIE_MSTR_AXI_CLK>,
	426	<&gcc GCC_PCIE_SLV_AXI_CLK>,
	427	<&gcc GCC_PCIE_SLV_Q2A_AXI_CLK>,
	428	<&gcc GCC_PCIE_SLEEP_CLK>,
	429	<&gcc GCC_PCIE_0_CLKREF_CLK>;
	430	clock-names = "aux", "cfg", "bus_master", "bus_slave",
	431	"slave_q2a", "sleep", "ref";
	432
	433	interrupts = <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>,
	434	<GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>;
	435	interrupt-names = "global", "doorbell";
	436	reset-gpios = <&tlmm 57 GPIO_ACTIVE_LOW>;
	437	wake-gpios = <&tlmm 53 GPIO_ACTIVE_LOW>;
	438	resets = <&gcc GCC_PCIE_BCR>;
	439	reset-names = "core";
	440	power-domains = <&gcc PCIE_GDSC>;
	441	phys = <&pcie0_lane>;
	442	phy-names = "pciephy";
	443	max-link-speed = <3>;
	444	num-lanes = <2>;
	445
	446	status = "disabled";
	447	};
	448
67b4744a MS	449	remoteproc_mpss: remoteproc@4080000 {
	450	compatible = "qcom,sdx55-mpss-pas";
	451	reg = <0x04080000 0x4040>;
	452
	453	interrupts-extended = <&intc GIC_SPI 250 IRQ_TYPE_EDGE_RISING>,
	454	<&modem_smp2p_in 0 IRQ_TYPE_EDGE_RISING>,
	455	<&modem_smp2p_in 1 IRQ_TYPE_EDGE_RISING>,
	456	<&modem_smp2p_in 2 IRQ_TYPE_EDGE_RISING>,
	457	<&modem_smp2p_in 3 IRQ_TYPE_EDGE_RISING>,
	458	<&modem_smp2p_in 7 IRQ_TYPE_EDGE_RISING>;
	459	interrupt-names = "wdog", "fatal", "ready", "handover",
	460	"stop-ack", "shutdown-ack";
	461
	462	clocks = <&rpmhcc RPMH_CXO_CLK>;
	463	clock-names = "xo";
	464
	465	power-domains = <&rpmhpd SDX55_CX>,
	466	<&rpmhpd SDX55_MSS>;
	467	power-domain-names = "cx", "mss";
	468
	469	qcom,smem-states = <&modem_smp2p_out 0>;
	470	qcom,smem-state-names = "stop";
	471
	472	status = "disabled";
	473
	474	glink-edge {
	475	interrupts = <GIC_SPI 114 IRQ_TYPE_EDGE_RISING>;
	476	label = "mpss";
	477	qcom,remote-pid = <1>;
	478	mboxes = <&apcs 15>;
	479	};
	480	};
	481
fea4b410 MS	482	usb: usb@a6f8800 {
	483	compatible = "qcom,sdx55-dwc3", "qcom,dwc3";
	484	reg = <0x0a6f8800 0x400>;
	485	status = "disabled";
	486	#address-cells = <1>;
	487	#size-cells = <1>;
	488	ranges;
	489
	490	clocks = <&gcc GCC_USB30_SLV_AHB_CLK>,
	491	<&gcc GCC_USB30_MASTER_CLK>,
	492	<&gcc GCC_USB30_MSTR_AXI_CLK>,
	493	<&gcc GCC_USB30_MOCK_UTMI_CLK>,
	494	<&gcc GCC_USB30_SLEEP_CLK>;
	495	clock-names = "cfg_noc", "core", "iface", "mock_utmi",
	496	"sleep";
	497
	498	assigned-clocks = <&gcc GCC_USB30_MOCK_UTMI_CLK>,
	499	<&gcc GCC_USB30_MASTER_CLK>;
	500	assigned-clock-rates = <19200000>, <200000000>;
	501
	502	interrupts = <GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>,
	503	<GIC_SPI 198 IRQ_TYPE_LEVEL_HIGH>,
	504	<GIC_SPI 158 IRQ_TYPE_LEVEL_HIGH>,
	505	<GIC_SPI 157 IRQ_TYPE_LEVEL_HIGH>;
	506	interrupt-names = "hs_phy_irq", "ss_phy_irq",
	507	"dm_hs_phy_irq", "dp_hs_phy_irq";
	508
	509	power-domains = <&gcc USB30_GDSC>;
	510
	511	resets = <&gcc GCC_USB30_BCR>;
	512
	513	usb_dwc3: dwc3@a600000 {
	514	compatible = "snps,dwc3";
	515	reg = <0x0a600000 0xcd00>;
	516	interrupts = <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>;
	517	iommus = <&apps_smmu 0x1a0 0x0>;
	518	snps,dis_u2_susphy_quirk;
	519	snps,dis_enblslpm_quirk;
	520	phys = <&usb_hsphy>, <&usb_ssphy>;
	521	phy-names = "usb2-phy", "usb3-phy";
	522	};
	523	};
	524
9d038b2e MS	525	pdc: interrupt-controller@b210000 {
	526	compatible = "qcom,sdx55-pdc", "qcom,pdc";
	527	reg = <0x0b210000 0x30000>;
	528	qcom,pdc-ranges = <0 179 52>;
	529	#interrupt-cells = <3>;
	530	interrupt-parent = <&intc>;
	531	interrupt-controller;
	532	};
	533
c4aa86f0 MS	534	restart@c264000 {
	535	compatible = "qcom,pshold";
	536	reg = <0x0c264000 0x1000>;
	537	};
	538
5035460b	539	spmi_bus: spmi@c440000 {
3b6785ed VK	540	compatible = "qcom,spmi-pmic-arb";
	541	reg = <0x0c440000 0x0000d00>,
	542	<0x0c600000 0x2000000>,
	543	<0x0e600000 0x0100000>,
	544	<0x0e700000 0x00a0000>,
	545	<0x0c40a000 0x0000700>;
	546	reg-names = "core", "chnls", "obsrvr", "intr", "cnfg";
	547	interrupt-names = "periph_irq";
	548	interrupts = <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>;
	549	qcom,ee = <0>;
	550	qcom,channel = <0>;
	551	#address-cells = <2>;
	552	#size-cells = <0>;
	553	interrupt-controller;
	554	#interrupt-cells = <4>;
	555	cell-index = <0>;
	556	};
	557
dea0e9bc VK	558	tlmm: pinctrl@f100000 {
	559	compatible = "qcom,sdx55-pinctrl";
	560	reg = <0xf100000 0x300000>;
	561	interrupts = <GIC_SPI 212 IRQ_TYPE_LEVEL_HIGH>;
	562	gpio-controller;
	563	#gpio-cells = <2>;
	564	interrupt-controller;
	565	#interrupt-cells = <2>;
	566	};
	567
9b7069ed MS	568	imem@1468f000 {
	569	compatible = "simple-mfd";
	570	reg = <0x1468f000 0x1000>;
	571
	572	#address-cells = <1>;
	573	#size-cells = <1>;
	574
	575	ranges = <0x0 0x1468f000 0x1000>;
	576
	577	pil-reloc@94c {
	578	compatible = "qcom,pil-reloc-info";
	579	reg = <0x94c 0x200>;
	580	};
	581	};
	582
a2bdfdfb BA	583	apps_smmu: iommu@15000000 {
	584	compatible = "qcom,sdx55-smmu-500", "arm,mmu-500";
	585	reg = <0x15000000 0x20000>;
	586	#iommu-cells = <2>;
	587	#global-interrupts = <1>;
	588	interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>,
	589	<GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>,
	590	<GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>,
	591	<GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>,
	592	<GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>,
	593	<GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>,
	594	<GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>,
	595	<GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>,
	596	<GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>,
	597	<GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>,
	598	<GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>,
	599	<GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>,
	600	<GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>,
	601	<GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>,
	602	<GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>,
	603	<GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>,
	604	<GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>;
	605	};
	606
9d038b2e MS	607	intc: interrupt-controller@17800000 {
	608	compatible = "qcom,msm-qgic2";
	609	interrupt-controller;
	610	interrupt-parent = <&intc>;
	611	#interrupt-cells = <3>;
	612	reg = <0x17800000 0x1000>,
	613	<0x17802000 0x1000>;
	614	};
	615
37f0f245 MS	616	a7pll: clock@17808000 {
	617	compatible = "qcom,sdx55-a7pll";
	618	reg = <0x17808000 0x1000>;
	619	clocks = <&rpmhcc RPMH_CXO_CLK>;
	620	clock-names = "bi_tcxo";
	621	#clock-cells = <0>;
	622	};
	623
8e3d9a7c MS	624	apcs: mailbox@17810000 {
	625	compatible = "qcom,sdx55-apcs-gcc", "syscon";
	626	reg = <0x17810000 0x2000>;
	627	#mbox-cells = <1>;
	628	clocks = <&rpmhcc RPMH_CXO_CLK>, <&a7pll>, <&gcc GPLL0>;
	629	clock-names = "ref", "pll", "aux";
	630	#clock-cells = <0>;
	631	};
	632
b1d20460 MS	633	watchdog@17817000 {
	634	compatible = "qcom,apss-wdt-sdx55", "qcom,kpss-wdt";
	635	reg = <0x17817000 0x1000>;
	636	clocks = <&sleep_clk>;
	637	};
	638
9d038b2e MS	639	timer@17820000 {
	640	#address-cells = <1>;
	641	#size-cells = <1>;
	642	ranges;
	643	compatible = "arm,armv7-timer-mem";
	644	reg = <0x17820000 0x1000>;
	645	clock-frequency = <19200000>;
	646
	647	frame@17821000 {
	648	frame-number = <0>;
	649	interrupts = <GIC_SPI 7 0x4>,
	650	<GIC_SPI 6 0x4>;
	651	reg = <0x17821000 0x1000>,
	652	<0x17822000 0x1000>;
	653	};
	654
	655	frame@17823000 {
	656	frame-number = <1>;
	657	interrupts = <GIC_SPI 8 0x4>;
	658	reg = <0x17823000 0x1000>;
	659	status = "disabled";
	660	};
	661
	662	frame@17824000 {
	663	frame-number = <2>;
	664	interrupts = <GIC_SPI 9 0x4>;
	665	reg = <0x17824000 0x1000>;
	666	status = "disabled";
	667	};
	668
	669	frame@17825000 {
	670	frame-number = <3>;
	671	interrupts = <GIC_SPI 10 0x4>;
	672	reg = <0x17825000 0x1000>;
	673	status = "disabled";
	674	};
	675
	676	frame@17826000 {
	677	frame-number = <4>;
	678	interrupts = <GIC_SPI 11 0x4>;
	679	reg = <0x17826000 0x1000>;
	680	status = "disabled";
	681	};
	682
	683	frame@17827000 {
	684	frame-number = <5>;
	685	interrupts = <GIC_SPI 12 0x4>;
	686	reg = <0x17827000 0x1000>;
	687	status = "disabled";
	688	};
	689
	690	frame@17828000 {
	691	frame-number = <6>;
	692	interrupts = <GIC_SPI 13 0x4>;
	693	reg = <0x17828000 0x1000>;
	694	status = "disabled";
	695	};
	696
	697	frame@17829000 {
	698	frame-number = <7>;
	699	interrupts = <GIC_SPI 14 0x4>;
	700	reg = <0x17829000 0x1000>;
	701	status = "disabled";
	702	};
703	};
704
705	apps_rsc: rsc@17840000 {
706	compatible = "qcom,rpmh-rsc";
707	reg = <0x17830000 0x10000>, <0x17840000 0x10000>;
708	reg-names = "drv-0", "drv-1";
709	interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>,
710	<GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
711	qcom,tcs-offset = <0xd00>;
712	qcom,drv-id = <1>;
713	qcom,tcs-config = <ACTIVE_TCS 2>, <SLEEP_TCS 2>,
714	<WAKE_TCS 2>, <CONTROL_TCS 1>;
715
716	rpmhcc: clock-controller {
717	compatible = "qcom,sdx55-rpmh-clk";
718	#clock-cells = <1>;
719	clock-names = "xo";
720	clocks = <&xo_board>;
721	};
3cef2d55 VK	722
	723	rpmhpd: power-controller {
	724	compatible = "qcom,sdx55-rpmhpd";
	725	#power-domain-cells = <1>;
	726	operating-points-v2 = <&rpmhpd_opp_table>;
	727
	728	rpmhpd_opp_table: opp-table {
	729	compatible = "operating-points-v2";
	730
	731	rpmhpd_opp_ret: opp1 {
	732	opp-level = <RPMH_REGULATOR_LEVEL_RETENTION>;
	733	};
	734
	735	rpmhpd_opp_min_svs: opp2 {
	736	opp-level = <RPMH_REGULATOR_LEVEL_MIN_SVS>;
	737	};
	738
	739	rpmhpd_opp_low_svs: opp3 {
	740	opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>;
	741	};
	742
	743	rpmhpd_opp_svs: opp4 {
	744	opp-level = <RPMH_REGULATOR_LEVEL_SVS>;
	745	};
	746
	747	rpmhpd_opp_svs_l1: opp5 {
	748	opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>;
	749	};
	750
	751	rpmhpd_opp_nom: opp6 {
	752	opp-level = <RPMH_REGULATOR_LEVEL_NOM>;
	753	};
	754
	755	rpmhpd_opp_nom_l1: opp7 {
	756	opp-level = <RPMH_REGULATOR_LEVEL_NOM_L1>;
	757	};
	758
	759	rpmhpd_opp_nom_l2: opp8 {
	760	opp-level = <RPMH_REGULATOR_LEVEL_NOM_L2>;
	761	};
	762
	763	rpmhpd_opp_turbo: opp9 {
	764	opp-level = <RPMH_REGULATOR_LEVEL_TURBO>;
	765	};
	766
	767	rpmhpd_opp_turbo_l1: opp10 {
	768	opp-level = <RPMH_REGULATOR_LEVEL_TURBO_L1>;
	769	};
	770	};
	771	};
ce5a28d1 MS	772
	773	apps_bcm_voter: bcm_voter {
	774	compatible = "qcom,bcm-voter";
	775	};
9d038b2e MS	776	};
	777	};
	778
	779	timer {
	780	compatible = "arm,armv7-timer";
	781	interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) \| IRQ_TYPE_LEVEL_LOW)>,
	782	<GIC_PPI 12 (GIC_CPU_MASK_SIMPLE(4) \| IRQ_TYPE_LEVEL_LOW)>,
	783	<GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) \| IRQ_TYPE_LEVEL_LOW)>,
	784	<GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) \| IRQ_TYPE_LEVEL_LOW)>;
	785	clock-frequency = <19200000>;
	786	};
	787	};