projects / linux-block.git / blame
| Commit | Line | Data |
|---|---|---|
| b2441318 | 1 | // SPDX-License-Identifier: GPL-2.0 |
| 2aec37c6 RV |
2 | /dts-v1/; |
| 3 | ||
| d44cbb1e | 4 | #include <dt-bindings/interrupt-controller/arm-gic.h> |
| 3933d267 | 5 | #include <dt-bindings/clock/qcom,gcc-msm8974.h> |
| 9db9559c | 6 | #include <dt-bindings/clock/qcom,rpmcc.h> |
| 4ac5a200 | 7 | #include <dt-bindings/reset/qcom,gcc-msm8974.h> |
| 73bae19c | 8 | #include <dt-bindings/gpio/gpio.h> |
| bf7f6b04 | 9 | #include "skeleton.dtsi" |
| 3933d267 | 10 | |
| 2aec37c6 RV |
11 | / { |
| 12 | model = "Qualcomm MSM8974"; | |
| 13 | compatible = "qcom,msm8974"; | |
| 14 | interrupt-parent = <&intc>; | |
| 15 | ||
| 6297c4b2 BA |
16 | reserved-memory { |
| 17 | #address-cells = <1>; | |
| 18 | #size-cells = <1>; | |
| 19 | ranges; | |
| 20 | ||
| 8dccafaa | 21 | mpss@8000000 { |
| ca3971cf BA |
22 | reg = <0x08000000 0x5100000>; |
| 23 | no-map; | |
| 24 | }; | |
| 25 | ||
| 8dccafaa | 26 | mba@d100000 { |
| ca3971cf BA |
27 | reg = <0x0d100000 0x100000>; |
| 28 | no-map; | |
| 29 | }; | |
| 30 | ||
| 8dccafaa | 31 | reserved@d200000 { |
| ca3971cf BA |
32 | reg = <0x0d200000 0xa00000>; |
| 33 | no-map; | |
| 34 | }; | |
| 35 | ||
| 8dccafaa | 36 | adsp_region: adsp@dc00000 { |
| ca3971cf BA |
37 | reg = <0x0dc00000 0x1900000>; |
| 38 | no-map; | |
| 39 | }; | |
| 40 | ||
| 8dccafaa | 41 | venus@f500000 { |
| ca3971cf BA |
42 | reg = <0x0f500000 0x500000>; |
| 43 | no-map; | |
| 44 | }; | |
| 45 | ||
| 6297c4b2 BA |
46 | smem_region: smem@fa00000 { |
| 47 | reg = <0xfa00000 0x200000>; | |
| 48 | no-map; | |
| 49 | }; | |
| ca3971cf | 50 | |
| 8dccafaa | 51 | tz@fc00000 { |
| ca3971cf BA |
52 | reg = <0x0fc00000 0x160000>; |
| 53 | no-map; | |
| 54 | }; | |
| 55 | ||
| 8dccafaa | 56 | rfsa@fd60000 { |
| 97311198 BA |
57 | reg = <0x0fd60000 0x20000>; |
| 58 | no-map; | |
| 59 | }; | |
| 60 | ||
| 8dccafaa | 61 | rmtfs@fd80000 { |
| 97311198 | 62 | reg = <0x0fd80000 0x180000>; |
| ca3971cf BA |
63 | no-map; |
| 64 | }; | |
| 6297c4b2 BA |
65 | }; |
| 66 | ||
| 2ab27991 RV |
67 | cpus { |
| 68 | #address-cells = <1>; | |
| 69 | #size-cells = <0>; | |
| b0a627b4 | 70 | interrupts = <GIC_PPI 9 0xf04>; |
| 2ab27991 | 71 | |
| 1e20223d | 72 | CPU0: cpu@0 { |
| ba08220a KG |
73 | compatible = "qcom,krait"; |
| 74 | enable-method = "qcom,kpss-acc-v2"; | |
| 2ab27991 RV |
75 | device_type = "cpu"; |
| 76 | reg = <0>; | |
| 77 | next-level-cache = <&L2>; | |
| 78 | qcom,acc = <&acc0>; | |
| 8c76a638 | 79 | qcom,saw = <&saw0>; |
| d596d620 | 80 | cpu-idle-states = <&CPU_SPC>; |
| 2ab27991 RV |
81 | }; |
| 82 | ||
| 1e20223d | 83 | CPU1: cpu@1 { |
| ba08220a KG |
84 | compatible = "qcom,krait"; |
| 85 | enable-method = "qcom,kpss-acc-v2"; | |
| 2ab27991 RV |
86 | device_type = "cpu"; |
| 87 | reg = <1>; | |
| 88 | next-level-cache = <&L2>; | |
| 89 | qcom,acc = <&acc1>; | |
| 8c76a638 | 90 | qcom,saw = <&saw1>; |
| d596d620 | 91 | cpu-idle-states = <&CPU_SPC>; |
| 2ab27991 RV |
92 | }; |
| 93 | ||
| 1e20223d | 94 | CPU2: cpu@2 { |
| ba08220a KG |
95 | compatible = "qcom,krait"; |
| 96 | enable-method = "qcom,kpss-acc-v2"; | |
| 2ab27991 RV |
97 | device_type = "cpu"; |
| 98 | reg = <2>; | |
| 99 | next-level-cache = <&L2>; | |
| 100 | qcom,acc = <&acc2>; | |
| 8c76a638 | 101 | qcom,saw = <&saw2>; |
| d596d620 | 102 | cpu-idle-states = <&CPU_SPC>; |
| 2ab27991 RV |
103 | }; |
| 104 | ||
| 1e20223d | 105 | CPU3: cpu@3 { |
| ba08220a KG |
106 | compatible = "qcom,krait"; |
| 107 | enable-method = "qcom,kpss-acc-v2"; | |
| 2ab27991 RV |
108 | device_type = "cpu"; |
| 109 | reg = <3>; | |
| 110 | next-level-cache = <&L2>; | |
| 111 | qcom,acc = <&acc3>; | |
| 8c76a638 | 112 | qcom,saw = <&saw3>; |
| d596d620 | 113 | cpu-idle-states = <&CPU_SPC>; |
| 2ab27991 RV |
114 | }; |
| 115 | ||
| 116 | L2: l2-cache { | |
| 117 | compatible = "cache"; | |
| 118 | cache-level = <2>; | |
| 2ab27991 RV |
119 | qcom,saw = <&saw_l2>; |
| 120 | }; | |
| d596d620 LI |
121 | |
| 122 | idle-states { | |
| 123 | CPU_SPC: spc { | |
| 124 | compatible = "qcom,idle-state-spc", | |
| 125 | "arm,idle-state"; | |
| 126 | entry-latency-us = <150>; | |
| 127 | exit-latency-us = <200>; | |
| 128 | min-residency-us = <2000>; | |
| 129 | }; | |
| 130 | }; | |
| 2ab27991 RV |
131 | }; |
| 132 | ||
| c59ffb51 RN |
133 | thermal-zones { |
| 134 | cpu-thermal0 { | |
| 135 | polling-delay-passive = <250>; | |
| 136 | polling-delay = <1000>; | |
| 137 | ||
| 138 | thermal-sensors = <&tsens 5>; | |
| 139 | ||
| 140 | trips { | |
| 141 | cpu_alert0: trip0 { | |
| 142 | temperature = <75000>; | |
| 143 | hysteresis = <2000>; | |
| 144 | type = "passive"; | |
| 145 | }; | |
| 146 | cpu_crit0: trip1 { | |
| 147 | temperature = <110000>; | |
| 148 | hysteresis = <2000>; | |
| 149 | type = "critical"; | |
| 150 | }; | |
| 151 | }; | |
| 152 | }; | |
| 153 | ||
| 154 | cpu-thermal1 { | |
| 155 | polling-delay-passive = <250>; | |
| 156 | polling-delay = <1000>; | |
| 157 | ||
| 158 | thermal-sensors = <&tsens 6>; | |
| 159 | ||
| 160 | trips { | |
| 161 | cpu_alert1: trip0 { | |
| 162 | temperature = <75000>; | |
| 163 | hysteresis = <2000>; | |
| 164 | type = "passive"; | |
| 165 | }; | |
| 166 | cpu_crit1: trip1 { | |
| 167 | temperature = <110000>; | |
| 168 | hysteresis = <2000>; | |
| 169 | type = "critical"; | |
| 170 | }; | |
| 171 | }; | |
| 172 | }; | |
| 173 | ||
| 174 | cpu-thermal2 { | |
| 175 | polling-delay-passive = <250>; | |
| 176 | polling-delay = <1000>; | |
| 177 | ||
| 178 | thermal-sensors = <&tsens 7>; | |
| 179 | ||
| 180 | trips { | |
| 181 | cpu_alert2: trip0 { | |
| 182 | temperature = <75000>; | |
| 183 | hysteresis = <2000>; | |
| 184 | type = "passive"; | |
| 185 | }; | |
| 186 | cpu_crit2: trip1 { | |
| 187 | temperature = <110000>; | |
| 188 | hysteresis = <2000>; | |
| 189 | type = "critical"; | |
| 190 | }; | |
| 191 | }; | |
| 192 | }; | |
| 193 | ||
| 194 | cpu-thermal3 { | |
| 195 | polling-delay-passive = <250>; | |
| 196 | polling-delay = <1000>; | |
| 197 | ||
| 198 | thermal-sensors = <&tsens 8>; | |
| 199 | ||
| 200 | trips { | |
| 201 | cpu_alert3: trip0 { | |
| 202 | temperature = <75000>; | |
| 203 | hysteresis = <2000>; | |
| 204 | type = "passive"; | |
| 205 | }; | |
| 206 | cpu_crit3: trip1 { | |
| 207 | temperature = <110000>; | |
| 208 | hysteresis = <2000>; | |
| 209 | type = "critical"; | |
| 210 | }; | |
| 211 | }; | |
| 212 | }; | |
| 213 | }; | |
| 214 | ||
| 3bff5474 SB |
215 | cpu-pmu { |
| 216 | compatible = "qcom,krait-pmu"; | |
| b0a627b4 | 217 | interrupts = <GIC_PPI 7 0xf04>; |
| 3bff5474 SB |
218 | }; |
| 219 | ||
| 30fc4212 | 220 | clocks { |
| a91b2e69 | 221 | xo_board: xo_board { |
| 30fc4212 SB |
222 | compatible = "fixed-clock"; |
| 223 | #clock-cells = <0>; | |
| 224 | clock-frequency = <19200000>; | |
| 225 | }; | |
| 226 | ||
| a91b2e69 | 227 | sleep_clk: sleep_clk { |
| 30fc4212 SB |
228 | compatible = "fixed-clock"; |
| 229 | #clock-cells = <0>; | |
| 230 | clock-frequency = <32768>; | |
| 231 | }; | |
| 232 | }; | |
| 233 | ||
| ba08220a KG |
234 | timer { |
| 235 | compatible = "arm,armv7-timer"; | |
| b0a627b4 FR |
236 | interrupts = <GIC_PPI 2 0xf08>, |
| 237 | <GIC_PPI 3 0xf08>, | |
| 238 | <GIC_PPI 4 0xf08>, | |
| 239 | <GIC_PPI 1 0xf08>; | |
| ba08220a KG |
240 | clock-frequency = <19200000>; |
| 241 | }; | |
| 242 | ||
| 6f04d7c5 BA |
243 | adsp-pil { |
| 244 | compatible = "qcom,msm8974-adsp-pil"; | |
| 245 | ||
| 12d2de2e | 246 | interrupts-extended = <&intc GIC_SPI 162 IRQ_TYPE_EDGE_RISING>, |
| 6f04d7c5 BA |
247 | <&adsp_smp2p_in 0 IRQ_TYPE_EDGE_RISING>, |
| 248 | <&adsp_smp2p_in 1 IRQ_TYPE_EDGE_RISING>, | |
| 249 | <&adsp_smp2p_in 2 IRQ_TYPE_EDGE_RISING>, | |
| 250 | <&adsp_smp2p_in 3 IRQ_TYPE_EDGE_RISING>; | |
| 251 | interrupt-names = "wdog", "fatal", "ready", "handover", "stop-ack"; | |
| 252 | ||
| 253 | cx-supply = <&pm8841_s2>; | |
| 254 | ||
| 4d931755 JN |
255 | clocks = <&xo_board>; |
| 256 | clock-names = "xo"; | |
| 257 | ||
| 6f04d7c5 BA |
258 | memory-region = <&adsp_region>; |
| 259 | ||
| 260 | qcom,smem-states = <&adsp_smp2p_out 0>; | |
| 261 | qcom,smem-state-names = "stop"; | |
| 262 | }; | |
| 263 | ||
| d0bfd7c9 SB |
264 | smem { |
| 265 | compatible = "qcom,smem"; | |
| 266 | ||
| 267 | memory-region = <&smem_region>; | |
| 268 | qcom,rpm-msg-ram = <&rpm_msg_ram>; | |
| 269 | ||
| 270 | hwlocks = <&tcsr_mutex 3>; | |
| 271 | }; | |
| 272 | ||
| 3028cbab BA |
273 | smp2p-adsp { |
| 274 | compatible = "qcom,smp2p"; | |
| 275 | qcom,smem = <443>, <429>; | |
| 276 | ||
| 277 | interrupt-parent = <&intc>; | |
| 12d2de2e | 278 | interrupts = <GIC_SPI 158 IRQ_TYPE_EDGE_RISING>; |
| 3028cbab BA |
279 | |
| 280 | qcom,ipc = <&apcs 8 10>; | |
| 281 | ||
| 282 | qcom,local-pid = <0>; | |
| 283 | qcom,remote-pid = <2>; | |
| 284 | ||
| 285 | adsp_smp2p_out: master-kernel { | |
| 286 | qcom,entry-name = "master-kernel"; | |
| 287 | #qcom,smem-state-cells = <1>; | |
| 288 | }; | |
| 289 | ||
| 290 | adsp_smp2p_in: slave-kernel { | |
| 291 | qcom,entry-name = "slave-kernel"; | |
| 292 | ||
| 293 | interrupt-controller; | |
| 294 | #interrupt-cells = <2>; | |
| 295 | }; | |
| 296 | }; | |
| 297 | ||
| 5d3178c8 BA |
298 | smp2p-modem { |
| 299 | compatible = "qcom,smp2p"; | |
| 300 | qcom,smem = <435>, <428>; | |
| 301 | ||
| 302 | interrupt-parent = <&intc>; | |
| 12d2de2e | 303 | interrupts = <GIC_SPI 27 IRQ_TYPE_EDGE_RISING>; |
| 5d3178c8 BA |
304 | |
| 305 | qcom,ipc = <&apcs 8 14>; | |
| 306 | ||
| 307 | qcom,local-pid = <0>; | |
| 308 | qcom,remote-pid = <1>; | |
| 309 | ||
| 310 | modem_smp2p_out: master-kernel { | |
| 311 | qcom,entry-name = "master-kernel"; | |
| 30f1e2dd | 312 | #qcom,smem-state-cells = <1>; |
| 5d3178c8 BA |
313 | }; |
| 314 | ||
| 315 | modem_smp2p_in: slave-kernel { | |
| 316 | qcom,entry-name = "slave-kernel"; | |
| 317 | ||
| 318 | interrupt-controller; | |
| 319 | #interrupt-cells = <2>; | |
| 320 | }; | |
| 321 | }; | |
| 322 | ||
| 7ccb11e7 BA |
323 | smp2p-wcnss { |
| 324 | compatible = "qcom,smp2p"; | |
| 325 | qcom,smem = <451>, <431>; | |
| 326 | ||
| 327 | interrupt-parent = <&intc>; | |
| 12d2de2e | 328 | interrupts = <GIC_SPI 143 IRQ_TYPE_EDGE_RISING>; |
| 7ccb11e7 BA |
329 | |
| 330 | qcom,ipc = <&apcs 8 18>; | |
| 331 | ||
| 332 | qcom,local-pid = <0>; | |
| 333 | qcom,remote-pid = <4>; | |
| 334 | ||
| 335 | wcnss_smp2p_out: master-kernel { | |
| 336 | qcom,entry-name = "master-kernel"; | |
| 337 | ||
| 30f1e2dd | 338 | #qcom,smem-state-cells = <1>; |
| 7ccb11e7 BA |
339 | }; |
| 340 | ||
| 341 | wcnss_smp2p_in: slave-kernel { | |
| 342 | qcom,entry-name = "slave-kernel"; | |
| 343 | ||
| 344 | interrupt-controller; | |
| 345 | #interrupt-cells = <2>; | |
| 346 | }; | |
| 347 | }; | |
| 348 | ||
| 9af88b2d BA |
349 | smsm { |
| 350 | compatible = "qcom,smsm"; | |
| 351 | ||
| 352 | #address-cells = <1>; | |
| 353 | #size-cells = <0>; | |
| 354 | ||
| 355 | qcom,ipc-1 = <&apcs 8 13>; | |
| 356 | qcom,ipc-2 = <&apcs 8 9>; | |
| 357 | qcom,ipc-3 = <&apcs 8 19>; | |
| 358 | ||
| 359 | apps_smsm: apps@0 { | |
| 360 | reg = <0>; | |
| 361 | ||
| 30f1e2dd | 362 | #qcom,smem-state-cells = <1>; |
| 9af88b2d BA |
363 | }; |
| 364 | ||
| 365 | modem_smsm: modem@1 { | |
| 366 | reg = <1>; | |
| 12d2de2e | 367 | interrupts = <GIC_SPI 26 IRQ_TYPE_EDGE_RISING>; |
| 9af88b2d BA |
368 | |
| 369 | interrupt-controller; | |
| 370 | #interrupt-cells = <2>; | |
| 371 | }; | |
| 372 | ||
| 373 | adsp_smsm: adsp@2 { | |
| 374 | reg = <2>; | |
| 12d2de2e | 375 | interrupts = <GIC_SPI 157 IRQ_TYPE_EDGE_RISING>; |
| 9af88b2d BA |
376 | |
| 377 | interrupt-controller; | |
| 378 | #interrupt-cells = <2>; | |
| 379 | }; | |
| 380 | ||
| 381 | wcnss_smsm: wcnss@7 { | |
| 382 | reg = <7>; | |
| 12d2de2e | 383 | interrupts = <GIC_SPI 144 IRQ_TYPE_EDGE_RISING>; |
| 9af88b2d BA |
384 | |
| 385 | interrupt-controller; | |
| 386 | #interrupt-cells = <2>; | |
| 387 | }; | |
| 388 | }; | |
| 389 | ||
| e0e7da5d AG |
390 | firmware { |
| 391 | scm { | |
| 392 | compatible = "qcom,scm"; | |
| 393 | clocks = <&gcc GCC_CE1_CLK>, <&gcc GCC_CE1_AXI_CLK>, <&gcc GCC_CE1_AHB_CLK>; | |
| 394 | clock-names = "core", "bus", "iface"; | |
| 395 | }; | |
| 396 | }; | |
| 397 | ||
| 2aec37c6 RV |
398 | soc: soc { |
| 399 | #address-cells = <1>; | |
| 400 | #size-cells = <1>; | |
| 401 | ranges; | |
| 402 | compatible = "simple-bus"; | |
| 403 | ||
| 404 | intc: interrupt-controller@f9000000 { | |
| 405 | compatible = "qcom,msm-qgic2"; | |
| 406 | interrupt-controller; | |
| 407 | #interrupt-cells = <3>; | |
| 408 | reg = <0xf9000000 0x1000>, | |
| 409 | <0xf9002000 0x1000>; | |
| 410 | }; | |
| 411 | ||
| 45b0ef05 BA |
412 | apcs: syscon@f9011000 { |
| 413 | compatible = "syscon"; | |
| 414 | reg = <0xf9011000 0x1000>; | |
| 415 | }; | |
| 416 | ||
| c59ffb51 RN |
417 | qfprom: qfprom@fc4bc000 { |
| 418 | #address-cells = <1>; | |
| 419 | #size-cells = <1>; | |
| 420 | compatible = "qcom,qfprom"; | |
| 421 | reg = <0xfc4bc000 0x1000>; | |
| 422 | tsens_calib: calib@d0 { | |
| 423 | reg = <0xd0 0x18>; | |
| 424 | }; | |
| 425 | tsens_backup: backup@440 { | |
| 426 | reg = <0x440 0x10>; | |
| 427 | }; | |
| 428 | }; | |
| 429 | ||
| 430 | tsens: thermal-sensor@fc4a8000 { | |
| 431 | compatible = "qcom,msm8974-tsens"; | |
| 432 | reg = <0xfc4a8000 0x2000>; | |
| 433 | nvmem-cells = <&tsens_calib>, <&tsens_backup>; | |
| 434 | nvmem-cell-names = "calib", "calib_backup"; | |
| 435 | #thermal-sensor-cells = <1>; | |
| 436 | }; | |
| 437 | ||
| 47c5a5d6 SB |
438 | timer@f9020000 { |
| 439 | #address-cells = <1>; | |
| 440 | #size-cells = <1>; | |
| 441 | ranges; | |
| 442 | compatible = "arm,armv7-timer-mem"; | |
| 443 | reg = <0xf9020000 0x1000>; | |
| 444 | clock-frequency = <19200000>; | |
| 445 | ||
| 446 | frame@f9021000 { | |
| 447 | frame-number = <0>; | |
| 1e19d44e FR |
448 | interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>, |
| 449 | <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>; | |
| 47c5a5d6 SB |
450 | reg = <0xf9021000 0x1000>, |
| 451 | <0xf9022000 0x1000>; | |
| 452 | }; | |
| 453 | ||
| 454 | frame@f9023000 { | |
| 455 | frame-number = <1>; | |
| 1e19d44e | 456 | interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>; |
| 47c5a5d6 SB |
457 | reg = <0xf9023000 0x1000>; |
| 458 | status = "disabled"; | |
| 459 | }; | |
| 460 | ||
| 461 | frame@f9024000 { | |
| 462 | frame-number = <2>; | |
| 1e19d44e | 463 | interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>; |
| 47c5a5d6 SB |
464 | reg = <0xf9024000 0x1000>; |
| 465 | status = "disabled"; | |
| 466 | }; | |
| 467 | ||
| 468 | frame@f9025000 { | |
| 469 | frame-number = <3>; | |
| 1e19d44e | 470 | interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>; |
| 47c5a5d6 SB |
471 | reg = <0xf9025000 0x1000>; |
| 472 | status = "disabled"; | |
| 473 | }; | |
| 474 | ||
| 475 | frame@f9026000 { | |
| 476 | frame-number = <4>; | |
| 1e19d44e | 477 | interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>; |
| 47c5a5d6 SB |
478 | reg = <0xf9026000 0x1000>; |
| 479 | status = "disabled"; | |
| 480 | }; | |
| 481 | ||
| 482 | frame@f9027000 { | |
| 483 | frame-number = <5>; | |
| 1e19d44e | 484 | interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>; |
| 47c5a5d6 SB |
485 | reg = <0xf9027000 0x1000>; |
| 486 | status = "disabled"; | |
| 487 | }; | |
| 488 | ||
| 489 | frame@f9028000 { | |
| 490 | frame-number = <6>; | |
| 1e19d44e | 491 | interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>; |
| 47c5a5d6 SB |
492 | reg = <0xf9028000 0x1000>; |
| 493 | status = "disabled"; | |
| 494 | }; | |
| 495 | }; | |
| 496 | ||
| 8c76a638 LI |
497 | saw0: power-controller@f9089000 { |
| 498 | compatible = "qcom,msm8974-saw2-v2.1-cpu", "qcom,saw2"; | |
| 499 | reg = <0xf9089000 0x1000>, <0xf9009000 0x1000>; | |
| 500 | }; | |
| 501 | ||
| 502 | saw1: power-controller@f9099000 { | |
| 503 | compatible = "qcom,msm8974-saw2-v2.1-cpu", "qcom,saw2"; | |
| 504 | reg = <0xf9099000 0x1000>, <0xf9009000 0x1000>; | |
| 505 | }; | |
| 506 | ||
| 507 | saw2: power-controller@f90a9000 { | |
| 508 | compatible = "qcom,msm8974-saw2-v2.1-cpu", "qcom,saw2"; | |
| 509 | reg = <0xf90a9000 0x1000>, <0xf9009000 0x1000>; | |
| 510 | }; | |
| 511 | ||
| 512 | saw3: power-controller@f90b9000 { | |
| 513 | compatible = "qcom,msm8974-saw2-v2.1-cpu", "qcom,saw2"; | |
| 514 | reg = <0xf90b9000 0x1000>, <0xf9009000 0x1000>; | |
| 515 | }; | |
| 516 | ||
| 517 | saw_l2: power-controller@f9012000 { | |
| 2ab27991 RV |
518 | compatible = "qcom,saw2"; |
| 519 | reg = <0xf9012000 0x1000>; | |
| 520 | regulator; | |
| 521 | }; | |
| 522 | ||
| 523 | acc0: clock-controller@f9088000 { | |
| 524 | compatible = "qcom,kpss-acc-v2"; | |
| 525 | reg = <0xf9088000 0x1000>, <0xf9008000 0x1000>; | |
| 526 | }; | |
| 527 | ||
| 528 | acc1: clock-controller@f9098000 { | |
| 529 | compatible = "qcom,kpss-acc-v2"; | |
| 530 | reg = <0xf9098000 0x1000>, <0xf9008000 0x1000>; | |
| 531 | }; | |
| 532 | ||
| 533 | acc2: clock-controller@f90a8000 { | |
| 534 | compatible = "qcom,kpss-acc-v2"; | |
| 535 | reg = <0xf90a8000 0x1000>, <0xf9008000 0x1000>; | |
| 536 | }; | |
| 537 | ||
| 538 | acc3: clock-controller@f90b8000 { | |
| 539 | compatible = "qcom,kpss-acc-v2"; | |
| 540 | reg = <0xf90b8000 0x1000>, <0xf9008000 0x1000>; | |
| 541 | }; | |
| 542 | ||
| 74e848f6 SB |
543 | restart@fc4ab000 { |
| 544 | compatible = "qcom,pshold"; | |
| 545 | reg = <0xfc4ab000 0x4>; | |
| 546 | }; | |
| 3933d267 SB |
547 | |
| 548 | gcc: clock-controller@fc400000 { | |
| 549 | compatible = "qcom,gcc-msm8974"; | |
| 550 | #clock-cells = <1>; | |
| 551 | #reset-cells = <1>; | |
| 89c7e671 | 552 | #power-domain-cells = <1>; |
| 3933d267 SB |
553 | reg = <0xfc400000 0x4000>; |
| 554 | }; | |
| 555 | ||
| 4ac5a200 SB |
556 | tcsr: syscon@fd4a0000 { |
| 557 | compatible = "syscon"; | |
| 558 | reg = <0xfd4a0000 0x10000>; | |
| 559 | }; | |
| 560 | ||
| b4e745e1 BA |
561 | tcsr_mutex_block: syscon@fd484000 { |
| 562 | compatible = "syscon"; | |
| 563 | reg = <0xfd484000 0x2000>; | |
| 564 | }; | |
| 565 | ||
| 3933d267 SB |
566 | mmcc: clock-controller@fd8c0000 { |
| 567 | compatible = "qcom,mmcc-msm8974"; | |
| 568 | #clock-cells = <1>; | |
| 569 | #reset-cells = <1>; | |
| 89c7e671 | 570 | #power-domain-cells = <1>; |
| 3933d267 SB |
571 | reg = <0xfd8c0000 0x6000>; |
| 572 | }; | |
| 573 | ||
| b4e745e1 BA |
574 | tcsr_mutex: tcsr-mutex { |
| 575 | compatible = "qcom,tcsr-mutex"; | |
| 576 | syscon = <&tcsr_mutex_block 0 0x80>; | |
| 577 | ||
| 578 | #hwlock-cells = <1>; | |
| 579 | }; | |
| 580 | ||
| d0bfd7c9 SB |
581 | rpm_msg_ram: memory@fc428000 { |
| 582 | compatible = "qcom,rpm-msg-ram"; | |
| 6297c4b2 | 583 | reg = <0xfc428000 0x4000>; |
| 6297c4b2 BA |
584 | }; |
| 585 | ||
| 5cae8a9f BS |
586 | blsp1_uart1: serial@f991d000 { |
| 587 | compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm"; | |
| 588 | reg = <0xf991d000 0x1000>; | |
| dcf14501 | 589 | interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>; |
| 5cae8a9f BS |
590 | clocks = <&gcc GCC_BLSP1_UART1_APPS_CLK>, <&gcc GCC_BLSP1_AHB_CLK>; |
| 591 | clock-names = "core", "iface"; | |
| 592 | status = "disabled"; | |
| 593 | }; | |
| 594 | ||
| 10bfcfea | 595 | blsp1_uart2: serial@f991e000 { |
| 3933d267 SB |
596 | compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm"; |
| 597 | reg = <0xf991e000 0x1000>; | |
| dcf14501 | 598 | interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>; |
| 3933d267 SB |
599 | clocks = <&gcc GCC_BLSP1_UART2_APPS_CLK>, <&gcc GCC_BLSP1_AHB_CLK>; |
| 600 | clock-names = "core", "iface"; | |
| ba08220a | 601 | status = "disabled"; |
| 3933d267 | 602 | }; |
| 19f4f8c1 | 603 | |
| 3e944c76 GD |
604 | sdhci@f9824900 { |
| 605 | compatible = "qcom,sdhci-msm-v4"; | |
| 606 | reg = <0xf9824900 0x11c>, <0xf9824000 0x800>; | |
| 607 | reg-names = "hc_mem", "core_mem"; | |
| dcf14501 FR |
608 | interrupts = <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>, |
| 609 | <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>; | |
| 3e944c76 | 610 | interrupt-names = "hc_irq", "pwr_irq"; |
| a91b2e69 RH |
611 | clocks = <&gcc GCC_SDCC1_APPS_CLK>, |
| 612 | <&gcc GCC_SDCC1_AHB_CLK>, | |
| 613 | <&xo_board>; | |
| 614 | clock-names = "core", "iface", "xo"; | |
| 3e944c76 GD |
615 | status = "disabled"; |
| 616 | }; | |
| 617 | ||
| ab806618 BA |
618 | sdhci@f9864900 { |
| 619 | compatible = "qcom,sdhci-msm-v4"; | |
| 620 | reg = <0xf9864900 0x11c>, <0xf9864000 0x800>; | |
| 621 | reg-names = "hc_mem", "core_mem"; | |
| dcf14501 FR |
622 | interrupts = <GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>, |
| 623 | <GIC_SPI 224 IRQ_TYPE_LEVEL_HIGH>; | |
| ab806618 BA |
624 | interrupt-names = "hc_irq", "pwr_irq"; |
| 625 | clocks = <&gcc GCC_SDCC3_APPS_CLK>, | |
| 626 | <&gcc GCC_SDCC3_AHB_CLK>, | |
| 627 | <&xo_board>; | |
| 628 | clock-names = "core", "iface", "xo"; | |
| 629 | status = "disabled"; | |
| 630 | }; | |
| 631 | ||
| 3e944c76 GD |
632 | sdhci@f98a4900 { |
| 633 | compatible = "qcom,sdhci-msm-v4"; | |
| 634 | reg = <0xf98a4900 0x11c>, <0xf98a4000 0x800>; | |
| 635 | reg-names = "hc_mem", "core_mem"; | |
| dcf14501 FR |
636 | interrupts = <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>, |
| 637 | <GIC_SPI 221 IRQ_TYPE_LEVEL_HIGH>; | |
| 3e944c76 | 638 | interrupt-names = "hc_irq", "pwr_irq"; |
| a91b2e69 RH |
639 | clocks = <&gcc GCC_SDCC2_APPS_CLK>, |
| 640 | <&gcc GCC_SDCC2_AHB_CLK>, | |
| 641 | <&xo_board>; | |
| 642 | clock-names = "core", "iface", "xo"; | |
| 3e944c76 GD |
643 | status = "disabled"; |
| 644 | }; | |
| 645 | ||
| 4ac5a200 SB |
646 | otg: usb@f9a55000 { |
| 647 | compatible = "qcom,ci-hdrc"; | |
| 648 | reg = <0xf9a55000 0x200>, | |
| 649 | <0xf9a55200 0x200>; | |
| 650 | interrupts = <GIC_SPI 134 IRQ_TYPE_LEVEL_HIGH>; | |
| 651 | clocks = <&gcc GCC_USB_HS_AHB_CLK>, | |
| 652 | <&gcc GCC_USB_HS_SYSTEM_CLK>; | |
| 653 | clock-names = "iface", "core"; | |
| 654 | assigned-clocks = <&gcc GCC_USB_HS_SYSTEM_CLK>; | |
| 655 | assigned-clock-rates = <75000000>; | |
| 656 | resets = <&gcc GCC_USB_HS_BCR>; | |
| 657 | reset-names = "core"; | |
| 658 | phy_type = "ulpi"; | |
| 659 | dr_mode = "otg"; | |
| 660 | ahb-burst-config = <0>; | |
| 661 | phy-names = "usb-phy"; | |
| 662 | status = "disabled"; | |
| 663 | #reset-cells = <1>; | |
| 664 | ||
| 665 | ulpi { | |
| 666 | usb_hs1_phy: phy@a { | |
| 667 | compatible = "qcom,usb-hs-phy-msm8974", | |
| 668 | "qcom,usb-hs-phy"; | |
| 669 | #phy-cells = <0>; | |
| 670 | clocks = <&xo_board>, <&gcc GCC_USB2A_PHY_SLEEP_CLK>; | |
| 671 | clock-names = "ref", "sleep"; | |
| 672 | resets = <&gcc GCC_USB2A_PHY_BCR>, <&otg 0>; | |
| 673 | reset-names = "phy", "por"; | |
| 674 | status = "disabled"; | |
| 675 | }; | |
| 676 | ||
| 677 | usb_hs2_phy: phy@b { | |
| 678 | compatible = "qcom,usb-hs-phy-msm8974", | |
| 679 | "qcom,usb-hs-phy"; | |
| 680 | #phy-cells = <0>; | |
| 681 | clocks = <&xo_board>, <&gcc GCC_USB2B_PHY_SLEEP_CLK>; | |
| 682 | clock-names = "ref", "sleep"; | |
| 683 | resets = <&gcc GCC_USB2B_PHY_BCR>, <&otg 1>; | |
| 684 | reset-names = "phy", "por"; | |
| 685 | status = "disabled"; | |
| 686 | }; | |
| 687 | }; | |
| 688 | }; | |
| 689 | ||
| 19f4f8c1 SV |
690 | rng@f9bff000 { |
| 691 | compatible = "qcom,prng"; | |
| 692 | reg = <0xf9bff000 0x200>; | |
| 693 | clocks = <&gcc GCC_PRNG_AHB_CLK>; | |
| 694 | clock-names = "core"; | |
| 695 | }; | |
| 7d7db8db II |
696 | |
| 697 | msmgpio: pinctrl@fd510000 { | |
| 698 | compatible = "qcom,msm8974-pinctrl"; | |
| 699 | reg = <0xfd510000 0x4000>; | |
| 700 | gpio-controller; | |
| 701 | #gpio-cells = <2>; | |
| 702 | interrupt-controller; | |
| 703 | #interrupt-cells = <2>; | |
| dcf14501 | 704 | interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>; |
| 7d7db8db | 705 | }; |
| bf7f6b04 | 706 | |
| 89af1c2d BA |
707 | i2c@f9924000 { |
| 708 | status = "disabled"; | |
| 709 | compatible = "qcom,i2c-qup-v2.1.1"; | |
| 710 | reg = <0xf9924000 0x1000>; | |
| dcf14501 | 711 | interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>; |
| 89af1c2d BA |
712 | clocks = <&gcc GCC_BLSP1_QUP2_I2C_APPS_CLK>, <&gcc GCC_BLSP1_AHB_CLK>; |
| 713 | clock-names = "core", "iface"; | |
| 714 | #address-cells = <1>; | |
| 715 | #size-cells = <0>; | |
| 716 | }; | |
| 717 | ||
| bd939250 BM |
718 | blsp_i2c3: i2c@f9925000 { |
| 719 | status = "disabled"; | |
| 720 | compatible = "qcom,i2c-qup-v2.1.1"; | |
| 721 | reg = <0xf9925000 0x1000>; | |
| 703e699d | 722 | interrupts = <0 97 IRQ_TYPE_LEVEL_HIGH>; |
| bd939250 BM |
723 | clocks = <&gcc GCC_BLSP1_QUP3_I2C_APPS_CLK>, <&gcc GCC_BLSP1_AHB_CLK>; |
| 724 | clock-names = "core", "iface"; | |
| 725 | #address-cells = <1>; | |
| 726 | #size-cells = <0>; | |
| 727 | }; | |
| 728 | ||
| 580df59f BA |
729 | blsp_i2c8: i2c@f9964000 { |
| 730 | status = "disabled"; | |
| 731 | compatible = "qcom,i2c-qup-v2.1.1"; | |
| 732 | reg = <0xf9964000 0x1000>; | |
| dcf14501 | 733 | interrupts = <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>; |
| 580df59f BA |
734 | clocks = <&gcc GCC_BLSP2_QUP2_I2C_APPS_CLK>, <&gcc GCC_BLSP2_AHB_CLK>; |
| 735 | clock-names = "core", "iface"; | |
| 736 | #address-cells = <1>; | |
| 737 | #size-cells = <0>; | |
| 738 | }; | |
| 739 | ||
| bf7f6b04 | 740 | blsp_i2c11: i2c@f9967000 { |
| 04edde25 | 741 | status = "disabled"; |
| bf7f6b04 | 742 | compatible = "qcom,i2c-qup-v2.1.1"; |
| 743 | reg = <0xf9967000 0x1000>; | |
| dcf14501 | 744 | interrupts = <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>; |
| bf7f6b04 | 745 | clocks = <&gcc GCC_BLSP2_QUP5_I2C_APPS_CLK>, <&gcc GCC_BLSP2_AHB_CLK>; |
| 746 | clock-names = "core", "iface"; | |
| 747 | #address-cells = <1>; | |
| 748 | #size-cells = <0>; | |
| 938b4d4e AG |
749 | dmas = <&blsp2_dma 20>, <&blsp2_dma 21>; |
| 750 | dma-names = "tx", "rx"; | |
| bf7f6b04 | 751 | }; |
| af22e46d | 752 | |
| fe8d81fe BM |
753 | blsp_i2c12: i2c@f9968000 { |
| 754 | status = "disabled"; | |
| 755 | compatible = "qcom,i2c-qup-v2.1.1"; | |
| 756 | reg = <0xf9968000 0x1000>; | |
| 703e699d | 757 | interrupts = <0 106 IRQ_TYPE_LEVEL_HIGH>; |
| fe8d81fe BM |
758 | clocks = <&gcc GCC_BLSP2_QUP6_I2C_APPS_CLK>, <&gcc GCC_BLSP2_AHB_CLK>; |
| 759 | clock-names = "core", "iface"; | |
| 760 | #address-cells = <1>; | |
| 761 | #size-cells = <0>; | |
| 762 | }; | |
| 763 | ||
| af22e46d II |
764 | spmi_bus: spmi@fc4cf000 { |
| 765 | compatible = "qcom,spmi-pmic-arb"; | |
| 766 | reg-names = "core", "intr", "cnfg"; | |
| 767 | reg = <0xfc4cf000 0x1000>, | |
| 768 | <0xfc4cb000 0x1000>, | |
| 769 | <0xfc4ca000 0x1000>; | |
| 770 | interrupt-names = "periph_irq"; | |
| dcf14501 | 771 | interrupts = <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>; |
| af22e46d II |
772 | qcom,ee = <0>; |
| 773 | qcom,channel = <0>; | |
| 774 | #address-cells = <2>; | |
| 775 | #size-cells = <0>; | |
| 776 | interrupt-controller; | |
| 777 | #interrupt-cells = <4>; | |
| 778 | }; | |
| d44cbb1e AG |
779 | |
| 780 | blsp2_dma: dma-controller@f9944000 { | |
| 781 | compatible = "qcom,bam-v1.4.0"; | |
| 782 | reg = <0xf9944000 0x19000>; | |
| 783 | interrupts = <GIC_SPI 239 IRQ_TYPE_LEVEL_HIGH>; | |
| 784 | clocks = <&gcc GCC_BLSP2_AHB_CLK>; | |
| 785 | clock-names = "bam_clk"; | |
| 786 | #dma-cells = <1>; | |
| 787 | qcom,ee = <0>; | |
| 788 | }; | |
| 769907ae | 789 | |
| 1e20223d II |
790 | etr@fc322000 { |
| 791 | compatible = "arm,coresight-tmc", "arm,primecell"; | |
| 792 | reg = <0xfc322000 0x1000>; | |
| 793 | ||
| 794 | clocks = <&rpmcc RPM_SMD_QDSS_CLK>, <&rpmcc RPM_SMD_QDSS_A_CLK>; | |
| 795 | clock-names = "apb_pclk", "atclk"; | |
| 796 | ||
| ca02f96b SP |
797 | in-ports { |
| 798 | port { | |
| 799 | etr_in: endpoint { | |
| 800 | remote-endpoint = <&replicator_out0>; | |
| 801 | }; | |
| 1e20223d II |
802 | }; |
| 803 | }; | |
| 804 | }; | |
| 805 | ||
| 806 | tpiu@fc318000 { | |
| 807 | compatible = "arm,coresight-tpiu", "arm,primecell"; | |
| 808 | reg = <0xfc318000 0x1000>; | |
| 809 | ||
| 810 | clocks = <&rpmcc RPM_SMD_QDSS_CLK>, <&rpmcc RPM_SMD_QDSS_A_CLK>; | |
| 811 | clock-names = "apb_pclk", "atclk"; | |
| 812 | ||
| ca02f96b SP |
813 | in-ports { |
| 814 | port { | |
| 815 | tpiu_in: endpoint { | |
| 816 | remote-endpoint = <&replicator_out1>; | |
| 817 | }; | |
| 1e20223d II |
818 | }; |
| 819 | }; | |
| 820 | }; | |
| 821 | ||
| 822 | replicator@fc31c000 { | |
| 8d4c75fb | 823 | compatible = "arm,coresight-dynamic-replicator", "arm,primecell"; |
| 1e20223d II |
824 | reg = <0xfc31c000 0x1000>; |
| 825 | ||
| 826 | clocks = <&rpmcc RPM_SMD_QDSS_CLK>, <&rpmcc RPM_SMD_QDSS_A_CLK>; | |
| 827 | clock-names = "apb_pclk", "atclk"; | |
| 828 | ||
| ca02f96b | 829 | out-ports { |
| 1e20223d II |
830 | #address-cells = <1>; |
| 831 | #size-cells = <0>; | |
| 832 | ||
| 833 | port@0 { | |
| 834 | reg = <0>; | |
| 835 | replicator_out0: endpoint { | |
| 836 | remote-endpoint = <&etr_in>; | |
| 837 | }; | |
| 838 | }; | |
| 839 | port@1 { | |
| 840 | reg = <1>; | |
| 841 | replicator_out1: endpoint { | |
| 842 | remote-endpoint = <&tpiu_in>; | |
| 843 | }; | |
| 844 | }; | |
| ca02f96b SP |
845 | }; |
| 846 | ||
| 847 | in-ports { | |
| 848 | port { | |
| 1e20223d | 849 | replicator_in: endpoint { |
| 1e20223d II |
850 | remote-endpoint = <&etf_out>; |
| 851 | }; | |
| 852 | }; | |
| 853 | }; | |
| 854 | }; | |
| 855 | ||
| 856 | etf@fc307000 { | |
| 857 | compatible = "arm,coresight-tmc", "arm,primecell"; | |
| 858 | reg = <0xfc307000 0x1000>; | |
| 859 | ||
| 860 | clocks = <&rpmcc RPM_SMD_QDSS_CLK>, <&rpmcc RPM_SMD_QDSS_A_CLK>; | |
| 861 | clock-names = "apb_pclk", "atclk"; | |
| 862 | ||
| ca02f96b SP |
863 | out-ports { |
| 864 | port { | |
| 1e20223d II |
865 | etf_out: endpoint { |
| 866 | remote-endpoint = <&replicator_in>; | |
| 867 | }; | |
| 868 | }; | |
| ca02f96b SP |
869 | }; |
| 870 | ||
| 871 | in-ports { | |
| 872 | port { | |
| 1e20223d | 873 | etf_in: endpoint { |
| 1e20223d II |
874 | remote-endpoint = <&merger_out>; |
| 875 | }; | |
| 876 | }; | |
| 877 | }; | |
| 878 | }; | |
| 879 | ||
| 880 | funnel@fc31b000 { | |
| 881 | compatible = "arm,coresight-funnel", "arm,primecell"; | |
| 882 | reg = <0xfc31b000 0x1000>; | |
| 883 | ||
| 884 | clocks = <&rpmcc RPM_SMD_QDSS_CLK>, <&rpmcc RPM_SMD_QDSS_A_CLK>; | |
| 885 | clock-names = "apb_pclk", "atclk"; | |
| 886 | ||
| ca02f96b | 887 | in-ports { |
| 1e20223d II |
888 | #address-cells = <1>; |
| 889 | #size-cells = <0>; | |
| 890 | ||
| 891 | /* | |
| 892 | * Not described input ports: | |
| 893 | * 0 - connected trought funnel to Audio, Modem and | |
| 894 | * Resource and Power Manager CPU's | |
| 895 | * 2...7 - not-connected | |
| 896 | */ | |
| 897 | port@1 { | |
| 898 | reg = <1>; | |
| 899 | merger_in1: endpoint { | |
| 1e20223d II |
900 | remote-endpoint = <&funnel1_out>; |
| 901 | }; | |
| 902 | }; | |
| ca02f96b SP |
903 | }; |
| 904 | ||
| 905 | out-ports { | |
| 906 | port { | |
| 1e20223d II |
907 | merger_out: endpoint { |
| 908 | remote-endpoint = <&etf_in>; | |
| 909 | }; | |
| 910 | }; | |
| 911 | }; | |
| 912 | }; | |
| 913 | ||
| 914 | funnel@fc31a000 { | |
| 915 | compatible = "arm,coresight-funnel", "arm,primecell"; | |
| 916 | reg = <0xfc31a000 0x1000>; | |
| 917 | ||
| 918 | clocks = <&rpmcc RPM_SMD_QDSS_CLK>, <&rpmcc RPM_SMD_QDSS_A_CLK>; | |
| 919 | clock-names = "apb_pclk", "atclk"; | |
| 920 | ||
| ca02f96b | 921 | in-ports { |
| 1e20223d II |
922 | #address-cells = <1>; |
| 923 | #size-cells = <0>; | |
| 924 | ||
| 925 | /* | |
| 926 | * Not described input ports: | |
| 927 | * 0 - not-connected | |
| 928 | * 1 - connected trought funnel to Multimedia CPU | |
| 929 | * 2 - connected to Wireless CPU | |
| 930 | * 3 - not-connected | |
| 931 | * 4 - not-connected | |
| 932 | * 6 - not-connected | |
| 933 | * 7 - connected to STM | |
| 934 | */ | |
| 935 | port@5 { | |
| 936 | reg = <5>; | |
| 937 | funnel1_in5: endpoint { | |
| 1e20223d II |
938 | remote-endpoint = <&kpss_out>; |
| 939 | }; | |
| 940 | }; | |
| ca02f96b SP |
941 | }; |
| 942 | ||
| 943 | out-ports { | |
| 944 | port { | |
| 1e20223d II |
945 | funnel1_out: endpoint { |
| 946 | remote-endpoint = <&merger_in1>; | |
| 947 | }; | |
| 948 | }; | |
| 949 | }; | |
| 950 | }; | |
| 951 | ||
| 952 | funnel@fc345000 { /* KPSS funnel only 4 inputs are used */ | |
| 953 | compatible = "arm,coresight-funnel", "arm,primecell"; | |
| 954 | reg = <0xfc345000 0x1000>; | |
| 955 | ||
| 956 | clocks = <&rpmcc RPM_SMD_QDSS_CLK>, <&rpmcc RPM_SMD_QDSS_A_CLK>; | |
| 957 | clock-names = "apb_pclk", "atclk"; | |
| 958 | ||
| ca02f96b | 959 | in-ports { |
| 1e20223d II |
960 | #address-cells = <1>; |
| 961 | #size-cells = <0>; | |
| 962 | ||
| 963 | port@0 { | |
| 964 | reg = <0>; | |
| 965 | kpss_in0: endpoint { | |
| 1e20223d II |
966 | remote-endpoint = <&etm0_out>; |
| 967 | }; | |
| 968 | }; | |
| 969 | port@1 { | |
| 970 | reg = <1>; | |
| 971 | kpss_in1: endpoint { | |
| 1e20223d II |
972 | remote-endpoint = <&etm1_out>; |
| 973 | }; | |
| 974 | }; | |
| 975 | port@2 { | |
| 976 | reg = <2>; | |
| 977 | kpss_in2: endpoint { | |
| 1e20223d II |
978 | remote-endpoint = <&etm2_out>; |
| 979 | }; | |
| 980 | }; | |
| 981 | port@3 { | |
| 982 | reg = <3>; | |
| 983 | kpss_in3: endpoint { | |
| 1e20223d II |
984 | remote-endpoint = <&etm3_out>; |
| 985 | }; | |
| 986 | }; | |
| ca02f96b SP |
987 | }; |
| 988 | ||
| 989 | out-ports { | |
| 990 | port { | |
| 1e20223d II |
991 | kpss_out: endpoint { |
| 992 | remote-endpoint = <&funnel1_in5>; | |
| 993 | }; | |
| 994 | }; | |
| 995 | }; | |
| 996 | }; | |
| 997 | ||
| 998 | etm@fc33c000 { | |
| 999 | compatible = "arm,coresight-etm4x", "arm,primecell"; | |
| 1000 | reg = <0xfc33c000 0x1000>; | |
| 1001 | ||
| 1002 | clocks = <&rpmcc RPM_SMD_QDSS_CLK>, <&rpmcc RPM_SMD_QDSS_A_CLK>; | |
| 1003 | clock-names = "apb_pclk", "atclk"; | |
| 1004 | ||
| 1005 | cpu = <&CPU0>; | |
| 1006 | ||
| ca02f96b SP |
1007 | out-ports { |
| 1008 | port { | |
| 1009 | etm0_out: endpoint { | |
| 1010 | remote-endpoint = <&kpss_in0>; | |
| 1011 | }; | |
| 1e20223d II |
1012 | }; |
| 1013 | }; | |
| 1014 | }; | |
| 1015 | ||
| 1016 | etm@fc33d000 { | |
| 1017 | compatible = "arm,coresight-etm4x", "arm,primecell"; | |
| 1018 | reg = <0xfc33d000 0x1000>; | |
| 1019 | ||
| 1020 | clocks = <&rpmcc RPM_SMD_QDSS_CLK>, <&rpmcc RPM_SMD_QDSS_A_CLK>; | |
| 1021 | clock-names = "apb_pclk", "atclk"; | |
| 1022 | ||
| 1023 | cpu = <&CPU1>; | |
| 1024 | ||
| ca02f96b SP |
1025 | out-ports { |
| 1026 | port { | |
| 1027 | etm1_out: endpoint { | |
| 1028 | remote-endpoint = <&kpss_in1>; | |
| 1029 | }; | |
| 1e20223d II |
1030 | }; |
| 1031 | }; | |
| 1032 | }; | |
| 1033 | ||
| 1034 | etm@fc33e000 { | |
| 1035 | compatible = "arm,coresight-etm4x", "arm,primecell"; | |
| 1036 | reg = <0xfc33e000 0x1000>; | |
| 1037 | ||
| 1038 | clocks = <&rpmcc RPM_SMD_QDSS_CLK>, <&rpmcc RPM_SMD_QDSS_A_CLK>; | |
| 1039 | clock-names = "apb_pclk", "atclk"; | |
| 1040 | ||
| 1041 | cpu = <&CPU2>; | |
| 1042 | ||
| ca02f96b SP |
1043 | out-ports { |
| 1044 | port { | |
| 1045 | etm2_out: endpoint { | |
| 1046 | remote-endpoint = <&kpss_in2>; | |
| 1047 | }; | |
| 1e20223d II |
1048 | }; |
| 1049 | }; | |
| 1050 | }; | |
| 1051 | ||
| 1052 | etm@fc33f000 { | |
| 1053 | compatible = "arm,coresight-etm4x", "arm,primecell"; | |
| 1054 | reg = <0xfc33f000 0x1000>; | |
| 1055 | ||
| 1056 | clocks = <&rpmcc RPM_SMD_QDSS_CLK>, <&rpmcc RPM_SMD_QDSS_A_CLK>; | |
| 1057 | clock-names = "apb_pclk", "atclk"; | |
| 1058 | ||
| 1059 | cpu = <&CPU3>; | |
| 1060 | ||
| ca02f96b SP |
1061 | out-ports { |
| 1062 | port { | |
| 1063 | etm3_out: endpoint { | |
| 1064 | remote-endpoint = <&kpss_in3>; | |
| 1065 | }; | |
| 1e20223d II |
1066 | }; |
| 1067 | }; | |
| 1068 | }; | |
| 2aec37c6 | 1069 | }; |
| 45b0ef05 BA |
1070 | |
| 1071 | smd { | |
| 1072 | compatible = "qcom,smd"; | |
| 1073 | ||
| 3028cbab | 1074 | adsp { |
| 12d2de2e | 1075 | interrupts = <GIC_SPI 156 IRQ_TYPE_EDGE_RISING>; |
| 3028cbab BA |
1076 | |
| 1077 | qcom,ipc = <&apcs 8 8>; | |
| 1078 | qcom,smd-edge = <1>; | |
| 1079 | }; | |
| 1080 | ||
| 5d3178c8 | 1081 | modem { |
| 12d2de2e | 1082 | interrupts = <GIC_SPI 25 IRQ_TYPE_EDGE_RISING>; |
| 5d3178c8 BA |
1083 | |
| 1084 | qcom,ipc = <&apcs 8 12>; | |
| 1085 | qcom,smd-edge = <0>; | |
| 1086 | }; | |
| 1087 | ||
| 45b0ef05 | 1088 | rpm { |
| b0ef3d94 | 1089 | interrupts = <GIC_SPI 168 IRQ_TYPE_EDGE_RISING>; |
| 45b0ef05 BA |
1090 | qcom,ipc = <&apcs 8 0>; |
| 1091 | qcom,smd-edge = <15>; | |
| 1092 | ||
| 1093 | rpm_requests { | |
| 1094 | compatible = "qcom,rpm-msm8974"; | |
| 1095 | qcom,smd-channels = "rpm_requests"; | |
| 1096 | ||
| 9db9559c GD |
1097 | rpmcc: clock-controller { |
| 1098 | compatible = "qcom,rpmcc-msm8974", "qcom,rpmcc"; | |
| 1099 | #clock-cells = <1>; | |
| 1100 | }; | |
| 1101 | ||
| 45b0ef05 BA |
1102 | pm8841-regulators { |
| 1103 | compatible = "qcom,rpm-pm8841-regulators"; | |
| 1104 | ||
| 1105 | pm8841_s1: s1 {}; | |
| 1106 | pm8841_s2: s2 {}; | |
| 1107 | pm8841_s3: s3 {}; | |
| 1108 | pm8841_s4: s4 {}; | |
| 1109 | pm8841_s5: s5 {}; | |
| 1110 | pm8841_s6: s6 {}; | |
| 1111 | pm8841_s7: s7 {}; | |
| 1112 | pm8841_s8: s8 {}; | |
| 1113 | }; | |
| 1114 | ||
| 1115 | pm8941-regulators { | |
| 1116 | compatible = "qcom,rpm-pm8941-regulators"; | |
| 1117 | ||
| 1118 | pm8941_s1: s1 {}; | |
| 1119 | pm8941_s2: s2 {}; | |
| 1120 | pm8941_s3: s3 {}; | |
| 45b0ef05 BA |
1121 | |
| 1122 | pm8941_l1: l1 {}; | |
| 1123 | pm8941_l2: l2 {}; | |
| 1124 | pm8941_l3: l3 {}; | |
| 1125 | pm8941_l4: l4 {}; | |
| 1126 | pm8941_l5: l5 {}; | |
| 1127 | pm8941_l6: l6 {}; | |
| 1128 | pm8941_l7: l7 {}; | |
| 1129 | pm8941_l8: l8 {}; | |
| 1130 | pm8941_l9: l9 {}; | |
| 1131 | pm8941_l10: l10 {}; | |
| 1132 | pm8941_l11: l11 {}; | |
| 1133 | pm8941_l12: l12 {}; | |
| 1134 | pm8941_l13: l13 {}; | |
| 1135 | pm8941_l14: l14 {}; | |
| 1136 | pm8941_l15: l15 {}; | |
| 1137 | pm8941_l16: l16 {}; | |
| 1138 | pm8941_l17: l17 {}; | |
| 1139 | pm8941_l18: l18 {}; | |
| 1140 | pm8941_l19: l19 {}; | |
| 1141 | pm8941_l20: l20 {}; | |
| 1142 | pm8941_l21: l21 {}; | |
| 1143 | pm8941_l22: l22 {}; | |
| 1144 | pm8941_l23: l23 {}; | |
| 1145 | pm8941_l24: l24 {}; | |
| 1146 | ||
| 1147 | pm8941_lvs1: lvs1 {}; | |
| 1148 | pm8941_lvs2: lvs2 {}; | |
| 1149 | pm8941_lvs3: lvs3 {}; | |
| 45b0ef05 BA |
1150 | }; |
| 1151 | }; | |
| 1152 | }; | |
| 1153 | }; | |
| 0485ef8e | 1154 | |
| 73bae19c BS |
1155 | vreg_boost: vreg-boost { |
| 1156 | compatible = "regulator-fixed"; | |
| 1157 | ||
| 1158 | regulator-name = "vreg-boost"; | |
| 1159 | regulator-min-microvolt = <3150000>; | |
| 1160 | regulator-max-microvolt = <3150000>; | |
| 1161 | ||
| 1162 | regulator-always-on; | |
| 1163 | regulator-boot-on; | |
| 1164 | ||
| 1165 | gpio = <&pm8941_gpios 21 GPIO_ACTIVE_HIGH>; | |
| 1166 | enable-active-high; | |
| 1167 | ||
| 1168 | pinctrl-names = "default"; | |
| 1169 | pinctrl-0 = <&boost_bypass_n_pin>; | |
| 1170 | }; | |
| 0485ef8e BS |
1171 | vreg_vph_pwr: vreg-vph-pwr { |
| 1172 | compatible = "regulator-fixed"; | |
| 1173 | regulator-name = "vph-pwr"; | |
| 1174 | ||
| 1175 | regulator-min-microvolt = <3600000>; | |
| 1176 | regulator-max-microvolt = <3600000>; | |
| 1177 | ||
| 1178 | regulator-always-on; | |
| 1179 | }; | |
| 2aec37c6 | 1180 | }; |