projects / linux-2.6-block.git / blame
| Commit | Line | Data |
|---|---|---|
| b2441318 | 1 | // SPDX-License-Identifier: GPL-2.0 |
| f335b8af KG |
2 | /dts-v1/; |
| 3 | ||
| 4 | #include "skeleton.dtsi" | |
| 5 | #include <dt-bindings/clock/qcom,gcc-msm8960.h> | |
| 223280b1 | 6 | #include <dt-bindings/reset/qcom,gcc-msm8960.h> |
| 3fe5e3ce | 7 | #include <dt-bindings/clock/qcom,mmcc-msm8960.h> |
| 542b9f07 | 8 | #include <dt-bindings/clock/qcom,rpmcc.h> |
| f335b8af | 9 | #include <dt-bindings/soc/qcom,gsbi.h> |
| ca88696e | 10 | #include <dt-bindings/interrupt-controller/irq.h> |
| 8b8936fc | 11 | #include <dt-bindings/interrupt-controller/arm-gic.h> |
| f335b8af KG |
12 | / { |
| 13 | model = "Qualcomm APQ8064"; | |
| 14 | compatible = "qcom,apq8064"; | |
| 15 | interrupt-parent = <&intc>; | |
| 16 | ||
| 24a9baf9 BA |
17 | reserved-memory { |
| 18 | #address-cells = <1>; | |
| 19 | #size-cells = <1>; | |
| 20 | ranges; | |
| 21 | ||
| 22 | smem_region: smem@80000000 { | |
| 23 | reg = <0x80000000 0x200000>; | |
| 24 | no-map; | |
| 25 | }; | |
| f9a8aaed BA |
26 | |
| 27 | wcnss_mem: wcnss@8f000000 { | |
| 28 | reg = <0x8f000000 0x700000>; | |
| 29 | no-map; | |
| 30 | }; | |
| 24a9baf9 BA |
31 | }; |
| 32 | ||
| f335b8af KG |
33 | cpus { |
| 34 | #address-cells = <1>; | |
| 35 | #size-cells = <0>; | |
| 36 | ||
| 7a5c275f | 37 | CPU0: cpu@0 { |
| f335b8af KG |
38 | compatible = "qcom,krait"; |
| 39 | enable-method = "qcom,kpss-acc-v1"; | |
| 40 | device_type = "cpu"; | |
| 41 | reg = <0>; | |
| 42 | next-level-cache = <&L2>; | |
| 43 | qcom,acc = <&acc0>; | |
| 44 | qcom,saw = <&saw0>; | |
| 06c49f2b | 45 | cpu-idle-states = <&CPU_SPC>; |
| f335b8af KG |
46 | }; |
| 47 | ||
| 7a5c275f | 48 | CPU1: cpu@1 { |
| f335b8af KG |
49 | compatible = "qcom,krait"; |
| 50 | enable-method = "qcom,kpss-acc-v1"; | |
| 51 | device_type = "cpu"; | |
| 52 | reg = <1>; | |
| 53 | next-level-cache = <&L2>; | |
| 54 | qcom,acc = <&acc1>; | |
| 55 | qcom,saw = <&saw1>; | |
| 06c49f2b | 56 | cpu-idle-states = <&CPU_SPC>; |
| f335b8af KG |
57 | }; |
| 58 | ||
| 7a5c275f | 59 | CPU2: cpu@2 { |
| f335b8af KG |
60 | compatible = "qcom,krait"; |
| 61 | enable-method = "qcom,kpss-acc-v1"; | |
| 62 | device_type = "cpu"; | |
| 63 | reg = <2>; | |
| 64 | next-level-cache = <&L2>; | |
| 65 | qcom,acc = <&acc2>; | |
| 66 | qcom,saw = <&saw2>; | |
| 06c49f2b | 67 | cpu-idle-states = <&CPU_SPC>; |
| f335b8af KG |
68 | }; |
| 69 | ||
| 7a5c275f | 70 | CPU3: cpu@3 { |
| f335b8af KG |
71 | compatible = "qcom,krait"; |
| 72 | enable-method = "qcom,kpss-acc-v1"; | |
| 73 | device_type = "cpu"; | |
| 74 | reg = <3>; | |
| 75 | next-level-cache = <&L2>; | |
| 76 | qcom,acc = <&acc3>; | |
| 77 | qcom,saw = <&saw3>; | |
| 06c49f2b | 78 | cpu-idle-states = <&CPU_SPC>; |
| f335b8af KG |
79 | }; |
| 80 | ||
| 81 | L2: l2-cache { | |
| 82 | compatible = "cache"; | |
| 83 | cache-level = <2>; | |
| 84 | }; | |
| 06c49f2b LI |
85 | |
| 86 | idle-states { | |
| 87 | CPU_SPC: spc { | |
| 88 | compatible = "qcom,idle-state-spc", | |
| 89 | "arm,idle-state"; | |
| 90 | entry-latency-us = <400>; | |
| 91 | exit-latency-us = <900>; | |
| 92 | min-residency-us = <3000>; | |
| 93 | }; | |
| 94 | }; | |
| f335b8af KG |
95 | }; |
| 96 | ||
| c8c87689 RN |
97 | thermal-zones { |
| 98 | cpu-thermal0 { | |
| 99 | polling-delay-passive = <250>; | |
| 100 | polling-delay = <1000>; | |
| 101 | ||
| 102 | thermal-sensors = <&gcc 7>; | |
| 103 | coefficients = <1199 0>; | |
| 104 | ||
| 105 | trips { | |
| 106 | cpu_alert0: trip0 { | |
| 107 | temperature = <75000>; | |
| 108 | hysteresis = <2000>; | |
| 109 | type = "passive"; | |
| 110 | }; | |
| 111 | cpu_crit0: trip1 { | |
| 112 | temperature = <110000>; | |
| 113 | hysteresis = <2000>; | |
| 114 | type = "critical"; | |
| 115 | }; | |
| 116 | }; | |
| 117 | }; | |
| 118 | ||
| 119 | cpu-thermal1 { | |
| 120 | polling-delay-passive = <250>; | |
| 121 | polling-delay = <1000>; | |
| 122 | ||
| 123 | thermal-sensors = <&gcc 8>; | |
| 124 | coefficients = <1132 0>; | |
| 125 | ||
| 126 | trips { | |
| 127 | cpu_alert1: trip0 { | |
| 128 | temperature = <75000>; | |
| 129 | hysteresis = <2000>; | |
| 130 | type = "passive"; | |
| 131 | }; | |
| 132 | cpu_crit1: trip1 { | |
| 133 | temperature = <110000>; | |
| 134 | hysteresis = <2000>; | |
| 135 | type = "critical"; | |
| 136 | }; | |
| 137 | }; | |
| 138 | }; | |
| 139 | ||
| 140 | cpu-thermal2 { | |
| 141 | polling-delay-passive = <250>; | |
| 142 | polling-delay = <1000>; | |
| 143 | ||
| 144 | thermal-sensors = <&gcc 9>; | |
| 145 | coefficients = <1199 0>; | |
| 146 | ||
| 147 | trips { | |
| 148 | cpu_alert2: trip0 { | |
| 149 | temperature = <75000>; | |
| 150 | hysteresis = <2000>; | |
| 151 | type = "passive"; | |
| 152 | }; | |
| 153 | cpu_crit2: trip1 { | |
| 154 | temperature = <110000>; | |
| 155 | hysteresis = <2000>; | |
| 156 | type = "critical"; | |
| 157 | }; | |
| 158 | }; | |
| 159 | }; | |
| 160 | ||
| 161 | cpu-thermal3 { | |
| 162 | polling-delay-passive = <250>; | |
| 163 | polling-delay = <1000>; | |
| 164 | ||
| 165 | thermal-sensors = <&gcc 10>; | |
| 166 | coefficients = <1132 0>; | |
| 167 | ||
| 168 | trips { | |
| 169 | cpu_alert3: trip0 { | |
| 170 | temperature = <75000>; | |
| 171 | hysteresis = <2000>; | |
| 172 | type = "passive"; | |
| 173 | }; | |
| 174 | cpu_crit3: trip1 { | |
| 175 | temperature = <110000>; | |
| 176 | hysteresis = <2000>; | |
| 177 | type = "critical"; | |
| 178 | }; | |
| 179 | }; | |
| 180 | }; | |
| 181 | }; | |
| 182 | ||
| f335b8af KG |
183 | cpu-pmu { |
| 184 | compatible = "qcom,krait-pmu"; | |
| 185 | interrupts = <1 10 0x304>; | |
| 186 | }; | |
| 187 | ||
| aa269127 | 188 | clocks { |
| f9a8aaed | 189 | cxo_board: cxo_board { |
| aa269127 GD |
190 | compatible = "fixed-clock"; |
| 191 | #clock-cells = <0>; | |
| 192 | clock-frequency = <19200000>; | |
| 193 | }; | |
| 194 | ||
| 195 | pxo_board { | |
| 196 | compatible = "fixed-clock"; | |
| 197 | #clock-cells = <0>; | |
| 198 | clock-frequency = <27000000>; | |
| 199 | }; | |
| 200 | ||
| b993292f | 201 | sleep_clk: sleep_clk { |
| aa269127 GD |
202 | compatible = "fixed-clock"; |
| 203 | #clock-cells = <0>; | |
| 204 | clock-frequency = <32768>; | |
| 205 | }; | |
| 206 | }; | |
| 207 | ||
| 24a9baf9 BA |
208 | sfpb_mutex: hwmutex { |
| 209 | compatible = "qcom,sfpb-mutex"; | |
| 210 | syscon = <&sfpb_wrapper_mutex 0x604 0x4>; | |
| 211 | #hwlock-cells = <1>; | |
| 212 | }; | |
| 213 | ||
| 214 | smem { | |
| 215 | compatible = "qcom,smem"; | |
| 216 | memory-region = <&smem_region>; | |
| 217 | ||
| 218 | hwlocks = <&sfpb_mutex 3>; | |
| 219 | }; | |
| 220 | ||
| 2afc5287 BA |
221 | smd { |
| 222 | compatible = "qcom,smd"; | |
| 223 | ||
| 224 | modem@0 { | |
| 225 | interrupts = <0 37 IRQ_TYPE_EDGE_RISING>; | |
| 226 | ||
| 227 | qcom,ipc = <&l2cc 8 3>; | |
| 228 | qcom,smd-edge = <0>; | |
| 229 | ||
| 230 | status = "disabled"; | |
| 231 | }; | |
| 232 | ||
| 233 | q6@1 { | |
| 234 | interrupts = <0 90 IRQ_TYPE_EDGE_RISING>; | |
| 235 | ||
| 236 | qcom,ipc = <&l2cc 8 15>; | |
| 237 | qcom,smd-edge = <1>; | |
| 238 | ||
| 239 | status = "disabled"; | |
| 240 | }; | |
| 241 | ||
| 242 | dsps@3 { | |
| 243 | interrupts = <0 138 IRQ_TYPE_EDGE_RISING>; | |
| 244 | ||
| 245 | qcom,ipc = <&sps_sic_non_secure 0x4080 0>; | |
| 246 | qcom,smd-edge = <3>; | |
| 247 | ||
| 248 | status = "disabled"; | |
| 249 | }; | |
| 250 | ||
| 251 | riva@6 { | |
| 252 | interrupts = <0 198 IRQ_TYPE_EDGE_RISING>; | |
| 253 | ||
| 254 | qcom,ipc = <&l2cc 8 25>; | |
| 255 | qcom,smd-edge = <6>; | |
| 256 | ||
| 257 | status = "disabled"; | |
| 258 | }; | |
| 259 | }; | |
| 260 | ||
| b4d4582f BA |
261 | smsm { |
| 262 | compatible = "qcom,smsm"; | |
| 263 | ||
| 264 | #address-cells = <1>; | |
| 265 | #size-cells = <0>; | |
| 266 | ||
| 267 | qcom,ipc-1 = <&l2cc 8 4>; | |
| 268 | qcom,ipc-2 = <&l2cc 8 14>; | |
| 269 | qcom,ipc-3 = <&l2cc 8 23>; | |
| 270 | qcom,ipc-4 = <&sps_sic_non_secure 0x4094 0>; | |
| 271 | ||
| 272 | apps_smsm: apps@0 { | |
| 273 | reg = <0>; | |
| 30f1e2dd | 274 | #qcom,smem-state-cells = <1>; |
| b4d4582f BA |
275 | }; |
| 276 | ||
| 277 | modem_smsm: modem@1 { | |
| 278 | reg = <1>; | |
| 279 | interrupts = <0 38 IRQ_TYPE_EDGE_RISING>; | |
| 280 | ||
| 281 | interrupt-controller; | |
| 282 | #interrupt-cells = <2>; | |
| 283 | }; | |
| 284 | ||
| 285 | q6_smsm: q6@2 { | |
| 286 | reg = <2>; | |
| 287 | interrupts = <0 89 IRQ_TYPE_EDGE_RISING>; | |
| 288 | ||
| 289 | interrupt-controller; | |
| 290 | #interrupt-cells = <2>; | |
| 291 | }; | |
| 292 | ||
| 293 | wcnss_smsm: wcnss@3 { | |
| 294 | reg = <3>; | |
| 295 | interrupts = <0 204 IRQ_TYPE_EDGE_RISING>; | |
| 296 | ||
| 297 | interrupt-controller; | |
| 298 | #interrupt-cells = <2>; | |
| 299 | }; | |
| 300 | ||
| 301 | dsps_smsm: dsps@4 { | |
| 302 | reg = <4>; | |
| 303 | interrupts = <0 137 IRQ_TYPE_EDGE_RISING>; | |
| 304 | ||
| 305 | interrupt-controller; | |
| 306 | #interrupt-cells = <2>; | |
| 307 | }; | |
| 308 | }; | |
| 309 | ||
| 9e5d41d4 AG |
310 | firmware { |
| 311 | scm { | |
| 312 | compatible = "qcom,scm-apq8064"; | |
| 542b9f07 BA |
313 | |
| 314 | clocks = <&rpmcc RPM_DAYTONA_FABRIC_CLK>; | |
| 315 | clock-names = "core"; | |
| 9e5d41d4 AG |
316 | }; |
| 317 | }; | |
| 318 | ||
| f335b8af KG |
319 | soc: soc { |
| 320 | #address-cells = <1>; | |
| 321 | #size-cells = <1>; | |
| 322 | ranges; | |
| 323 | compatible = "simple-bus"; | |
| 324 | ||
| 8b8936fc PG |
325 | tlmm_pinmux: pinctrl@800000 { |
| 326 | compatible = "qcom,apq8064-pinctrl"; | |
| 327 | reg = <0x800000 0x4000>; | |
| 328 | ||
| 329 | gpio-controller; | |
| 330 | #gpio-cells = <2>; | |
| 331 | interrupt-controller; | |
| 332 | #interrupt-cells = <2>; | |
| 333 | interrupts = <0 16 IRQ_TYPE_LEVEL_HIGH>; | |
| cd6dd11a PG |
334 | |
| 335 | pinctrl-names = "default"; | |
| 336 | pinctrl-0 = <&ps_hold>; | |
| 8b8936fc PG |
337 | }; |
| 338 | ||
| 24a9baf9 BA |
339 | sfpb_wrapper_mutex: syscon@1200000 { |
| 340 | compatible = "syscon"; | |
| 341 | reg = <0x01200000 0x8000>; | |
| 342 | }; | |
| 343 | ||
| f335b8af KG |
344 | intc: interrupt-controller@2000000 { |
| 345 | compatible = "qcom,msm-qgic2"; | |
| 346 | interrupt-controller; | |
| 347 | #interrupt-cells = <3>; | |
| 348 | reg = <0x02000000 0x1000>, | |
| 349 | <0x02002000 0x1000>; | |
| 350 | }; | |
| 351 | ||
| 352 | timer@200a000 { | |
| 6e062696 MM |
353 | compatible = "qcom,kpss-timer", |
| 354 | "qcom,kpss-wdt-apq8064", "qcom,msm-timer"; | |
| f335b8af KG |
355 | interrupts = <1 1 0x301>, |
| 356 | <1 2 0x301>, | |
| 357 | <1 3 0x301>; | |
| 358 | reg = <0x0200a000 0x100>; | |
| 359 | clock-frequency = <27000000>, | |
| 360 | <32768>; | |
| 361 | cpu-offset = <0x80000>; | |
| 362 | }; | |
| 363 | ||
| 364 | acc0: clock-controller@2088000 { | |
| 365 | compatible = "qcom,kpss-acc-v1"; | |
| 366 | reg = <0x02088000 0x1000>, <0x02008000 0x1000>; | |
| 367 | }; | |
| 368 | ||
| 369 | acc1: clock-controller@2098000 { | |
| 370 | compatible = "qcom,kpss-acc-v1"; | |
| 371 | reg = <0x02098000 0x1000>, <0x02008000 0x1000>; | |
| 372 | }; | |
| 373 | ||
| 374 | acc2: clock-controller@20a8000 { | |
| 375 | compatible = "qcom,kpss-acc-v1"; | |
| 376 | reg = <0x020a8000 0x1000>, <0x02008000 0x1000>; | |
| 377 | }; | |
| 378 | ||
| 379 | acc3: clock-controller@20b8000 { | |
| 380 | compatible = "qcom,kpss-acc-v1"; | |
| 381 | reg = <0x020b8000 0x1000>, <0x02008000 0x1000>; | |
| 382 | }; | |
| 383 | ||
| 9fc23ce3 LI |
384 | saw0: power-controller@2089000 { |
| 385 | compatible = "qcom,apq8064-saw2-v1.1-cpu", "qcom,saw2"; | |
| f335b8af KG |
386 | reg = <0x02089000 0x1000>, <0x02009000 0x1000>; |
| 387 | regulator; | |
| 388 | }; | |
| 389 | ||
| 9fc23ce3 LI |
390 | saw1: power-controller@2099000 { |
| 391 | compatible = "qcom,apq8064-saw2-v1.1-cpu", "qcom,saw2"; | |
| f335b8af KG |
392 | reg = <0x02099000 0x1000>, <0x02009000 0x1000>; |
| 393 | regulator; | |
| 394 | }; | |
| 395 | ||
| 9fc23ce3 LI |
396 | saw2: power-controller@20a9000 { |
| 397 | compatible = "qcom,apq8064-saw2-v1.1-cpu", "qcom,saw2"; | |
| f335b8af KG |
398 | reg = <0x020a9000 0x1000>, <0x02009000 0x1000>; |
| 399 | regulator; | |
| 400 | }; | |
| 401 | ||
| 9fc23ce3 LI |
402 | saw3: power-controller@20b9000 { |
| 403 | compatible = "qcom,apq8064-saw2-v1.1-cpu", "qcom,saw2"; | |
| f335b8af KG |
404 | reg = <0x020b9000 0x1000>, <0x02009000 0x1000>; |
| 405 | regulator; | |
| 406 | }; | |
| 407 | ||
| b9e4c5e6 BA |
408 | sps_sic_non_secure: sps-sic-non-secure@12100000 { |
| 409 | compatible = "syscon"; | |
| 410 | reg = <0x12100000 0x10000>; | |
| 411 | }; | |
| 412 | ||
| 8c3166f5 | 413 | gsbi1: gsbi@12440000 { |
| 414 | status = "disabled"; | |
| 415 | compatible = "qcom,gsbi-v1.0.0"; | |
| 4105d9d6 | 416 | cell-index = <1>; |
| 8c3166f5 | 417 | reg = <0x12440000 0x100>; |
| 418 | clocks = <&gcc GSBI1_H_CLK>; | |
| 419 | clock-names = "iface"; | |
| 420 | #address-cells = <1>; | |
| 421 | #size-cells = <1>; | |
| 422 | ranges; | |
| 423 | ||
| 4105d9d6 AG |
424 | syscon-tcsr = <&tcsr>; |
| 425 | ||
| 12861674 SK |
426 | gsbi1_serial: serial@12450000 { |
| 427 | compatible = "qcom,msm-uartdm-v1.3", "qcom,msm-uartdm"; | |
| 428 | reg = <0x12450000 0x100>, | |
| 429 | <0x12400000 0x03>; | |
| 430 | interrupts = <0 193 0x0>; | |
| 431 | clocks = <&gcc GSBI1_UART_CLK>, <&gcc GSBI1_H_CLK>; | |
| 432 | clock-names = "core", "iface"; | |
| 433 | status = "disabled"; | |
| 434 | }; | |
| 435 | ||
| e07214db | 436 | gsbi1_i2c: i2c@12460000 { |
| 8c3166f5 | 437 | compatible = "qcom,i2c-qup-v1.1.1"; |
| 67b5ad57 SK |
438 | pinctrl-0 = <&i2c1_pins>; |
| 439 | pinctrl-1 = <&i2c1_pins_sleep>; | |
| 64b22b25 | 440 | pinctrl-names = "default", "sleep"; |
| 8c3166f5 | 441 | reg = <0x12460000 0x1000>; |
| 442 | interrupts = <0 194 IRQ_TYPE_NONE>; | |
| 443 | clocks = <&gcc GSBI1_QUP_CLK>, <&gcc GSBI1_H_CLK>; | |
| 444 | clock-names = "core", "iface"; | |
| 445 | #address-cells = <1>; | |
| 446 | #size-cells = <0>; | |
| 447 | }; | |
| b2dc04c5 | 448 | |
| 8c3166f5 | 449 | }; |
| 450 | ||
| 451 | gsbi2: gsbi@12480000 { | |
| 452 | status = "disabled"; | |
| 453 | compatible = "qcom,gsbi-v1.0.0"; | |
| 4105d9d6 | 454 | cell-index = <2>; |
| 8c3166f5 | 455 | reg = <0x12480000 0x100>; |
| 456 | clocks = <&gcc GSBI2_H_CLK>; | |
| 457 | clock-names = "iface"; | |
| 458 | #address-cells = <1>; | |
| 459 | #size-cells = <1>; | |
| 460 | ranges; | |
| 461 | ||
| 4105d9d6 AG |
462 | syscon-tcsr = <&tcsr>; |
| 463 | ||
| e07214db | 464 | gsbi2_i2c: i2c@124a0000 { |
| 8c3166f5 | 465 | compatible = "qcom,i2c-qup-v1.1.1"; |
| 466 | reg = <0x124a0000 0x1000>; | |
| 67b5ad57 SK |
467 | pinctrl-0 = <&i2c2_pins>; |
| 468 | pinctrl-1 = <&i2c2_pins_sleep>; | |
| 7788d439 | 469 | pinctrl-names = "default", "sleep"; |
| 8c3166f5 | 470 | interrupts = <0 196 IRQ_TYPE_NONE>; |
| 471 | clocks = <&gcc GSBI2_QUP_CLK>, <&gcc GSBI2_H_CLK>; | |
| 472 | clock-names = "core", "iface"; | |
| 473 | #address-cells = <1>; | |
| 474 | #size-cells = <0>; | |
| 475 | }; | |
| 476 | }; | |
| 477 | ||
| 3f62b46b SK |
478 | gsbi3: gsbi@16200000 { |
| 479 | status = "disabled"; | |
| 480 | compatible = "qcom,gsbi-v1.0.0"; | |
| 504155ca | 481 | cell-index = <3>; |
| 3f62b46b SK |
482 | reg = <0x16200000 0x100>; |
| 483 | clocks = <&gcc GSBI3_H_CLK>; | |
| 484 | clock-names = "iface"; | |
| 485 | #address-cells = <1>; | |
| 486 | #size-cells = <1>; | |
| 487 | ranges; | |
| e07214db | 488 | gsbi3_i2c: i2c@16280000 { |
| 3f62b46b | 489 | compatible = "qcom,i2c-qup-v1.1.1"; |
| 67b5ad57 SK |
490 | pinctrl-0 = <&i2c3_pins>; |
| 491 | pinctrl-1 = <&i2c3_pins_sleep>; | |
| 64b22b25 | 492 | pinctrl-names = "default", "sleep"; |
| 3f62b46b SK |
493 | reg = <0x16280000 0x1000>; |
| 494 | interrupts = <GIC_SPI 151 IRQ_TYPE_NONE>; | |
| 495 | clocks = <&gcc GSBI3_QUP_CLK>, | |
| 496 | <&gcc GSBI3_H_CLK>; | |
| 497 | clock-names = "core", "iface"; | |
| 5d31f606 JS |
498 | #address-cells = <1>; |
| 499 | #size-cells = <0>; | |
| 1099b26e BA |
500 | }; |
| 501 | }; | |
| 502 | ||
| 2a5cbc15 SK |
503 | gsbi4: gsbi@16300000 { |
| 504 | status = "disabled"; | |
| 505 | compatible = "qcom,gsbi-v1.0.0"; | |
| 506 | cell-index = <4>; | |
| 507 | reg = <0x16300000 0x03>; | |
| 508 | clocks = <&gcc GSBI4_H_CLK>; | |
| 509 | clock-names = "iface"; | |
| 510 | #address-cells = <1>; | |
| 511 | #size-cells = <1>; | |
| 512 | ranges; | |
| 513 | ||
| 514 | gsbi4_i2c: i2c@16380000 { | |
| 515 | compatible = "qcom,i2c-qup-v1.1.1"; | |
| 67b5ad57 SK |
516 | pinctrl-0 = <&i2c4_pins>; |
| 517 | pinctrl-1 = <&i2c4_pins_sleep>; | |
| 2a5cbc15 SK |
518 | pinctrl-names = "default", "sleep"; |
| 519 | reg = <0x16380000 0x1000>; | |
| 520 | interrupts = <GIC_SPI 153 IRQ_TYPE_NONE>; | |
| 521 | clocks = <&gcc GSBI4_QUP_CLK>, | |
| 522 | <&gcc GSBI4_H_CLK>; | |
| 523 | clock-names = "core", "iface"; | |
| 524 | }; | |
| 525 | }; | |
| 526 | ||
| 1099b26e BA |
527 | gsbi5: gsbi@1a200000 { |
| 528 | status = "disabled"; | |
| 529 | compatible = "qcom,gsbi-v1.0.0"; | |
| 530 | cell-index = <5>; | |
| 531 | reg = <0x1a200000 0x03>; | |
| 532 | clocks = <&gcc GSBI5_H_CLK>; | |
| 533 | clock-names = "iface"; | |
| 534 | #address-cells = <1>; | |
| 535 | #size-cells = <1>; | |
| 536 | ranges; | |
| 537 | ||
| 538 | gsbi5_serial: serial@1a240000 { | |
| 539 | compatible = "qcom,msm-uartdm-v1.3", "qcom,msm-uartdm"; | |
| 540 | reg = <0x1a240000 0x100>, | |
| 541 | <0x1a200000 0x03>; | |
| 542 | interrupts = <0 154 0x0>; | |
| 543 | clocks = <&gcc GSBI5_UART_CLK>, <&gcc GSBI5_H_CLK>; | |
| 544 | clock-names = "core", "iface"; | |
| 545 | status = "disabled"; | |
| 3f62b46b | 546 | }; |
| b2dc04c5 SK |
547 | |
| 548 | gsbi5_spi: spi@1a280000 { | |
| 549 | compatible = "qcom,spi-qup-v1.1.1"; | |
| 550 | reg = <0x1a280000 0x1000>; | |
| 551 | interrupts = <0 155 0>; | |
| 67b5ad57 SK |
552 | pinctrl-0 = <&spi5_default>; |
| 553 | pinctrl-1 = <&spi5_sleep>; | |
| b2dc04c5 SK |
554 | pinctrl-names = "default", "sleep"; |
| 555 | clocks = <&gcc GSBI5_QUP_CLK>, <&gcc GSBI5_H_CLK>; | |
| 556 | clock-names = "core", "iface"; | |
| 557 | status = "disabled"; | |
| 558 | #address-cells = <1>; | |
| 559 | #size-cells = <0>; | |
| 560 | }; | |
| 3f62b46b SK |
561 | }; |
| 562 | ||
| 86e252a4 PG |
563 | gsbi6: gsbi@16500000 { |
| 564 | status = "disabled"; | |
| 565 | compatible = "qcom,gsbi-v1.0.0"; | |
| 566 | cell-index = <6>; | |
| 567 | reg = <0x16500000 0x03>; | |
| 568 | clocks = <&gcc GSBI6_H_CLK>; | |
| 569 | clock-names = "iface"; | |
| 570 | #address-cells = <1>; | |
| 571 | #size-cells = <1>; | |
| 572 | ranges; | |
| 573 | ||
| 574 | gsbi6_serial: serial@16540000 { | |
| 575 | compatible = "qcom,msm-uartdm-v1.3", "qcom,msm-uartdm"; | |
| 576 | reg = <0x16540000 0x100>, | |
| 577 | <0x16500000 0x03>; | |
| 578 | interrupts = <0 156 0x0>; | |
| 579 | clocks = <&gcc GSBI6_UART_CLK>, <&gcc GSBI6_H_CLK>; | |
| 580 | clock-names = "core", "iface"; | |
| 581 | status = "disabled"; | |
| 582 | }; | |
| 806334ed SK |
583 | |
| 584 | gsbi6_i2c: i2c@16580000 { | |
| 585 | compatible = "qcom,i2c-qup-v1.1.1"; | |
| 67b5ad57 SK |
586 | pinctrl-0 = <&i2c6_pins>; |
| 587 | pinctrl-1 = <&i2c6_pins_sleep>; | |
| 806334ed SK |
588 | pinctrl-names = "default", "sleep"; |
| 589 | reg = <0x16580000 0x1000>; | |
| 590 | interrupts = <GIC_SPI 157 IRQ_TYPE_NONE>; | |
| 591 | clocks = <&gcc GSBI6_QUP_CLK>, | |
| 592 | <&gcc GSBI6_H_CLK>; | |
| 593 | clock-names = "core", "iface"; | |
| fb83f201 | 594 | status = "disabled"; |
| 806334ed | 595 | }; |
| 86e252a4 PG |
596 | }; |
| 597 | ||
| f335b8af KG |
598 | gsbi7: gsbi@16600000 { |
| 599 | status = "disabled"; | |
| 600 | compatible = "qcom,gsbi-v1.0.0"; | |
| 4105d9d6 | 601 | cell-index = <7>; |
| f335b8af KG |
602 | reg = <0x16600000 0x100>; |
| 603 | clocks = <&gcc GSBI7_H_CLK>; | |
| 604 | clock-names = "iface"; | |
| 605 | #address-cells = <1>; | |
| 606 | #size-cells = <1>; | |
| 607 | ranges; | |
| 4105d9d6 AG |
608 | syscon-tcsr = <&tcsr>; |
| 609 | ||
| d5d4654e | 610 | gsbi7_serial: serial@16640000 { |
| f335b8af KG |
611 | compatible = "qcom,msm-uartdm-v1.3", "qcom,msm-uartdm"; |
| 612 | reg = <0x16640000 0x1000>, | |
| 613 | <0x16600000 0x1000>; | |
| 614 | interrupts = <0 158 0x0>; | |
| 615 | clocks = <&gcc GSBI7_UART_CLK>, <&gcc GSBI7_H_CLK>; | |
| 616 | clock-names = "core", "iface"; | |
| 617 | status = "disabled"; | |
| 618 | }; | |
| e4b01fda SK |
619 | |
| 620 | gsbi7_i2c: i2c@16680000 { | |
| 621 | compatible = "qcom,i2c-qup-v1.1.1"; | |
| 622 | pinctrl-0 = <&i2c7_pins>; | |
| 623 | pinctrl-1 = <&i2c7_pins_sleep>; | |
| 624 | pinctrl-names = "default", "sleep"; | |
| 625 | reg = <0x16680000 0x1000>; | |
| 626 | interrupts = <GIC_SPI 159 IRQ_TYPE_NONE>; | |
| 627 | clocks = <&gcc GSBI7_QUP_CLK>, | |
| 628 | <&gcc GSBI7_H_CLK>; | |
| 629 | clock-names = "core", "iface"; | |
| 630 | status = "disabled"; | |
| 631 | }; | |
| f335b8af KG |
632 | }; |
| 633 | ||
| 6a607e03 JS |
634 | rng@1a500000 { |
| 635 | compatible = "qcom,prng"; | |
| 636 | reg = <0x1a500000 0x200>; | |
| 637 | clocks = <&gcc PRNG_CLK>; | |
| 638 | clock-names = "core"; | |
| 639 | }; | |
| 640 | ||
| 4123366a SK |
641 | ssbi@c00000 { |
| 642 | compatible = "qcom,ssbi"; | |
| 643 | reg = <0x00c00000 0x1000>; | |
| 644 | qcom,controller-type = "pmic-arbiter"; | |
| 645 | ||
| 646 | pm8821: pmic@1 { | |
| 647 | compatible = "qcom,pm8821"; | |
| 648 | interrupt-parent = <&tlmm_pinmux>; | |
| 649 | interrupts = <76 IRQ_TYPE_LEVEL_LOW>; | |
| 650 | #interrupt-cells = <2>; | |
| 651 | interrupt-controller; | |
| 652 | #address-cells = <1>; | |
| 653 | #size-cells = <0>; | |
| 654 | ||
| 655 | pm8821_mpps: mpps@50 { | |
| 656 | compatible = "qcom,pm8821-mpp", "qcom,ssbi-mpp"; | |
| 657 | reg = <0x50>; | |
| 658 | interrupts = <24 IRQ_TYPE_NONE>, | |
| 659 | <25 IRQ_TYPE_NONE>, | |
| 660 | <26 IRQ_TYPE_NONE>, | |
| 661 | <27 IRQ_TYPE_NONE>; | |
| 662 | gpio-controller; | |
| 663 | #gpio-cells = <2>; | |
| 664 | }; | |
| 665 | }; | |
| 666 | }; | |
| 667 | ||
| f335b8af KG |
668 | qcom,ssbi@500000 { |
| 669 | compatible = "qcom,ssbi"; | |
| 670 | reg = <0x00500000 0x1000>; | |
| 671 | qcom,controller-type = "pmic-arbiter"; | |
| 874443fe SK |
672 | |
| 673 | pmicintc: pmic@0 { | |
| 674 | compatible = "qcom,pm8921"; | |
| 675 | interrupt-parent = <&tlmm_pinmux>; | |
| 676 | interrupts = <74 8>; | |
| 677 | #interrupt-cells = <2>; | |
| 678 | interrupt-controller; | |
| 679 | #address-cells = <1>; | |
| 680 | #size-cells = <0>; | |
| 681 | ||
| 682 | pm8921_gpio: gpio@150 { | |
| 683 | ||
| 2ca9c2a4 SB |
684 | compatible = "qcom,pm8921-gpio", |
| 685 | "qcom,ssbi-gpio"; | |
| 874443fe | 686 | reg = <0x150>; |
| ca88696e LW |
687 | interrupts = <192 IRQ_TYPE_NONE>, |
| 688 | <193 IRQ_TYPE_NONE>, | |
| 689 | <194 IRQ_TYPE_NONE>, | |
| 690 | <195 IRQ_TYPE_NONE>, | |
| 691 | <196 IRQ_TYPE_NONE>, | |
| 692 | <197 IRQ_TYPE_NONE>, | |
| 693 | <198 IRQ_TYPE_NONE>, | |
| 694 | <199 IRQ_TYPE_NONE>, | |
| 695 | <200 IRQ_TYPE_NONE>, | |
| 696 | <201 IRQ_TYPE_NONE>, | |
| 697 | <202 IRQ_TYPE_NONE>, | |
| 698 | <203 IRQ_TYPE_NONE>, | |
| 699 | <204 IRQ_TYPE_NONE>, | |
| 700 | <205 IRQ_TYPE_NONE>, | |
| 701 | <206 IRQ_TYPE_NONE>, | |
| 702 | <207 IRQ_TYPE_NONE>, | |
| 703 | <208 IRQ_TYPE_NONE>, | |
| 704 | <209 IRQ_TYPE_NONE>, | |
| 705 | <210 IRQ_TYPE_NONE>, | |
| 706 | <211 IRQ_TYPE_NONE>, | |
| 707 | <212 IRQ_TYPE_NONE>, | |
| 708 | <213 IRQ_TYPE_NONE>, | |
| 709 | <214 IRQ_TYPE_NONE>, | |
| 710 | <215 IRQ_TYPE_NONE>, | |
| 711 | <216 IRQ_TYPE_NONE>, | |
| 712 | <217 IRQ_TYPE_NONE>, | |
| 713 | <218 IRQ_TYPE_NONE>, | |
| 714 | <219 IRQ_TYPE_NONE>, | |
| 715 | <220 IRQ_TYPE_NONE>, | |
| 716 | <221 IRQ_TYPE_NONE>, | |
| 717 | <222 IRQ_TYPE_NONE>, | |
| 718 | <223 IRQ_TYPE_NONE>, | |
| 719 | <224 IRQ_TYPE_NONE>, | |
| 720 | <225 IRQ_TYPE_NONE>, | |
| 721 | <226 IRQ_TYPE_NONE>, | |
| 722 | <227 IRQ_TYPE_NONE>, | |
| 723 | <228 IRQ_TYPE_NONE>, | |
| 724 | <229 IRQ_TYPE_NONE>, | |
| 725 | <230 IRQ_TYPE_NONE>, | |
| 726 | <231 IRQ_TYPE_NONE>, | |
| 727 | <232 IRQ_TYPE_NONE>, | |
| 728 | <233 IRQ_TYPE_NONE>, | |
| 729 | <234 IRQ_TYPE_NONE>, | |
| 730 | <235 IRQ_TYPE_NONE>; | |
| 874443fe SK |
731 | gpio-controller; |
| 732 | #gpio-cells = <2>; | |
| 733 | ||
| 734 | }; | |
| bce36046 SK |
735 | |
| 736 | pm8921_mpps: mpps@50 { | |
| 2ca9c2a4 SB |
737 | compatible = "qcom,pm8921-mpp", |
| 738 | "qcom,ssbi-mpp"; | |
| bce36046 SK |
739 | reg = <0x50>; |
| 740 | gpio-controller; | |
| 741 | #gpio-cells = <2>; | |
| 742 | interrupts = | |
| ca88696e LW |
743 | <128 IRQ_TYPE_NONE>, |
| 744 | <129 IRQ_TYPE_NONE>, | |
| 745 | <130 IRQ_TYPE_NONE>, | |
| 746 | <131 IRQ_TYPE_NONE>, | |
| 747 | <132 IRQ_TYPE_NONE>, | |
| 748 | <133 IRQ_TYPE_NONE>, | |
| 749 | <134 IRQ_TYPE_NONE>, | |
| 750 | <135 IRQ_TYPE_NONE>, | |
| 751 | <136 IRQ_TYPE_NONE>, | |
| 752 | <137 IRQ_TYPE_NONE>, | |
| 753 | <138 IRQ_TYPE_NONE>, | |
| 754 | <139 IRQ_TYPE_NONE>; | |
| bce36046 SK |
755 | }; |
| 756 | ||
| bbf89b96 SK |
757 | rtc@11d { |
| 758 | compatible = "qcom,pm8921-rtc"; | |
| 759 | interrupt-parent = <&pmicintc>; | |
| 760 | interrupts = <39 1>; | |
| 761 | reg = <0x11d>; | |
| 762 | allow-set-time; | |
| 763 | }; | |
| 764 | ||
| 3050c5f5 SK |
765 | pwrkey@1c { |
| 766 | compatible = "qcom,pm8921-pwrkey"; | |
| 767 | reg = <0x1c>; | |
| 768 | interrupt-parent = <&pmicintc>; | |
| 769 | interrupts = <50 1>, <51 1>; | |
| 770 | debounce = <15625>; | |
| 771 | pull-up; | |
| 772 | }; | |
| 874443fe | 773 | }; |
| f335b8af KG |
774 | }; |
| 775 | ||
| c8c87689 RN |
776 | qfprom: qfprom@700000 { |
| 777 | compatible = "qcom,qfprom"; | |
| 778 | reg = <0x00700000 0x1000>; | |
| 779 | #address-cells = <1>; | |
| 780 | #size-cells = <1>; | |
| 781 | ranges; | |
| 782 | tsens_calib: calib { | |
| 783 | reg = <0x404 0x10>; | |
| 784 | }; | |
| 785 | tsens_backup: backup_calib { | |
| 786 | reg = <0x414 0x10>; | |
| 787 | }; | |
| 788 | }; | |
| 789 | ||
| f335b8af KG |
790 | gcc: clock-controller@900000 { |
| 791 | compatible = "qcom,gcc-apq8064"; | |
| 792 | reg = <0x00900000 0x4000>; | |
| c8c87689 RN |
793 | nvmem-cells = <&tsens_calib>, <&tsens_backup>; |
| 794 | nvmem-cell-names = "calib", "calib_backup"; | |
| f335b8af KG |
795 | #clock-cells = <1>; |
| 796 | #reset-cells = <1>; | |
| c8c87689 | 797 | #thermal-sensor-cells = <1>; |
| f335b8af | 798 | }; |
| 3fe5e3ce | 799 | |
| 1e1177bf KG |
800 | lcc: clock-controller@28000000 { |
| 801 | compatible = "qcom,lcc-apq8064"; | |
| 802 | reg = <0x28000000 0x1000>; | |
| 803 | #clock-cells = <1>; | |
| 804 | #reset-cells = <1>; | |
| 805 | }; | |
| 806 | ||
| 3fe5e3ce SB |
807 | mmcc: clock-controller@4000000 { |
| 808 | compatible = "qcom,mmcc-apq8064"; | |
| 809 | reg = <0x4000000 0x1000>; | |
| 810 | #clock-cells = <1>; | |
| 811 | #reset-cells = <1>; | |
| 812 | }; | |
| 045644ff | 813 | |
| dc2f8152 SK |
814 | l2cc: clock-controller@2011000 { |
| 815 | compatible = "syscon"; | |
| 816 | reg = <0x2011000 0x1000>; | |
| 817 | }; | |
| 818 | ||
| 819 | rpm@108000 { | |
| 820 | compatible = "qcom,rpm-apq8064"; | |
| 821 | reg = <0x108000 0x1000>; | |
| 822 | qcom,ipc = <&l2cc 0x8 2>; | |
| 823 | ||
| 824 | interrupts = <GIC_SPI 19 IRQ_TYPE_EDGE_RISING>, | |
| 825 | <GIC_SPI 21 IRQ_TYPE_EDGE_RISING>, | |
| 826 | <GIC_SPI 22 IRQ_TYPE_EDGE_RISING>; | |
| 827 | interrupt-names = "ack", "err", "wakeup"; | |
| 828 | ||
| aac1b297 GD |
829 | rpmcc: clock-controller { |
| 830 | compatible = "qcom,rpmcc-apq8064", "qcom,rpmcc"; | |
| 831 | #clock-cells = <1>; | |
| 832 | }; | |
| 833 | ||
| dc2f8152 SK |
834 | regulators { |
| 835 | compatible = "qcom,rpm-pm8921-regulators"; | |
| 836 | ||
| 2bce6e26 BA |
837 | pm8921_s1: s1 {}; |
| 838 | pm8921_s2: s2 {}; | |
| 839 | pm8921_s3: s3 {}; | |
| 840 | pm8921_s4: s4 {}; | |
| 841 | pm8921_s7: s7 {}; | |
| 842 | pm8921_s8: s8 {}; | |
| 843 | ||
| 844 | pm8921_l1: l1 {}; | |
| 845 | pm8921_l2: l2 {}; | |
| 846 | pm8921_l3: l3 {}; | |
| 847 | pm8921_l4: l4 {}; | |
| 848 | pm8921_l5: l5 {}; | |
| 849 | pm8921_l6: l6 {}; | |
| 850 | pm8921_l7: l7 {}; | |
| 851 | pm8921_l8: l8 {}; | |
| 852 | pm8921_l9: l9 {}; | |
| 853 | pm8921_l10: l10 {}; | |
| 854 | pm8921_l11: l11 {}; | |
| 855 | pm8921_l12: l12 {}; | |
| 856 | pm8921_l14: l14 {}; | |
| 857 | pm8921_l15: l15 {}; | |
| 858 | pm8921_l16: l16 {}; | |
| 859 | pm8921_l17: l17 {}; | |
| 860 | pm8921_l18: l18 {}; | |
| 861 | pm8921_l21: l21 {}; | |
| 862 | pm8921_l22: l22 {}; | |
| 863 | pm8921_l23: l23 {}; | |
| 864 | pm8921_l24: l24 {}; | |
| 865 | pm8921_l25: l25 {}; | |
| 866 | pm8921_l26: l26 {}; | |
| 867 | pm8921_l27: l27 {}; | |
| 868 | pm8921_l28: l28 {}; | |
| 869 | pm8921_l29: l29 {}; | |
| 870 | ||
| 871 | pm8921_lvs1: lvs1 {}; | |
| 872 | pm8921_lvs2: lvs2 {}; | |
| 873 | pm8921_lvs3: lvs3 {}; | |
| 874 | pm8921_lvs4: lvs4 {}; | |
| 875 | pm8921_lvs5: lvs5 {}; | |
| 876 | pm8921_lvs6: lvs6 {}; | |
| 877 | pm8921_lvs7: lvs7 {}; | |
| 878 | ||
| 879 | pm8921_usb_switch: usb-switch {}; | |
| 880 | ||
| dc2f8152 SK |
881 | pm8921_hdmi_switch: hdmi-switch { |
| 882 | bias-pull-down; | |
| 883 | }; | |
| 2bce6e26 BA |
884 | |
| 885 | pm8921_ncp: ncp {}; | |
| dc2f8152 SK |
886 | }; |
| 887 | }; | |
| 888 | ||
| ea986611 | 889 | usb1: usb@12500000 { |
| b993292f SB |
890 | compatible = "qcom,ci-hdrc"; |
| 891 | reg = <0x12500000 0x200>, | |
| 892 | <0x12500200 0x200>; | |
| 893 | interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>; | |
| 894 | clocks = <&gcc USB_HS1_XCVR_CLK>, <&gcc USB_HS1_H_CLK>; | |
| 895 | clock-names = "core", "iface"; | |
| 896 | assigned-clocks = <&gcc USB_HS1_XCVR_CLK>; | |
| 897 | assigned-clock-rates = <60000000>; | |
| 898 | resets = <&gcc USB_HS1_RESET>; | |
| 899 | reset-names = "core"; | |
| 900 | phy_type = "ulpi"; | |
| 901 | ahb-burst-config = <0>; | |
| 902 | phys = <&usb_hs1_phy>; | |
| 903 | phy-names = "usb-phy"; | |
| 904 | status = "disabled"; | |
| 905 | #reset-cells = <1>; | |
| 906 | ||
| 907 | ulpi { | |
| 908 | usb_hs1_phy: phy { | |
| 909 | compatible = "qcom,usb-hs-phy-apq8064", | |
| 910 | "qcom,usb-hs-phy"; | |
| b993292f SB |
911 | clocks = <&sleep_clk>, <&cxo_board>; |
| 912 | clock-names = "sleep", "ref"; | |
| 913 | resets = <&usb1 0>; | |
| 914 | reset-names = "por"; | |
| 3191b5b3 | 915 | #phy-cells = <0>; |
| b993292f SB |
916 | }; |
| 917 | }; | |
| ea986611 SK |
918 | }; |
| 919 | ||
| 223280b1 | 920 | usb3: usb@12520000 { |
| b993292f SB |
921 | compatible = "qcom,ci-hdrc"; |
| 922 | reg = <0x12520000 0x200>, | |
| 923 | <0x12520200 0x200>; | |
| 924 | interrupts = <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>; | |
| 925 | clocks = <&gcc USB_HS3_XCVR_CLK>, <&gcc USB_HS3_H_CLK>; | |
| 926 | clock-names = "core", "iface"; | |
| 927 | assigned-clocks = <&gcc USB_HS3_XCVR_CLK>; | |
| 928 | assigned-clock-rates = <60000000>; | |
| 929 | resets = <&gcc USB_HS3_RESET>; | |
| 930 | reset-names = "core"; | |
| 931 | phy_type = "ulpi"; | |
| 932 | ahb-burst-config = <0>; | |
| 933 | phys = <&usb_hs3_phy>; | |
| 934 | phy-names = "usb-phy"; | |
| 935 | status = "disabled"; | |
| 936 | #reset-cells = <1>; | |
| 937 | ||
| 938 | ulpi { | |
| 939 | usb_hs3_phy: phy { | |
| 940 | compatible = "qcom,usb-hs-phy-apq8064", | |
| 941 | "qcom,usb-hs-phy"; | |
| 942 | #phy-cells = <0>; | |
| 943 | clocks = <&sleep_clk>, <&cxo_board>; | |
| 944 | clock-names = "sleep", "ref"; | |
| 945 | resets = <&usb3 0>; | |
| 946 | reset-names = "por"; | |
| 947 | }; | |
| 948 | }; | |
| 223280b1 SK |
949 | }; |
| 950 | ||
| 951 | usb4: usb@12530000 { | |
| b993292f SB |
952 | compatible = "qcom,ci-hdrc"; |
| 953 | reg = <0x12530000 0x200>, | |
| 954 | <0x12530200 0x200>; | |
| 955 | interrupts = <GIC_SPI 215 IRQ_TYPE_LEVEL_HIGH>; | |
| 956 | clocks = <&gcc USB_HS4_XCVR_CLK>, <&gcc USB_HS4_H_CLK>; | |
| 957 | clock-names = "core", "iface"; | |
| 958 | assigned-clocks = <&gcc USB_HS4_XCVR_CLK>; | |
| 959 | assigned-clock-rates = <60000000>; | |
| 960 | resets = <&gcc USB_HS4_RESET>; | |
| 961 | reset-names = "core"; | |
| 962 | phy_type = "ulpi"; | |
| 963 | ahb-burst-config = <0>; | |
| 964 | phys = <&usb_hs4_phy>; | |
| 965 | phy-names = "usb-phy"; | |
| 966 | status = "disabled"; | |
| 967 | #reset-cells = <1>; | |
| 968 | ||
| 969 | ulpi { | |
| 970 | usb_hs4_phy: phy { | |
| 971 | compatible = "qcom,usb-hs-phy-apq8064", | |
| 972 | "qcom,usb-hs-phy"; | |
| 973 | #phy-cells = <0>; | |
| 974 | clocks = <&sleep_clk>, <&cxo_board>; | |
| 975 | clock-names = "sleep", "ref"; | |
| 976 | resets = <&usb4 0>; | |
| 977 | reset-names = "por"; | |
| 978 | }; | |
| 979 | }; | |
| 223280b1 SK |
980 | }; |
| 981 | ||
| e629335f SK |
982 | sata_phy0: phy@1b400000 { |
| 983 | compatible = "qcom,apq8064-sata-phy"; | |
| 984 | status = "disabled"; | |
| 985 | reg = <0x1b400000 0x200>; | |
| 986 | reg-names = "phy_mem"; | |
| 987 | clocks = <&gcc SATA_PHY_CFG_CLK>; | |
| 988 | clock-names = "cfg"; | |
| 989 | #phy-cells = <0>; | |
| 990 | }; | |
| 991 | ||
| 992 | sata0: sata@29000000 { | |
| bb4add2c | 993 | compatible = "qcom,apq8064-ahci", "generic-ahci"; |
| e629335f SK |
994 | status = "disabled"; |
| 995 | reg = <0x29000000 0x180>; | |
| 996 | interrupts = <GIC_SPI 209 IRQ_TYPE_NONE>; | |
| 997 | ||
| 998 | clocks = <&gcc SFAB_SATA_S_H_CLK>, | |
| 999 | <&gcc SATA_H_CLK>, | |
| 1000 | <&gcc SATA_A_CLK>, | |
| 1001 | <&gcc SATA_RXOOB_CLK>, | |
| 1002 | <&gcc SATA_PMALIVE_CLK>; | |
| 1003 | clock-names = "slave_iface", | |
| 1004 | "iface", | |
| 1005 | "bus", | |
| 1006 | "rxoob", | |
| 1007 | "core_pmalive"; | |
| 1008 | ||
| 1009 | assigned-clocks = <&gcc SATA_RXOOB_CLK>, | |
| 1010 | <&gcc SATA_PMALIVE_CLK>; | |
| 1011 | assigned-clock-rates = <100000000>, <100000000>; | |
| 1012 | ||
| 1013 | phys = <&sata_phy0>; | |
| 1014 | phy-names = "sata-phy"; | |
| bb4add2c | 1015 | ports-implemented = <0x1>; |
| e629335f SK |
1016 | }; |
| 1017 | ||
| 045644ff | 1018 | /* Temporary fixed regulator */ |
| edb81ca3 SK |
1019 | sdcc1bam:dma@12402000{ |
| 1020 | compatible = "qcom,bam-v1.3.0"; | |
| 1021 | reg = <0x12402000 0x8000>; | |
| 1022 | interrupts = <0 98 0>; | |
| 1023 | clocks = <&gcc SDC1_H_CLK>; | |
| 1024 | clock-names = "bam_clk"; | |
| 1025 | #dma-cells = <1>; | |
| 1026 | qcom,ee = <0>; | |
| 1027 | }; | |
| 1028 | ||
| 1029 | sdcc3bam:dma@12182000{ | |
| 1030 | compatible = "qcom,bam-v1.3.0"; | |
| 1031 | reg = <0x12182000 0x8000>; | |
| 1032 | interrupts = <0 96 0>; | |
| 1033 | clocks = <&gcc SDC3_H_CLK>; | |
| 1034 | clock-names = "bam_clk"; | |
| 1035 | #dma-cells = <1>; | |
| 1036 | qcom,ee = <0>; | |
| 1037 | }; | |
| 1038 | ||
| 0be5fef1 SK |
1039 | sdcc4bam:dma@121c2000{ |
| 1040 | compatible = "qcom,bam-v1.3.0"; | |
| 1041 | reg = <0x121c2000 0x8000>; | |
| 1042 | interrupts = <0 95 0>; | |
| 1043 | clocks = <&gcc SDC4_H_CLK>; | |
| 1044 | clock-names = "bam_clk"; | |
| 1045 | #dma-cells = <1>; | |
| 1046 | qcom,ee = <0>; | |
| 1047 | }; | |
| 1048 | ||
| 045644ff | 1049 | amba { |
| 2ef7d5f3 | 1050 | compatible = "simple-bus"; |
| 045644ff SK |
1051 | #address-cells = <1>; |
| 1052 | #size-cells = <1>; | |
| 1053 | ranges; | |
| 1054 | sdcc1: sdcc@12400000 { | |
| 1055 | status = "disabled"; | |
| 1056 | compatible = "arm,pl18x", "arm,primecell"; | |
| ccd140b5 SK |
1057 | pinctrl-names = "default"; |
| 1058 | pinctrl-0 = <&sdcc1_pins>; | |
| 045644ff SK |
1059 | arm,primecell-periphid = <0x00051180>; |
| 1060 | reg = <0x12400000 0x2000>; | |
| 1061 | interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>; | |
| 1062 | interrupt-names = "cmd_irq"; | |
| 1063 | clocks = <&gcc SDC1_CLK>, <&gcc SDC1_H_CLK>; | |
| 1064 | clock-names = "mclk", "apb_pclk"; | |
| 1065 | bus-width = <8>; | |
| 1066 | max-frequency = <96000000>; | |
| 1067 | non-removable; | |
| 1068 | cap-sd-highspeed; | |
| 1069 | cap-mmc-highspeed; | |
| edb81ca3 SK |
1070 | dmas = <&sdcc1bam 2>, <&sdcc1bam 1>; |
| 1071 | dma-names = "tx", "rx"; | |
| 045644ff SK |
1072 | }; |
| 1073 | ||
| 1074 | sdcc3: sdcc@12180000 { | |
| 1075 | compatible = "arm,pl18x", "arm,primecell"; | |
| 1076 | arm,primecell-periphid = <0x00051180>; | |
| 1077 | status = "disabled"; | |
| 1078 | reg = <0x12180000 0x2000>; | |
| 1079 | interrupts = <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>; | |
| 1080 | interrupt-names = "cmd_irq"; | |
| 1081 | clocks = <&gcc SDC3_CLK>, <&gcc SDC3_H_CLK>; | |
| 1082 | clock-names = "mclk", "apb_pclk"; | |
| 1083 | bus-width = <4>; | |
| 1084 | cap-sd-highspeed; | |
| 1085 | cap-mmc-highspeed; | |
| 1086 | max-frequency = <192000000>; | |
| 1087 | no-1-8-v; | |
| edb81ca3 SK |
1088 | dmas = <&sdcc3bam 2>, <&sdcc3bam 1>; |
| 1089 | dma-names = "tx", "rx"; | |
| 045644ff | 1090 | }; |
| 0be5fef1 SK |
1091 | |
| 1092 | sdcc4: sdcc@121c0000 { | |
| 1093 | compatible = "arm,pl18x", "arm,primecell"; | |
| 1094 | arm,primecell-periphid = <0x00051180>; | |
| 1095 | status = "disabled"; | |
| 1096 | reg = <0x121c0000 0x2000>; | |
| 1097 | interrupts = <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>; | |
| 1098 | interrupt-names = "cmd_irq"; | |
| 1099 | clocks = <&gcc SDC4_CLK>, <&gcc SDC4_H_CLK>; | |
| 1100 | clock-names = "mclk", "apb_pclk"; | |
| 1101 | bus-width = <4>; | |
| 1102 | cap-sd-highspeed; | |
| 1103 | cap-mmc-highspeed; | |
| 1104 | max-frequency = <48000000>; | |
| 0be5fef1 SK |
1105 | dmas = <&sdcc4bam 2>, <&sdcc4bam 1>; |
| 1106 | dma-names = "tx", "rx"; | |
| 1107 | pinctrl-names = "default"; | |
| 1108 | pinctrl-0 = <&sdc4_gpios>; | |
| 1109 | }; | |
| 045644ff | 1110 | }; |
| 4105d9d6 AG |
1111 | |
| 1112 | tcsr: syscon@1a400000 { | |
| 1113 | compatible = "qcom,tcsr-apq8064", "syscon"; | |
| 1114 | reg = <0x1a400000 0x100>; | |
| 1115 | }; | |
| bcc74b09 | 1116 | |
| f078eac6 JS |
1117 | gpu: adreno-3xx@4300000 { |
| 1118 | compatible = "qcom,adreno-3xx"; | |
| 1119 | reg = <0x04300000 0x20000>; | |
| 1120 | reg-names = "kgsl_3d0_reg_memory"; | |
| 1121 | interrupts = <GIC_SPI 80 0>; | |
| 1122 | interrupt-names = "kgsl_3d0_irq"; | |
| 1123 | clock-names = | |
| 1124 | "core_clk", | |
| 1125 | "iface_clk", | |
| 1126 | "mem_clk", | |
| 1127 | "mem_iface_clk"; | |
| 1128 | clocks = | |
| 1129 | <&mmcc GFX3D_CLK>, | |
| 1130 | <&mmcc GFX3D_AHB_CLK>, | |
| 1131 | <&mmcc GFX3D_AXI_CLK>, | |
| 1132 | <&mmcc MMSS_IMEM_AHB_CLK>; | |
| 1133 | qcom,chipid = <0x03020002>; | |
| 1134 | ||
| 1135 | iommus = <&gfx3d 0 | |
| 1136 | &gfx3d 1 | |
| 1137 | &gfx3d 2 | |
| 1138 | &gfx3d 3 | |
| 1139 | &gfx3d 4 | |
| 1140 | &gfx3d 5 | |
| 1141 | &gfx3d 6 | |
| 1142 | &gfx3d 7 | |
| 1143 | &gfx3d 8 | |
| 1144 | &gfx3d 9 | |
| 1145 | &gfx3d 10 | |
| 1146 | &gfx3d 11 | |
| 1147 | &gfx3d 12 | |
| 1148 | &gfx3d 13 | |
| 1149 | &gfx3d 14 | |
| 1150 | &gfx3d 15 | |
| 1151 | &gfx3d 16 | |
| 1152 | &gfx3d 17 | |
| 1153 | &gfx3d 18 | |
| 1154 | &gfx3d 19 | |
| 1155 | &gfx3d 20 | |
| 1156 | &gfx3d 21 | |
| 1157 | &gfx3d 22 | |
| 1158 | &gfx3d 23 | |
| 1159 | &gfx3d 24 | |
| 1160 | &gfx3d 25 | |
| 1161 | &gfx3d 26 | |
| 1162 | &gfx3d 27 | |
| 1163 | &gfx3d 28 | |
| 1164 | &gfx3d 29 | |
| 1165 | &gfx3d 30 | |
| 1166 | &gfx3d 31 | |
| 1167 | &gfx3d1 0 | |
| 1168 | &gfx3d1 1 | |
| 1169 | &gfx3d1 2 | |
| 1170 | &gfx3d1 3 | |
| 1171 | &gfx3d1 4 | |
| 1172 | &gfx3d1 5 | |
| 1173 | &gfx3d1 6 | |
| 1174 | &gfx3d1 7 | |
| 1175 | &gfx3d1 8 | |
| 1176 | &gfx3d1 9 | |
| 1177 | &gfx3d1 10 | |
| 1178 | &gfx3d1 11 | |
| 1179 | &gfx3d1 12 | |
| 1180 | &gfx3d1 13 | |
| 1181 | &gfx3d1 14 | |
| 1182 | &gfx3d1 15 | |
| 1183 | &gfx3d1 16 | |
| 1184 | &gfx3d1 17 | |
| 1185 | &gfx3d1 18 | |
| 1186 | &gfx3d1 19 | |
| 1187 | &gfx3d1 20 | |
| 1188 | &gfx3d1 21 | |
| 1189 | &gfx3d1 22 | |
| 1190 | &gfx3d1 23 | |
| 1191 | &gfx3d1 24 | |
| 1192 | &gfx3d1 25 | |
| 1193 | &gfx3d1 26 | |
| 1194 | &gfx3d1 27 | |
| 1195 | &gfx3d1 28 | |
| 1196 | &gfx3d1 29 | |
| 1197 | &gfx3d1 30 | |
| 1198 | &gfx3d1 31>; | |
| 1199 | ||
| 1200 | qcom,gpu-pwrlevels { | |
| 1201 | compatible = "qcom,gpu-pwrlevels"; | |
| 1202 | qcom,gpu-pwrlevel@0 { | |
| 1203 | qcom,gpu-freq = <450000000>; | |
| 1204 | }; | |
| 1205 | qcom,gpu-pwrlevel@1 { | |
| 1206 | qcom,gpu-freq = <27000000>; | |
| 1207 | }; | |
| 1208 | }; | |
| 1209 | }; | |
| 1210 | ||
| 1211 | mmss_sfpb: syscon@5700000 { | |
| 1212 | compatible = "syscon"; | |
| 1213 | reg = <0x5700000 0x70>; | |
| 1214 | }; | |
| 1215 | ||
| 1216 | dsi0: mdss_dsi@4700000 { | |
| 1217 | compatible = "qcom,mdss-dsi-ctrl"; | |
| 1218 | label = "MDSS DSI CTRL->0"; | |
| 1219 | #address-cells = <1>; | |
| 1220 | #size-cells = <0>; | |
| 1221 | interrupts = <GIC_SPI 82 0>; | |
| 1222 | reg = <0x04700000 0x200>; | |
| 1223 | reg-names = "dsi_ctrl"; | |
| 1224 | ||
| 1225 | clocks = <&mmcc DSI_M_AHB_CLK>, | |
| 1226 | <&mmcc DSI_S_AHB_CLK>, | |
| 1227 | <&mmcc AMP_AHB_CLK>, | |
| 1228 | <&mmcc DSI_CLK>, | |
| 1229 | <&mmcc DSI1_BYTE_CLK>, | |
| 1230 | <&mmcc DSI_PIXEL_CLK>, | |
| 1231 | <&mmcc DSI1_ESC_CLK>; | |
| 1232 | clock-names = "iface_clk", "bus_clk", "core_mmss_clk", | |
| 1233 | "src_clk", "byte_clk", "pixel_clk", | |
| 1234 | "core_clk"; | |
| 1235 | ||
| 1236 | assigned-clocks = <&mmcc DSI1_BYTE_SRC>, | |
| 1237 | <&mmcc DSI1_ESC_SRC>, | |
| 1238 | <&mmcc DSI_SRC>, | |
| 1239 | <&mmcc DSI_PIXEL_SRC>; | |
| 1240 | assigned-clock-parents = <&dsi0_phy 0>, | |
| 1241 | <&dsi0_phy 0>, | |
| 1242 | <&dsi0_phy 1>, | |
| 1243 | <&dsi0_phy 1>; | |
| 1244 | syscon-sfpb = <&mmss_sfpb>; | |
| 1245 | phys = <&dsi0_phy>; | |
| 1246 | ports { | |
| 1247 | #address-cells = <1>; | |
| 1248 | #size-cells = <0>; | |
| 1249 | ||
| 1250 | port@0 { | |
| 1251 | reg = <0>; | |
| 1252 | dsi0_in: endpoint { | |
| 1253 | }; | |
| 1254 | }; | |
| 1255 | ||
| 1256 | port@1 { | |
| 1257 | reg = <1>; | |
| 1258 | dsi0_out: endpoint { | |
| 1259 | }; | |
| 1260 | }; | |
| 1261 | }; | |
| 1262 | }; | |
| 1263 | ||
| 1264 | ||
| 1265 | dsi0_phy: dsi-phy@4700200 { | |
| 1266 | compatible = "qcom,dsi-phy-28nm-8960"; | |
| 1267 | #clock-cells = <1>; | |
| 3191b5b3 | 1268 | #phy-cells = <0>; |
| f078eac6 JS |
1269 | |
| 1270 | reg = <0x04700200 0x100>, | |
| 1271 | <0x04700300 0x200>, | |
| 1272 | <0x04700500 0x5c>; | |
| 1273 | reg-names = "dsi_pll", "dsi_phy", "dsi_phy_regulator"; | |
| 1274 | clock-names = "iface_clk"; | |
| 1275 | clocks = <&mmcc DSI_M_AHB_CLK>; | |
| 1276 | }; | |
| 1277 | ||
| 1278 | ||
| 1279 | mdp_port0: iommu@7500000 { | |
| 1280 | compatible = "qcom,apq8064-iommu"; | |
| 1281 | #iommu-cells = <1>; | |
| 1282 | clock-names = | |
| 1283 | "smmu_pclk", | |
| 1284 | "iommu_clk"; | |
| 1285 | clocks = | |
| 1286 | <&mmcc SMMU_AHB_CLK>, | |
| 1287 | <&mmcc MDP_AXI_CLK>; | |
| 1288 | reg = <0x07500000 0x100000>; | |
| 1289 | interrupts = | |
| 1290 | <GIC_SPI 63 0>, | |
| 1291 | <GIC_SPI 64 0>; | |
| 1292 | qcom,ncb = <2>; | |
| 1293 | }; | |
| 1294 | ||
| 1295 | mdp_port1: iommu@7600000 { | |
| 1296 | compatible = "qcom,apq8064-iommu"; | |
| 1297 | #iommu-cells = <1>; | |
| 1298 | clock-names = | |
| 1299 | "smmu_pclk", | |
| 1300 | "iommu_clk"; | |
| 1301 | clocks = | |
| 1302 | <&mmcc SMMU_AHB_CLK>, | |
| 1303 | <&mmcc MDP_AXI_CLK>; | |
| 1304 | reg = <0x07600000 0x100000>; | |
| 1305 | interrupts = | |
| 1306 | <GIC_SPI 61 0>, | |
| 1307 | <GIC_SPI 62 0>; | |
| 1308 | qcom,ncb = <2>; | |
| 1309 | }; | |
| 1310 | ||
| 1311 | gfx3d: iommu@7c00000 { | |
| 1312 | compatible = "qcom,apq8064-iommu"; | |
| 1313 | #iommu-cells = <1>; | |
| 1314 | clock-names = | |
| 1315 | "smmu_pclk", | |
| 1316 | "iommu_clk"; | |
| 1317 | clocks = | |
| 1318 | <&mmcc SMMU_AHB_CLK>, | |
| 1319 | <&mmcc GFX3D_AXI_CLK>; | |
| 1320 | reg = <0x07c00000 0x100000>; | |
| 1321 | interrupts = | |
| 1322 | <GIC_SPI 69 0>, | |
| 1323 | <GIC_SPI 70 0>; | |
| 1324 | qcom,ncb = <3>; | |
| 1325 | }; | |
| 1326 | ||
| 1327 | gfx3d1: iommu@7d00000 { | |
| 1328 | compatible = "qcom,apq8064-iommu"; | |
| 1329 | #iommu-cells = <1>; | |
| 1330 | clock-names = | |
| 1331 | "smmu_pclk", | |
| 1332 | "iommu_clk"; | |
| 1333 | clocks = | |
| 1334 | <&mmcc SMMU_AHB_CLK>, | |
| 1335 | <&mmcc GFX3D_AXI_CLK>; | |
| 1336 | reg = <0x07d00000 0x100000>; | |
| 1337 | interrupts = | |
| 1338 | <GIC_SPI 210 0>, | |
| 1339 | <GIC_SPI 211 0>; | |
| 1340 | qcom,ncb = <3>; | |
| 1341 | }; | |
| 1342 | ||
| bcc74b09 SV |
1343 | pcie: pci@1b500000 { |
| 1344 | compatible = "qcom,pcie-apq8064", "snps,dw-pcie"; | |
| 1345 | reg = <0x1b500000 0x1000 | |
| 1346 | 0x1b502000 0x80 | |
| 1347 | 0x1b600000 0x100 | |
| 1348 | 0x0ff00000 0x100000>; | |
| 1349 | reg-names = "dbi", "elbi", "parf", "config"; | |
| 1350 | device_type = "pci"; | |
| 1351 | linux,pci-domain = <0>; | |
| 1352 | bus-range = <0x00 0xff>; | |
| 1353 | num-lanes = <1>; | |
| 1354 | #address-cells = <3>; | |
| 1355 | #size-cells = <2>; | |
| 1356 | ranges = <0x81000000 0 0 0x0fe00000 0 0x00100000 /* I/O */ | |
| 1357 | 0x82000000 0 0 0x08000000 0 0x07e00000>; /* memory */ | |
| 1358 | interrupts = <GIC_SPI 238 IRQ_TYPE_NONE>; | |
| 1359 | interrupt-names = "msi"; | |
| 1360 | #interrupt-cells = <1>; | |
| 1361 | interrupt-map-mask = <0 0 0 0x7>; | |
| 1362 | interrupt-map = <0 0 0 1 &intc 0 36 IRQ_TYPE_LEVEL_HIGH>, /* int_a */ | |
| 1363 | <0 0 0 2 &intc 0 37 IRQ_TYPE_LEVEL_HIGH>, /* int_b */ | |
| 1364 | <0 0 0 3 &intc 0 38 IRQ_TYPE_LEVEL_HIGH>, /* int_c */ | |
| 1365 | <0 0 0 4 &intc 0 39 IRQ_TYPE_LEVEL_HIGH>; /* int_d */ | |
| 1366 | clocks = <&gcc PCIE_A_CLK>, | |
| 1367 | <&gcc PCIE_H_CLK>, | |
| 1368 | <&gcc PCIE_PHY_REF_CLK>; | |
| 1369 | clock-names = "core", "iface", "phy"; | |
| 1370 | resets = <&gcc PCIE_ACLK_RESET>, | |
| 1371 | <&gcc PCIE_HCLK_RESET>, | |
| 1372 | <&gcc PCIE_POR_RESET>, | |
| 1373 | <&gcc PCIE_PCI_RESET>, | |
| 1374 | <&gcc PCIE_PHY_RESET>; | |
| 1375 | reset-names = "axi", "ahb", "por", "pci", "phy"; | |
| 1376 | status = "disabled"; | |
| 1377 | }; | |
| e77a3a78 AT |
1378 | |
| 1379 | hdmi: hdmi-tx@4a00000 { | |
| 1380 | compatible = "qcom,hdmi-tx-8960"; | |
| ec65428f SK |
1381 | pinctrl-names = "default"; |
| 1382 | pinctrl-0 = <&hdmi_pinctrl>; | |
| e77a3a78 AT |
1383 | reg = <0x04a00000 0x2f0>; |
| 1384 | reg-names = "core_physical"; | |
| 1385 | interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>; | |
| 1386 | clocks = <&mmcc HDMI_APP_CLK>, | |
| 1387 | <&mmcc HDMI_M_AHB_CLK>, | |
| 1388 | <&mmcc HDMI_S_AHB_CLK>; | |
| 1389 | clock-names = "core_clk", | |
| 1390 | "master_iface_clk", | |
| 1391 | "slave_iface_clk"; | |
| 1392 | ||
| 1393 | phys = <&hdmi_phy>; | |
| 1394 | phy-names = "hdmi-phy"; | |
| 1395 | ||
| 1396 | ports { | |
| 1397 | #address-cells = <1>; | |
| 1398 | #size-cells = <0>; | |
| 1399 | ||
| 1400 | port@0 { | |
| 1401 | reg = <0>; | |
| 1402 | hdmi_in: endpoint { | |
| 1403 | }; | |
| 1404 | }; | |
| 1405 | ||
| 1406 | port@1 { | |
| 1407 | reg = <1>; | |
| 1408 | hdmi_out: endpoint { | |
| 1409 | }; | |
| 1410 | }; | |
| 1411 | }; | |
| 1412 | }; | |
| 1413 | ||
| 1414 | hdmi_phy: hdmi-phy@4a00400 { | |
| 1415 | compatible = "qcom,hdmi-phy-8960"; | |
| 1416 | reg = <0x4a00400 0x60>, | |
| 1417 | <0x4a00500 0x100>; | |
| 1418 | reg-names = "hdmi_phy", | |
| 1419 | "hdmi_pll"; | |
| 1420 | ||
| 1421 | clocks = <&mmcc HDMI_S_AHB_CLK>; | |
| 1422 | clock-names = "slave_iface_clk"; | |
| 3191b5b3 | 1423 | #phy-cells = <0>; |
| e77a3a78 AT |
1424 | }; |
| 1425 | ||
| 1426 | mdp: mdp@5100000 { | |
| 1427 | compatible = "qcom,mdp4"; | |
| 1428 | reg = <0x05100000 0xf0000>; | |
| 1429 | interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>; | |
| 1430 | clocks = <&mmcc MDP_CLK>, | |
| 1431 | <&mmcc MDP_AHB_CLK>, | |
| 1432 | <&mmcc MDP_AXI_CLK>, | |
| 1433 | <&mmcc MDP_LUT_CLK>, | |
| 1434 | <&mmcc HDMI_TV_CLK>, | |
| 1435 | <&mmcc MDP_TV_CLK>; | |
| 1436 | clock-names = "core_clk", | |
| 1437 | "iface_clk", | |
| 1438 | "bus_clk", | |
| 1439 | "lut_clk", | |
| 1440 | "hdmi_clk", | |
| 1441 | "tv_clk"; | |
| 1442 | ||
| f078eac6 JS |
1443 | iommus = <&mdp_port0 0 |
| 1444 | &mdp_port0 2 | |
| 1445 | &mdp_port1 0 | |
| 1446 | &mdp_port1 2>; | |
| 1447 | ||
| e77a3a78 AT |
1448 | ports { |
| 1449 | #address-cells = <1>; | |
| 1450 | #size-cells = <0>; | |
| 1451 | ||
| 1452 | port@0 { | |
| 1453 | reg = <0>; | |
| 1454 | mdp_lvds_out: endpoint { | |
| 1455 | }; | |
| 1456 | }; | |
| 1457 | ||
| 1458 | port@1 { | |
| 1459 | reg = <1>; | |
| 1460 | mdp_dsi1_out: endpoint { | |
| 1461 | }; | |
| 1462 | }; | |
| 1463 | ||
| 1464 | port@2 { | |
| 1465 | reg = <2>; | |
| 1466 | mdp_dsi2_out: endpoint { | |
| 1467 | }; | |
| 1468 | }; | |
| 1469 | ||
| 1470 | port@3 { | |
| 1471 | reg = <3>; | |
| 1472 | mdp_dtv_out: endpoint { | |
| 1473 | }; | |
| 1474 | }; | |
| 1475 | }; | |
| 1476 | }; | |
| f9a8aaed BA |
1477 | |
| 1478 | riva: riva-pil@3204000 { | |
| 1479 | compatible = "qcom,riva-pil"; | |
| 1480 | ||
| 1481 | reg = <0x03200800 0x1000>, <0x03202000 0x2000>, <0x03204000 0x100>; | |
| 1482 | reg-names = "ccu", "dxe", "pmu"; | |
| 1483 | ||
| 1484 | interrupts-extended = <&intc GIC_SPI 199 IRQ_TYPE_EDGE_RISING>, | |
| 1485 | <&wcnss_smsm 6 IRQ_TYPE_EDGE_RISING>; | |
| 1486 | interrupt-names = "wdog", "fatal"; | |
| 1487 | ||
| 1488 | memory-region = <&wcnss_mem>; | |
| 1489 | ||
| 1490 | vddcx-supply = <&pm8921_s3>; | |
| 1491 | vddmx-supply = <&pm8921_l24>; | |
| 1492 | vddpx-supply = <&pm8921_s4>; | |
| 1493 | ||
| 1494 | status = "disabled"; | |
| 1495 | ||
| 1496 | iris { | |
| 1497 | compatible = "qcom,wcn3660"; | |
| 1498 | ||
| 1499 | clocks = <&cxo_board>; | |
| 1500 | clock-names = "xo"; | |
| 1501 | ||
| 1502 | vddxo-supply = <&pm8921_l4>; | |
| 1503 | vddrfa-supply = <&pm8921_s2>; | |
| 1504 | vddpa-supply = <&pm8921_l10>; | |
| 1505 | vdddig-supply = <&pm8921_lvs2>; | |
| 1506 | }; | |
| 1507 | ||
| 1508 | smd-edge { | |
| 1509 | interrupts = <GIC_SPI 198 IRQ_TYPE_EDGE_RISING>; | |
| 1510 | ||
| 1511 | qcom,ipc = <&l2cc 8 25>; | |
| 1512 | qcom,smd-edge = <6>; | |
| 1513 | ||
| 1514 | label = "riva"; | |
| 1515 | ||
| 1516 | wcnss { | |
| 1517 | compatible = "qcom,wcnss"; | |
| 1518 | qcom,smd-channels = "WCNSS_CTRL"; | |
| 1519 | ||
| 1520 | qcom,mmio = <&riva>; | |
| 1521 | ||
| 1522 | bt { | |
| 1523 | compatible = "qcom,wcnss-bt"; | |
| 1524 | }; | |
| 1525 | ||
| 1526 | wifi { | |
| 1527 | compatible = "qcom,wcnss-wlan"; | |
| 1528 | ||
| 1529 | interrupts = <GIC_SPI 203 IRQ_TYPE_LEVEL_HIGH>, | |
| 1530 | <GIC_SPI 202 IRQ_TYPE_LEVEL_HIGH>; | |
| 1531 | interrupt-names = "tx", "rx"; | |
| 1532 | ||
| 1533 | qcom,smem-states = <&apps_smsm 10>, <&apps_smsm 9>; | |
| 1534 | qcom,smem-state-names = "tx-enable", "tx-rings-empty"; | |
| 1535 | }; | |
| 1536 | }; | |
| 1537 | }; | |
| 1538 | }; | |
| 7a5c275f II |
1539 | |
| 1540 | etb@1a01000 { | |
| 1541 | compatible = "coresight-etb10", "arm,primecell"; | |
| 1542 | reg = <0x1a01000 0x1000>; | |
| 1543 | ||
| 1544 | clocks = <&rpmcc RPM_QDSS_CLK>; | |
| 1545 | clock-names = "apb_pclk"; | |
| 1546 | ||
| 1547 | port { | |
| 1548 | etb_in: endpoint { | |
| 1549 | slave-mode; | |
| 1550 | remote-endpoint = <&replicator_out0>; | |
| 1551 | }; | |
| 1552 | }; | |
| 1553 | }; | |
| 1554 | ||
| 1555 | tpiu@1a03000 { | |
| 1556 | compatible = "arm,coresight-tpiu", "arm,primecell"; | |
| 1557 | reg = <0x1a03000 0x1000>; | |
| 1558 | ||
| 1559 | clocks = <&rpmcc RPM_QDSS_CLK>; | |
| 1560 | clock-names = "apb_pclk"; | |
| 1561 | ||
| 1562 | port { | |
| 1563 | tpiu_in: endpoint { | |
| 1564 | slave-mode; | |
| 1565 | remote-endpoint = <&replicator_out1>; | |
| 1566 | }; | |
| 1567 | }; | |
| 1568 | }; | |
| 1569 | ||
| 1570 | replicator { | |
| 1571 | compatible = "arm,coresight-replicator"; | |
| 1572 | ||
| 1573 | clocks = <&rpmcc RPM_QDSS_CLK>; | |
| 1574 | clock-names = "apb_pclk"; | |
| 1575 | ||
| 1576 | ports { | |
| 1577 | #address-cells = <1>; | |
| 1578 | #size-cells = <0>; | |
| 1579 | ||
| 1580 | port@0 { | |
| 1581 | reg = <0>; | |
| 1582 | replicator_out0: endpoint { | |
| 1583 | remote-endpoint = <&etb_in>; | |
| 1584 | }; | |
| 1585 | }; | |
| 1586 | port@1 { | |
| 1587 | reg = <1>; | |
| 1588 | replicator_out1: endpoint { | |
| 1589 | remote-endpoint = <&tpiu_in>; | |
| 1590 | }; | |
| 1591 | }; | |
| 1592 | port@2 { | |
| 1593 | reg = <0>; | |
| 1594 | replicator_in: endpoint { | |
| 1595 | slave-mode; | |
| 1596 | remote-endpoint = <&funnel_out>; | |
| 1597 | }; | |
| 1598 | }; | |
| 1599 | }; | |
| 1600 | }; | |
| 1601 | ||
| 1602 | funnel@1a04000 { | |
| 1603 | compatible = "arm,coresight-funnel", "arm,primecell"; | |
| 1604 | reg = <0x1a04000 0x1000>; | |
| 1605 | ||
| 1606 | clocks = <&rpmcc RPM_QDSS_CLK>; | |
| 1607 | clock-names = "apb_pclk"; | |
| 1608 | ||
| 1609 | ports { | |
| 1610 | #address-cells = <1>; | |
| 1611 | #size-cells = <0>; | |
| 1612 | ||
| 1613 | /* | |
| 1614 | * Not described input ports: | |
| 1615 | * 2 - connected to STM component | |
| 1616 | * 3 - not-connected | |
| 1617 | * 6 - not-connected | |
| 1618 | * 7 - not-connected | |
| 1619 | */ | |
| 1620 | port@0 { | |
| 1621 | reg = <0>; | |
| 1622 | funnel_in0: endpoint { | |
| 1623 | slave-mode; | |
| 1624 | remote-endpoint = <&etm0_out>; | |
| 1625 | }; | |
| 1626 | }; | |
| 1627 | port@1 { | |
| 1628 | reg = <1>; | |
| 1629 | funnel_in1: endpoint { | |
| 1630 | slave-mode; | |
| 1631 | remote-endpoint = <&etm1_out>; | |
| 1632 | }; | |
| 1633 | }; | |
| 1634 | port@4 { | |
| 1635 | reg = <4>; | |
| 1636 | funnel_in4: endpoint { | |
| 1637 | slave-mode; | |
| 1638 | remote-endpoint = <&etm2_out>; | |
| 1639 | }; | |
| 1640 | }; | |
| 1641 | port@5 { | |
| 1642 | reg = <5>; | |
| 1643 | funnel_in5: endpoint { | |
| 1644 | slave-mode; | |
| 1645 | remote-endpoint = <&etm3_out>; | |
| 1646 | }; | |
| 1647 | }; | |
| 1648 | port@8 { | |
| 1649 | reg = <0>; | |
| 1650 | funnel_out: endpoint { | |
| 1651 | remote-endpoint = <&replicator_in>; | |
| 1652 | }; | |
| 1653 | }; | |
| 1654 | }; | |
| 1655 | }; | |
| 1656 | ||
| 1657 | etm@1a1c000 { | |
| 1658 | compatible = "arm,coresight-etm3x", "arm,primecell"; | |
| 1659 | reg = <0x1a1c000 0x1000>; | |
| 1660 | ||
| 1661 | clocks = <&rpmcc RPM_QDSS_CLK>; | |
| 1662 | clock-names = "apb_pclk"; | |
| 1663 | ||
| 1664 | cpu = <&CPU0>; | |
| 1665 | ||
| 1666 | port { | |
| 1667 | etm0_out: endpoint { | |
| 1668 | remote-endpoint = <&funnel_in0>; | |
| 1669 | }; | |
| 1670 | }; | |
| 1671 | }; | |
| 1672 | ||
| 1673 | etm@1a1d000 { | |
| 1674 | compatible = "arm,coresight-etm3x", "arm,primecell"; | |
| 1675 | reg = <0x1a1d000 0x1000>; | |
| 1676 | ||
| 1677 | clocks = <&rpmcc RPM_QDSS_CLK>; | |
| 1678 | clock-names = "apb_pclk"; | |
| 1679 | ||
| 1680 | cpu = <&CPU1>; | |
| 1681 | ||
| 1682 | port { | |
| 1683 | etm1_out: endpoint { | |
| 1684 | remote-endpoint = <&funnel_in1>; | |
| 1685 | }; | |
| 1686 | }; | |
| 1687 | }; | |
| 1688 | ||
| 1689 | etm@1a1e000 { | |
| 1690 | compatible = "arm,coresight-etm3x", "arm,primecell"; | |
| 1691 | reg = <0x1a1e000 0x1000>; | |
| 1692 | ||
| 1693 | clocks = <&rpmcc RPM_QDSS_CLK>; | |
| 1694 | clock-names = "apb_pclk"; | |
| 1695 | ||
| 1696 | cpu = <&CPU2>; | |
| 1697 | ||
| 1698 | port { | |
| 1699 | etm2_out: endpoint { | |
| 1700 | remote-endpoint = <&funnel_in4>; | |
| 1701 | }; | |
| 1702 | }; | |
| 1703 | }; | |
| 1704 | ||
| 1705 | etm@1a1f000 { | |
| 1706 | compatible = "arm,coresight-etm3x", "arm,primecell"; | |
| 1707 | reg = <0x1a1f000 0x1000>; | |
| 1708 | ||
| 1709 | clocks = <&rpmcc RPM_QDSS_CLK>; | |
| 1710 | clock-names = "apb_pclk"; | |
| 1711 | ||
| 1712 | cpu = <&CPU3>; | |
| 1713 | ||
| 1714 | port { | |
| 1715 | etm3_out: endpoint { | |
| 1716 | remote-endpoint = <&funnel_in5>; | |
| 1717 | }; | |
| 1718 | }; | |
| 1719 | }; | |
| f335b8af KG |
1720 | }; |
| 1721 | }; | |
| a30e78bd | 1722 | #include "qcom-apq8064-pins.dtsi" |