Commit | Line | Data |
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f335b8af KG |
1 | /dts-v1/; |
2 | ||
3 | #include "skeleton.dtsi" | |
4 | #include <dt-bindings/clock/qcom,gcc-msm8960.h> | |
223280b1 | 5 | #include <dt-bindings/reset/qcom,gcc-msm8960.h> |
3fe5e3ce | 6 | #include <dt-bindings/clock/qcom,mmcc-msm8960.h> |
f335b8af | 7 | #include <dt-bindings/soc/qcom,gsbi.h> |
8b8936fc | 8 | #include <dt-bindings/interrupt-controller/arm-gic.h> |
f335b8af KG |
9 | / { |
10 | model = "Qualcomm APQ8064"; | |
11 | compatible = "qcom,apq8064"; | |
12 | interrupt-parent = <&intc>; | |
13 | ||
24a9baf9 BA |
14 | reserved-memory { |
15 | #address-cells = <1>; | |
16 | #size-cells = <1>; | |
17 | ranges; | |
18 | ||
19 | smem_region: smem@80000000 { | |
20 | reg = <0x80000000 0x200000>; | |
21 | no-map; | |
22 | }; | |
23 | }; | |
24 | ||
f335b8af KG |
25 | cpus { |
26 | #address-cells = <1>; | |
27 | #size-cells = <0>; | |
28 | ||
29 | cpu@0 { | |
30 | compatible = "qcom,krait"; | |
31 | enable-method = "qcom,kpss-acc-v1"; | |
32 | device_type = "cpu"; | |
33 | reg = <0>; | |
34 | next-level-cache = <&L2>; | |
35 | qcom,acc = <&acc0>; | |
36 | qcom,saw = <&saw0>; | |
06c49f2b | 37 | cpu-idle-states = <&CPU_SPC>; |
f335b8af KG |
38 | }; |
39 | ||
40 | cpu@1 { | |
41 | compatible = "qcom,krait"; | |
42 | enable-method = "qcom,kpss-acc-v1"; | |
43 | device_type = "cpu"; | |
44 | reg = <1>; | |
45 | next-level-cache = <&L2>; | |
46 | qcom,acc = <&acc1>; | |
47 | qcom,saw = <&saw1>; | |
06c49f2b | 48 | cpu-idle-states = <&CPU_SPC>; |
f335b8af KG |
49 | }; |
50 | ||
51 | cpu@2 { | |
52 | compatible = "qcom,krait"; | |
53 | enable-method = "qcom,kpss-acc-v1"; | |
54 | device_type = "cpu"; | |
55 | reg = <2>; | |
56 | next-level-cache = <&L2>; | |
57 | qcom,acc = <&acc2>; | |
58 | qcom,saw = <&saw2>; | |
06c49f2b | 59 | cpu-idle-states = <&CPU_SPC>; |
f335b8af KG |
60 | }; |
61 | ||
62 | cpu@3 { | |
63 | compatible = "qcom,krait"; | |
64 | enable-method = "qcom,kpss-acc-v1"; | |
65 | device_type = "cpu"; | |
66 | reg = <3>; | |
67 | next-level-cache = <&L2>; | |
68 | qcom,acc = <&acc3>; | |
69 | qcom,saw = <&saw3>; | |
06c49f2b | 70 | cpu-idle-states = <&CPU_SPC>; |
f335b8af KG |
71 | }; |
72 | ||
73 | L2: l2-cache { | |
74 | compatible = "cache"; | |
75 | cache-level = <2>; | |
76 | }; | |
06c49f2b LI |
77 | |
78 | idle-states { | |
79 | CPU_SPC: spc { | |
80 | compatible = "qcom,idle-state-spc", | |
81 | "arm,idle-state"; | |
82 | entry-latency-us = <400>; | |
83 | exit-latency-us = <900>; | |
84 | min-residency-us = <3000>; | |
85 | }; | |
86 | }; | |
f335b8af KG |
87 | }; |
88 | ||
89 | cpu-pmu { | |
90 | compatible = "qcom,krait-pmu"; | |
91 | interrupts = <1 10 0x304>; | |
92 | }; | |
93 | ||
aa269127 GD |
94 | clocks { |
95 | cxo_board { | |
96 | compatible = "fixed-clock"; | |
97 | #clock-cells = <0>; | |
98 | clock-frequency = <19200000>; | |
99 | }; | |
100 | ||
101 | pxo_board { | |
102 | compatible = "fixed-clock"; | |
103 | #clock-cells = <0>; | |
104 | clock-frequency = <27000000>; | |
105 | }; | |
106 | ||
107 | sleep_clk { | |
108 | compatible = "fixed-clock"; | |
109 | #clock-cells = <0>; | |
110 | clock-frequency = <32768>; | |
111 | }; | |
112 | }; | |
113 | ||
24a9baf9 BA |
114 | sfpb_mutex: hwmutex { |
115 | compatible = "qcom,sfpb-mutex"; | |
116 | syscon = <&sfpb_wrapper_mutex 0x604 0x4>; | |
117 | #hwlock-cells = <1>; | |
118 | }; | |
119 | ||
120 | smem { | |
121 | compatible = "qcom,smem"; | |
122 | memory-region = <&smem_region>; | |
123 | ||
124 | hwlocks = <&sfpb_mutex 3>; | |
125 | }; | |
126 | ||
f335b8af KG |
127 | soc: soc { |
128 | #address-cells = <1>; | |
129 | #size-cells = <1>; | |
130 | ranges; | |
131 | compatible = "simple-bus"; | |
132 | ||
8b8936fc PG |
133 | tlmm_pinmux: pinctrl@800000 { |
134 | compatible = "qcom,apq8064-pinctrl"; | |
135 | reg = <0x800000 0x4000>; | |
136 | ||
137 | gpio-controller; | |
138 | #gpio-cells = <2>; | |
139 | interrupt-controller; | |
140 | #interrupt-cells = <2>; | |
141 | interrupts = <0 16 IRQ_TYPE_LEVEL_HIGH>; | |
cd6dd11a PG |
142 | |
143 | pinctrl-names = "default"; | |
144 | pinctrl-0 = <&ps_hold>; | |
8b8936fc PG |
145 | }; |
146 | ||
24a9baf9 BA |
147 | sfpb_wrapper_mutex: syscon@1200000 { |
148 | compatible = "syscon"; | |
149 | reg = <0x01200000 0x8000>; | |
150 | }; | |
151 | ||
f335b8af KG |
152 | intc: interrupt-controller@2000000 { |
153 | compatible = "qcom,msm-qgic2"; | |
154 | interrupt-controller; | |
155 | #interrupt-cells = <3>; | |
156 | reg = <0x02000000 0x1000>, | |
157 | <0x02002000 0x1000>; | |
158 | }; | |
159 | ||
160 | timer@200a000 { | |
161 | compatible = "qcom,kpss-timer", "qcom,msm-timer"; | |
162 | interrupts = <1 1 0x301>, | |
163 | <1 2 0x301>, | |
164 | <1 3 0x301>; | |
165 | reg = <0x0200a000 0x100>; | |
166 | clock-frequency = <27000000>, | |
167 | <32768>; | |
168 | cpu-offset = <0x80000>; | |
169 | }; | |
170 | ||
171 | acc0: clock-controller@2088000 { | |
172 | compatible = "qcom,kpss-acc-v1"; | |
173 | reg = <0x02088000 0x1000>, <0x02008000 0x1000>; | |
174 | }; | |
175 | ||
176 | acc1: clock-controller@2098000 { | |
177 | compatible = "qcom,kpss-acc-v1"; | |
178 | reg = <0x02098000 0x1000>, <0x02008000 0x1000>; | |
179 | }; | |
180 | ||
181 | acc2: clock-controller@20a8000 { | |
182 | compatible = "qcom,kpss-acc-v1"; | |
183 | reg = <0x020a8000 0x1000>, <0x02008000 0x1000>; | |
184 | }; | |
185 | ||
186 | acc3: clock-controller@20b8000 { | |
187 | compatible = "qcom,kpss-acc-v1"; | |
188 | reg = <0x020b8000 0x1000>, <0x02008000 0x1000>; | |
189 | }; | |
190 | ||
9fc23ce3 LI |
191 | saw0: power-controller@2089000 { |
192 | compatible = "qcom,apq8064-saw2-v1.1-cpu", "qcom,saw2"; | |
f335b8af KG |
193 | reg = <0x02089000 0x1000>, <0x02009000 0x1000>; |
194 | regulator; | |
195 | }; | |
196 | ||
9fc23ce3 LI |
197 | saw1: power-controller@2099000 { |
198 | compatible = "qcom,apq8064-saw2-v1.1-cpu", "qcom,saw2"; | |
f335b8af KG |
199 | reg = <0x02099000 0x1000>, <0x02009000 0x1000>; |
200 | regulator; | |
201 | }; | |
202 | ||
9fc23ce3 LI |
203 | saw2: power-controller@20a9000 { |
204 | compatible = "qcom,apq8064-saw2-v1.1-cpu", "qcom,saw2"; | |
f335b8af KG |
205 | reg = <0x020a9000 0x1000>, <0x02009000 0x1000>; |
206 | regulator; | |
207 | }; | |
208 | ||
9fc23ce3 LI |
209 | saw3: power-controller@20b9000 { |
210 | compatible = "qcom,apq8064-saw2-v1.1-cpu", "qcom,saw2"; | |
f335b8af KG |
211 | reg = <0x020b9000 0x1000>, <0x02009000 0x1000>; |
212 | regulator; | |
213 | }; | |
214 | ||
8c3166f5 | 215 | gsbi1: gsbi@12440000 { |
216 | status = "disabled"; | |
217 | compatible = "qcom,gsbi-v1.0.0"; | |
4105d9d6 | 218 | cell-index = <1>; |
8c3166f5 | 219 | reg = <0x12440000 0x100>; |
220 | clocks = <&gcc GSBI1_H_CLK>; | |
221 | clock-names = "iface"; | |
222 | #address-cells = <1>; | |
223 | #size-cells = <1>; | |
224 | ranges; | |
225 | ||
4105d9d6 AG |
226 | syscon-tcsr = <&tcsr>; |
227 | ||
e07214db | 228 | gsbi1_i2c: i2c@12460000 { |
8c3166f5 | 229 | compatible = "qcom,i2c-qup-v1.1.1"; |
64b22b25 SK |
230 | pinctrl-0 = <&i2c1_pins &i2c1_pins_sleep>; |
231 | pinctrl-names = "default", "sleep"; | |
8c3166f5 | 232 | reg = <0x12460000 0x1000>; |
233 | interrupts = <0 194 IRQ_TYPE_NONE>; | |
234 | clocks = <&gcc GSBI1_QUP_CLK>, <&gcc GSBI1_H_CLK>; | |
235 | clock-names = "core", "iface"; | |
236 | #address-cells = <1>; | |
237 | #size-cells = <0>; | |
238 | }; | |
b2dc04c5 | 239 | |
8c3166f5 | 240 | }; |
241 | ||
242 | gsbi2: gsbi@12480000 { | |
243 | status = "disabled"; | |
244 | compatible = "qcom,gsbi-v1.0.0"; | |
4105d9d6 | 245 | cell-index = <2>; |
8c3166f5 | 246 | reg = <0x12480000 0x100>; |
247 | clocks = <&gcc GSBI2_H_CLK>; | |
248 | clock-names = "iface"; | |
249 | #address-cells = <1>; | |
250 | #size-cells = <1>; | |
251 | ranges; | |
252 | ||
4105d9d6 AG |
253 | syscon-tcsr = <&tcsr>; |
254 | ||
e07214db | 255 | gsbi2_i2c: i2c@124a0000 { |
8c3166f5 | 256 | compatible = "qcom,i2c-qup-v1.1.1"; |
257 | reg = <0x124a0000 0x1000>; | |
258 | interrupts = <0 196 IRQ_TYPE_NONE>; | |
259 | clocks = <&gcc GSBI2_QUP_CLK>, <&gcc GSBI2_H_CLK>; | |
260 | clock-names = "core", "iface"; | |
261 | #address-cells = <1>; | |
262 | #size-cells = <0>; | |
263 | }; | |
264 | }; | |
265 | ||
3f62b46b SK |
266 | gsbi3: gsbi@16200000 { |
267 | status = "disabled"; | |
268 | compatible = "qcom,gsbi-v1.0.0"; | |
504155ca | 269 | cell-index = <3>; |
3f62b46b SK |
270 | reg = <0x16200000 0x100>; |
271 | clocks = <&gcc GSBI3_H_CLK>; | |
272 | clock-names = "iface"; | |
273 | #address-cells = <1>; | |
274 | #size-cells = <1>; | |
275 | ranges; | |
e07214db | 276 | gsbi3_i2c: i2c@16280000 { |
3f62b46b | 277 | compatible = "qcom,i2c-qup-v1.1.1"; |
64b22b25 SK |
278 | pinctrl-0 = <&i2c3_pins &i2c3_pins_sleep>; |
279 | pinctrl-names = "default", "sleep"; | |
3f62b46b SK |
280 | reg = <0x16280000 0x1000>; |
281 | interrupts = <GIC_SPI 151 IRQ_TYPE_NONE>; | |
282 | clocks = <&gcc GSBI3_QUP_CLK>, | |
283 | <&gcc GSBI3_H_CLK>; | |
284 | clock-names = "core", "iface"; | |
5d31f606 JS |
285 | #address-cells = <1>; |
286 | #size-cells = <0>; | |
1099b26e BA |
287 | }; |
288 | }; | |
289 | ||
290 | gsbi5: gsbi@1a200000 { | |
291 | status = "disabled"; | |
292 | compatible = "qcom,gsbi-v1.0.0"; | |
293 | cell-index = <5>; | |
294 | reg = <0x1a200000 0x03>; | |
295 | clocks = <&gcc GSBI5_H_CLK>; | |
296 | clock-names = "iface"; | |
297 | #address-cells = <1>; | |
298 | #size-cells = <1>; | |
299 | ranges; | |
300 | ||
301 | gsbi5_serial: serial@1a240000 { | |
302 | compatible = "qcom,msm-uartdm-v1.3", "qcom,msm-uartdm"; | |
303 | reg = <0x1a240000 0x100>, | |
304 | <0x1a200000 0x03>; | |
305 | interrupts = <0 154 0x0>; | |
306 | clocks = <&gcc GSBI5_UART_CLK>, <&gcc GSBI5_H_CLK>; | |
307 | clock-names = "core", "iface"; | |
308 | status = "disabled"; | |
3f62b46b | 309 | }; |
b2dc04c5 SK |
310 | |
311 | gsbi5_spi: spi@1a280000 { | |
312 | compatible = "qcom,spi-qup-v1.1.1"; | |
313 | reg = <0x1a280000 0x1000>; | |
314 | interrupts = <0 155 0>; | |
315 | pinctrl-0 = <&spi5_default &spi5_sleep>; | |
316 | pinctrl-names = "default", "sleep"; | |
317 | clocks = <&gcc GSBI5_QUP_CLK>, <&gcc GSBI5_H_CLK>; | |
318 | clock-names = "core", "iface"; | |
319 | status = "disabled"; | |
320 | #address-cells = <1>; | |
321 | #size-cells = <0>; | |
322 | }; | |
3f62b46b SK |
323 | }; |
324 | ||
86e252a4 PG |
325 | gsbi6: gsbi@16500000 { |
326 | status = "disabled"; | |
327 | compatible = "qcom,gsbi-v1.0.0"; | |
328 | cell-index = <6>; | |
329 | reg = <0x16500000 0x03>; | |
330 | clocks = <&gcc GSBI6_H_CLK>; | |
331 | clock-names = "iface"; | |
332 | #address-cells = <1>; | |
333 | #size-cells = <1>; | |
334 | ranges; | |
335 | ||
336 | gsbi6_serial: serial@16540000 { | |
337 | compatible = "qcom,msm-uartdm-v1.3", "qcom,msm-uartdm"; | |
338 | reg = <0x16540000 0x100>, | |
339 | <0x16500000 0x03>; | |
340 | interrupts = <0 156 0x0>; | |
341 | clocks = <&gcc GSBI6_UART_CLK>, <&gcc GSBI6_H_CLK>; | |
342 | clock-names = "core", "iface"; | |
343 | status = "disabled"; | |
344 | }; | |
345 | }; | |
346 | ||
f335b8af KG |
347 | gsbi7: gsbi@16600000 { |
348 | status = "disabled"; | |
349 | compatible = "qcom,gsbi-v1.0.0"; | |
4105d9d6 | 350 | cell-index = <7>; |
f335b8af KG |
351 | reg = <0x16600000 0x100>; |
352 | clocks = <&gcc GSBI7_H_CLK>; | |
353 | clock-names = "iface"; | |
354 | #address-cells = <1>; | |
355 | #size-cells = <1>; | |
356 | ranges; | |
4105d9d6 AG |
357 | syscon-tcsr = <&tcsr>; |
358 | ||
d5d4654e | 359 | gsbi7_serial: serial@16640000 { |
f335b8af KG |
360 | compatible = "qcom,msm-uartdm-v1.3", "qcom,msm-uartdm"; |
361 | reg = <0x16640000 0x1000>, | |
362 | <0x16600000 0x1000>; | |
363 | interrupts = <0 158 0x0>; | |
364 | clocks = <&gcc GSBI7_UART_CLK>, <&gcc GSBI7_H_CLK>; | |
365 | clock-names = "core", "iface"; | |
366 | status = "disabled"; | |
367 | }; | |
368 | }; | |
369 | ||
6a607e03 JS |
370 | rng@1a500000 { |
371 | compatible = "qcom,prng"; | |
372 | reg = <0x1a500000 0x200>; | |
373 | clocks = <&gcc PRNG_CLK>; | |
374 | clock-names = "core"; | |
375 | }; | |
376 | ||
f335b8af KG |
377 | qcom,ssbi@500000 { |
378 | compatible = "qcom,ssbi"; | |
379 | reg = <0x00500000 0x1000>; | |
380 | qcom,controller-type = "pmic-arbiter"; | |
874443fe SK |
381 | |
382 | pmicintc: pmic@0 { | |
383 | compatible = "qcom,pm8921"; | |
384 | interrupt-parent = <&tlmm_pinmux>; | |
385 | interrupts = <74 8>; | |
386 | #interrupt-cells = <2>; | |
387 | interrupt-controller; | |
388 | #address-cells = <1>; | |
389 | #size-cells = <0>; | |
390 | ||
391 | pm8921_gpio: gpio@150 { | |
392 | ||
2ca9c2a4 SB |
393 | compatible = "qcom,pm8921-gpio", |
394 | "qcom,ssbi-gpio"; | |
874443fe SK |
395 | reg = <0x150>; |
396 | interrupts = <192 1>, <193 1>, <194 1>, | |
397 | <195 1>, <196 1>, <197 1>, | |
398 | <198 1>, <199 1>, <200 1>, | |
399 | <201 1>, <202 1>, <203 1>, | |
400 | <204 1>, <205 1>, <206 1>, | |
401 | <207 1>, <208 1>, <209 1>, | |
402 | <210 1>, <211 1>, <212 1>, | |
403 | <213 1>, <214 1>, <215 1>, | |
404 | <216 1>, <217 1>, <218 1>, | |
405 | <219 1>, <220 1>, <221 1>, | |
406 | <222 1>, <223 1>, <224 1>, | |
407 | <225 1>, <226 1>, <227 1>, | |
408 | <228 1>, <229 1>, <230 1>, | |
409 | <231 1>, <232 1>, <233 1>, | |
410 | <234 1>, <235 1>; | |
411 | ||
412 | gpio-controller; | |
413 | #gpio-cells = <2>; | |
414 | ||
415 | }; | |
bce36046 SK |
416 | |
417 | pm8921_mpps: mpps@50 { | |
2ca9c2a4 SB |
418 | compatible = "qcom,pm8921-mpp", |
419 | "qcom,ssbi-mpp"; | |
bce36046 SK |
420 | reg = <0x50>; |
421 | gpio-controller; | |
422 | #gpio-cells = <2>; | |
423 | interrupts = | |
424 | <128 1>, <129 1>, <130 1>, <131 1>, | |
425 | <132 1>, <133 1>, <134 1>, <135 1>, | |
426 | <136 1>, <137 1>, <138 1>, <139 1>; | |
427 | }; | |
428 | ||
bbf89b96 SK |
429 | rtc@11d { |
430 | compatible = "qcom,pm8921-rtc"; | |
431 | interrupt-parent = <&pmicintc>; | |
432 | interrupts = <39 1>; | |
433 | reg = <0x11d>; | |
434 | allow-set-time; | |
435 | }; | |
436 | ||
3050c5f5 SK |
437 | pwrkey@1c { |
438 | compatible = "qcom,pm8921-pwrkey"; | |
439 | reg = <0x1c>; | |
440 | interrupt-parent = <&pmicintc>; | |
441 | interrupts = <50 1>, <51 1>; | |
442 | debounce = <15625>; | |
443 | pull-up; | |
444 | }; | |
874443fe | 445 | }; |
f335b8af KG |
446 | }; |
447 | ||
448 | gcc: clock-controller@900000 { | |
449 | compatible = "qcom,gcc-apq8064"; | |
450 | reg = <0x00900000 0x4000>; | |
451 | #clock-cells = <1>; | |
452 | #reset-cells = <1>; | |
453 | }; | |
3fe5e3ce | 454 | |
1e1177bf KG |
455 | lcc: clock-controller@28000000 { |
456 | compatible = "qcom,lcc-apq8064"; | |
457 | reg = <0x28000000 0x1000>; | |
458 | #clock-cells = <1>; | |
459 | #reset-cells = <1>; | |
460 | }; | |
461 | ||
3fe5e3ce SB |
462 | mmcc: clock-controller@4000000 { |
463 | compatible = "qcom,mmcc-apq8064"; | |
464 | reg = <0x4000000 0x1000>; | |
465 | #clock-cells = <1>; | |
466 | #reset-cells = <1>; | |
467 | }; | |
045644ff | 468 | |
dc2f8152 SK |
469 | l2cc: clock-controller@2011000 { |
470 | compatible = "syscon"; | |
471 | reg = <0x2011000 0x1000>; | |
472 | }; | |
473 | ||
474 | rpm@108000 { | |
475 | compatible = "qcom,rpm-apq8064"; | |
476 | reg = <0x108000 0x1000>; | |
477 | qcom,ipc = <&l2cc 0x8 2>; | |
478 | ||
479 | interrupts = <GIC_SPI 19 IRQ_TYPE_EDGE_RISING>, | |
480 | <GIC_SPI 21 IRQ_TYPE_EDGE_RISING>, | |
481 | <GIC_SPI 22 IRQ_TYPE_EDGE_RISING>; | |
482 | interrupt-names = "ack", "err", "wakeup"; | |
483 | ||
aac1b297 GD |
484 | rpmcc: clock-controller { |
485 | compatible = "qcom,rpmcc-apq8064", "qcom,rpmcc"; | |
486 | #clock-cells = <1>; | |
487 | }; | |
488 | ||
dc2f8152 SK |
489 | regulators { |
490 | compatible = "qcom,rpm-pm8921-regulators"; | |
491 | ||
2bce6e26 BA |
492 | pm8921_s1: s1 {}; |
493 | pm8921_s2: s2 {}; | |
494 | pm8921_s3: s3 {}; | |
495 | pm8921_s4: s4 {}; | |
496 | pm8921_s7: s7 {}; | |
497 | pm8921_s8: s8 {}; | |
498 | ||
499 | pm8921_l1: l1 {}; | |
500 | pm8921_l2: l2 {}; | |
501 | pm8921_l3: l3 {}; | |
502 | pm8921_l4: l4 {}; | |
503 | pm8921_l5: l5 {}; | |
504 | pm8921_l6: l6 {}; | |
505 | pm8921_l7: l7 {}; | |
506 | pm8921_l8: l8 {}; | |
507 | pm8921_l9: l9 {}; | |
508 | pm8921_l10: l10 {}; | |
509 | pm8921_l11: l11 {}; | |
510 | pm8921_l12: l12 {}; | |
511 | pm8921_l14: l14 {}; | |
512 | pm8921_l15: l15 {}; | |
513 | pm8921_l16: l16 {}; | |
514 | pm8921_l17: l17 {}; | |
515 | pm8921_l18: l18 {}; | |
516 | pm8921_l21: l21 {}; | |
517 | pm8921_l22: l22 {}; | |
518 | pm8921_l23: l23 {}; | |
519 | pm8921_l24: l24 {}; | |
520 | pm8921_l25: l25 {}; | |
521 | pm8921_l26: l26 {}; | |
522 | pm8921_l27: l27 {}; | |
523 | pm8921_l28: l28 {}; | |
524 | pm8921_l29: l29 {}; | |
525 | ||
526 | pm8921_lvs1: lvs1 {}; | |
527 | pm8921_lvs2: lvs2 {}; | |
528 | pm8921_lvs3: lvs3 {}; | |
529 | pm8921_lvs4: lvs4 {}; | |
530 | pm8921_lvs5: lvs5 {}; | |
531 | pm8921_lvs6: lvs6 {}; | |
532 | pm8921_lvs7: lvs7 {}; | |
533 | ||
534 | pm8921_usb_switch: usb-switch {}; | |
535 | ||
dc2f8152 SK |
536 | pm8921_hdmi_switch: hdmi-switch { |
537 | bias-pull-down; | |
538 | }; | |
2bce6e26 BA |
539 | |
540 | pm8921_ncp: ncp {}; | |
dc2f8152 SK |
541 | }; |
542 | }; | |
543 | ||
ea986611 SK |
544 | usb1_phy: phy@12500000 { |
545 | compatible = "qcom,usb-otg-ci"; | |
546 | reg = <0x12500000 0x400>; | |
547 | interrupts = <GIC_SPI 100 IRQ_TYPE_NONE>; | |
548 | status = "disabled"; | |
549 | dr_mode = "host"; | |
550 | ||
551 | clocks = <&gcc USB_HS1_XCVR_CLK>, | |
552 | <&gcc USB_HS1_H_CLK>; | |
553 | clock-names = "core", "iface"; | |
554 | ||
555 | resets = <&gcc USB_HS1_RESET>; | |
556 | reset-names = "link"; | |
557 | }; | |
558 | ||
223280b1 SK |
559 | usb3_phy: phy@12520000 { |
560 | compatible = "qcom,usb-otg-ci"; | |
561 | reg = <0x12520000 0x400>; | |
562 | interrupts = <GIC_SPI 188 IRQ_TYPE_NONE>; | |
563 | status = "disabled"; | |
564 | dr_mode = "host"; | |
565 | ||
566 | clocks = <&gcc USB_HS3_XCVR_CLK>, | |
567 | <&gcc USB_HS3_H_CLK>; | |
568 | clock-names = "core", "iface"; | |
569 | ||
570 | resets = <&gcc USB_HS3_RESET>; | |
571 | reset-names = "link"; | |
572 | }; | |
573 | ||
574 | usb4_phy: phy@12530000 { | |
575 | compatible = "qcom,usb-otg-ci"; | |
576 | reg = <0x12530000 0x400>; | |
577 | interrupts = <GIC_SPI 215 IRQ_TYPE_NONE>; | |
578 | status = "disabled"; | |
579 | dr_mode = "host"; | |
580 | ||
581 | clocks = <&gcc USB_HS4_XCVR_CLK>, | |
582 | <&gcc USB_HS4_H_CLK>; | |
583 | clock-names = "core", "iface"; | |
584 | ||
585 | resets = <&gcc USB_HS4_RESET>; | |
586 | reset-names = "link"; | |
587 | }; | |
588 | ||
ea986611 SK |
589 | gadget1: gadget@12500000 { |
590 | compatible = "qcom,ci-hdrc"; | |
591 | reg = <0x12500000 0x400>; | |
592 | status = "disabled"; | |
593 | dr_mode = "peripheral"; | |
594 | interrupts = <GIC_SPI 100 IRQ_TYPE_NONE>; | |
595 | usb-phy = <&usb1_phy>; | |
596 | }; | |
597 | ||
598 | usb1: usb@12500000 { | |
599 | compatible = "qcom,ehci-host"; | |
600 | reg = <0x12500000 0x400>; | |
601 | interrupts = <GIC_SPI 100 IRQ_TYPE_NONE>; | |
602 | status = "disabled"; | |
603 | usb-phy = <&usb1_phy>; | |
604 | }; | |
605 | ||
223280b1 SK |
606 | usb3: usb@12520000 { |
607 | compatible = "qcom,ehci-host"; | |
608 | reg = <0x12520000 0x400>; | |
609 | interrupts = <GIC_SPI 188 IRQ_TYPE_NONE>; | |
610 | status = "disabled"; | |
611 | usb-phy = <&usb3_phy>; | |
612 | }; | |
613 | ||
614 | usb4: usb@12530000 { | |
615 | compatible = "qcom,ehci-host"; | |
616 | reg = <0x12530000 0x400>; | |
617 | interrupts = <GIC_SPI 215 IRQ_TYPE_NONE>; | |
618 | status = "disabled"; | |
619 | usb-phy = <&usb4_phy>; | |
620 | }; | |
621 | ||
e629335f SK |
622 | sata_phy0: phy@1b400000 { |
623 | compatible = "qcom,apq8064-sata-phy"; | |
624 | status = "disabled"; | |
625 | reg = <0x1b400000 0x200>; | |
626 | reg-names = "phy_mem"; | |
627 | clocks = <&gcc SATA_PHY_CFG_CLK>; | |
628 | clock-names = "cfg"; | |
629 | #phy-cells = <0>; | |
630 | }; | |
631 | ||
632 | sata0: sata@29000000 { | |
633 | compatible = "generic-ahci"; | |
634 | status = "disabled"; | |
635 | reg = <0x29000000 0x180>; | |
636 | interrupts = <GIC_SPI 209 IRQ_TYPE_NONE>; | |
637 | ||
638 | clocks = <&gcc SFAB_SATA_S_H_CLK>, | |
639 | <&gcc SATA_H_CLK>, | |
640 | <&gcc SATA_A_CLK>, | |
641 | <&gcc SATA_RXOOB_CLK>, | |
642 | <&gcc SATA_PMALIVE_CLK>; | |
643 | clock-names = "slave_iface", | |
644 | "iface", | |
645 | "bus", | |
646 | "rxoob", | |
647 | "core_pmalive"; | |
648 | ||
649 | assigned-clocks = <&gcc SATA_RXOOB_CLK>, | |
650 | <&gcc SATA_PMALIVE_CLK>; | |
651 | assigned-clock-rates = <100000000>, <100000000>; | |
652 | ||
653 | phys = <&sata_phy0>; | |
654 | phy-names = "sata-phy"; | |
655 | }; | |
656 | ||
045644ff | 657 | /* Temporary fixed regulator */ |
edb81ca3 SK |
658 | sdcc1bam:dma@12402000{ |
659 | compatible = "qcom,bam-v1.3.0"; | |
660 | reg = <0x12402000 0x8000>; | |
661 | interrupts = <0 98 0>; | |
662 | clocks = <&gcc SDC1_H_CLK>; | |
663 | clock-names = "bam_clk"; | |
664 | #dma-cells = <1>; | |
665 | qcom,ee = <0>; | |
666 | }; | |
667 | ||
668 | sdcc3bam:dma@12182000{ | |
669 | compatible = "qcom,bam-v1.3.0"; | |
670 | reg = <0x12182000 0x8000>; | |
671 | interrupts = <0 96 0>; | |
672 | clocks = <&gcc SDC3_H_CLK>; | |
673 | clock-names = "bam_clk"; | |
674 | #dma-cells = <1>; | |
675 | qcom,ee = <0>; | |
676 | }; | |
677 | ||
0be5fef1 SK |
678 | sdcc4bam:dma@121c2000{ |
679 | compatible = "qcom,bam-v1.3.0"; | |
680 | reg = <0x121c2000 0x8000>; | |
681 | interrupts = <0 95 0>; | |
682 | clocks = <&gcc SDC4_H_CLK>; | |
683 | clock-names = "bam_clk"; | |
684 | #dma-cells = <1>; | |
685 | qcom,ee = <0>; | |
686 | }; | |
687 | ||
045644ff SK |
688 | amba { |
689 | compatible = "arm,amba-bus"; | |
690 | #address-cells = <1>; | |
691 | #size-cells = <1>; | |
692 | ranges; | |
693 | sdcc1: sdcc@12400000 { | |
694 | status = "disabled"; | |
695 | compatible = "arm,pl18x", "arm,primecell"; | |
696 | arm,primecell-periphid = <0x00051180>; | |
697 | reg = <0x12400000 0x2000>; | |
698 | interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>; | |
699 | interrupt-names = "cmd_irq"; | |
700 | clocks = <&gcc SDC1_CLK>, <&gcc SDC1_H_CLK>; | |
701 | clock-names = "mclk", "apb_pclk"; | |
702 | bus-width = <8>; | |
703 | max-frequency = <96000000>; | |
704 | non-removable; | |
705 | cap-sd-highspeed; | |
706 | cap-mmc-highspeed; | |
edb81ca3 SK |
707 | dmas = <&sdcc1bam 2>, <&sdcc1bam 1>; |
708 | dma-names = "tx", "rx"; | |
045644ff SK |
709 | }; |
710 | ||
711 | sdcc3: sdcc@12180000 { | |
712 | compatible = "arm,pl18x", "arm,primecell"; | |
713 | arm,primecell-periphid = <0x00051180>; | |
714 | status = "disabled"; | |
715 | reg = <0x12180000 0x2000>; | |
716 | interrupts = <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>; | |
717 | interrupt-names = "cmd_irq"; | |
718 | clocks = <&gcc SDC3_CLK>, <&gcc SDC3_H_CLK>; | |
719 | clock-names = "mclk", "apb_pclk"; | |
720 | bus-width = <4>; | |
721 | cap-sd-highspeed; | |
722 | cap-mmc-highspeed; | |
723 | max-frequency = <192000000>; | |
724 | no-1-8-v; | |
edb81ca3 SK |
725 | dmas = <&sdcc3bam 2>, <&sdcc3bam 1>; |
726 | dma-names = "tx", "rx"; | |
045644ff | 727 | }; |
0be5fef1 SK |
728 | |
729 | sdcc4: sdcc@121c0000 { | |
730 | compatible = "arm,pl18x", "arm,primecell"; | |
731 | arm,primecell-periphid = <0x00051180>; | |
732 | status = "disabled"; | |
733 | reg = <0x121c0000 0x2000>; | |
734 | interrupts = <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>; | |
735 | interrupt-names = "cmd_irq"; | |
736 | clocks = <&gcc SDC4_CLK>, <&gcc SDC4_H_CLK>; | |
737 | clock-names = "mclk", "apb_pclk"; | |
738 | bus-width = <4>; | |
739 | cap-sd-highspeed; | |
740 | cap-mmc-highspeed; | |
741 | max-frequency = <48000000>; | |
0be5fef1 SK |
742 | dmas = <&sdcc4bam 2>, <&sdcc4bam 1>; |
743 | dma-names = "tx", "rx"; | |
744 | pinctrl-names = "default"; | |
745 | pinctrl-0 = <&sdc4_gpios>; | |
746 | }; | |
045644ff | 747 | }; |
4105d9d6 AG |
748 | |
749 | tcsr: syscon@1a400000 { | |
750 | compatible = "qcom,tcsr-apq8064", "syscon"; | |
751 | reg = <0x1a400000 0x100>; | |
752 | }; | |
bcc74b09 SV |
753 | |
754 | pcie: pci@1b500000 { | |
755 | compatible = "qcom,pcie-apq8064", "snps,dw-pcie"; | |
756 | reg = <0x1b500000 0x1000 | |
757 | 0x1b502000 0x80 | |
758 | 0x1b600000 0x100 | |
759 | 0x0ff00000 0x100000>; | |
760 | reg-names = "dbi", "elbi", "parf", "config"; | |
761 | device_type = "pci"; | |
762 | linux,pci-domain = <0>; | |
763 | bus-range = <0x00 0xff>; | |
764 | num-lanes = <1>; | |
765 | #address-cells = <3>; | |
766 | #size-cells = <2>; | |
767 | ranges = <0x81000000 0 0 0x0fe00000 0 0x00100000 /* I/O */ | |
768 | 0x82000000 0 0 0x08000000 0 0x07e00000>; /* memory */ | |
769 | interrupts = <GIC_SPI 238 IRQ_TYPE_NONE>; | |
770 | interrupt-names = "msi"; | |
771 | #interrupt-cells = <1>; | |
772 | interrupt-map-mask = <0 0 0 0x7>; | |
773 | interrupt-map = <0 0 0 1 &intc 0 36 IRQ_TYPE_LEVEL_HIGH>, /* int_a */ | |
774 | <0 0 0 2 &intc 0 37 IRQ_TYPE_LEVEL_HIGH>, /* int_b */ | |
775 | <0 0 0 3 &intc 0 38 IRQ_TYPE_LEVEL_HIGH>, /* int_c */ | |
776 | <0 0 0 4 &intc 0 39 IRQ_TYPE_LEVEL_HIGH>; /* int_d */ | |
777 | clocks = <&gcc PCIE_A_CLK>, | |
778 | <&gcc PCIE_H_CLK>, | |
779 | <&gcc PCIE_PHY_REF_CLK>; | |
780 | clock-names = "core", "iface", "phy"; | |
781 | resets = <&gcc PCIE_ACLK_RESET>, | |
782 | <&gcc PCIE_HCLK_RESET>, | |
783 | <&gcc PCIE_POR_RESET>, | |
784 | <&gcc PCIE_PCI_RESET>, | |
785 | <&gcc PCIE_PHY_RESET>; | |
786 | reset-names = "axi", "ahb", "por", "pci", "phy"; | |
787 | status = "disabled"; | |
788 | }; | |
f335b8af KG |
789 | }; |
790 | }; | |
a30e78bd | 791 | #include "qcom-apq8064-pins.dtsi" |