[linux-block.git] / arch / arm / boot / dts / ox810se.dtsi

/*
 * ox810se.dtsi - Device tree file for Oxford Semiconductor OX810SE SoC
 *
 * Copyright (C) 2016 Neil Armstrong <narmstrong@baylibre.com>
 *
 * Licensed under GPLv2 or later
 */

/include/ "skeleton.dtsi"
#include <dt-bindings/clock/oxsemi,ox810se.h>
#include <dt-bindings/reset/oxsemi,ox810se.h>

/ {
	compatible = "oxsemi,ox810se";

	cpus {
		#address-cells = <0>;
		#size-cells = <0>;

		cpu {
			device_type = "cpu";
			compatible = "arm,arm926ej-s";
			clocks = <&armclk>;
		};
	};

	memory {
		/* Max 256MB @ 0x48000000 */
		reg = <0x48000000 0x10000000>;
	};

	clocks {
		osc: oscillator {
			compatible = "fixed-clock";
			#clock-cells = <0>;
			clock-frequency = <25000000>;
		};

		gmacclk: gmacclk {
			compatible = "fixed-clock";
			#clock-cells = <0>;
			clock-frequency = <125000000>;
		};

		rpsclk: rpsclk {
			compatible = "fixed-factor-clock";
			#clock-cells = <0>;
			clock-div = <1>;
			clock-mult = <1>;
			clocks = <&osc>;
		};

		pll400: pll400 {
			compatible = "fixed-clock";
			#clock-cells = <0>;
			clock-frequency = <733333333>;
		};

		sysclk: sysclk {
			compatible = "fixed-factor-clock";
			#clock-cells = <0>;
			clock-div = <4>;
			clock-mult = <1>;
			clocks = <&pll400>;
		};

		armclk: armclk {
			compatible = "fixed-factor-clock";
			#clock-cells = <0>;
			clock-div = <2>;
			clock-mult = <1>;
			clocks = <&pll400>;
		};
	};

	soc {
		#address-cells = <1>;
		#size-cells = <1>;
		compatible = "simple-bus";
		ranges;
		interrupt-parent = <&intc>;

		apb-bridge@44000000 {
			#address-cells = <1>;
			#size-cells = <1>;
			compatible = "simple-bus";
			ranges = <0 0x44000000 0x1000000>;

			pinctrl: pinctrl {
				compatible = "oxsemi,ox810se-pinctrl";

				/* Regmap for sys registers */
				oxsemi,sys-ctrl = <&sys>;

				pinctrl_uart0: uart0 {
					uart0a {
						pins = "gpio31";
						function = "fct3";
					};
					uart0b {
						pins = "gpio32";
						function = "fct3";
					};
				};

				pinctrl_uart0_modem: uart0_modem {
					uart0c {
						pins = "gpio27";
						function = "fct3";
					};
					uart0d {
						pins = "gpio28";
						function = "fct3";
					};
					uart0e {
						pins = "gpio29";
						function = "fct3";
					};
					uart0f {
						pins = "gpio30";
						function = "fct3";
					};
					uart0g {
						pins = "gpio33";
						function = "fct3";
					};
					uart0h {
						pins = "gpio34";
						function = "fct3";
					};
				};

				pinctrl_uart1: uart1 {
					uart1a {
						pins = "gpio20";
						function = "fct3";
					};
					uart1b {
						pins = "gpio22";
						function = "fct3";
					};
				};

				pinctrl_uart1_modem: uart1_modem {
					uart1c {
						pins = "gpio8";
						function = "fct3";
					};
					uart1d {
						pins = "gpio9";
						function = "fct3";
					};
					uart1e {
						pins = "gpio23";
						function = "fct3";
					};
					uart1f {
						pins = "gpio24";
						function = "fct3";
					};
					uart1g {
						pins = "gpio25";
						function = "fct3";
					};
					uart1h {
						pins = "gpio26";
						function = "fct3";
					};
				};

				pinctrl_uart2: uart2 {
					uart2a {
						pins = "gpio6";
						function = "fct3";
					};
					uart2b {
						pins = "gpio7";
						function = "fct3";
					};
				};

				pinctrl_uart2_modem: uart2_modem {
					uart2c {
						pins = "gpio0";
						function = "fct3";
					};
					uart2d {
						pins = "gpio1";
						function = "fct3";
					};
					uart2e {
						pins = "gpio2";
						function = "fct3";
					};
					uart2f {
						pins = "gpio3";
						function = "fct3";
					};
					uart2g {
						pins = "gpio4";
						function = "fct3";
					};
					uart2h {
						pins = "gpio5";
						function = "fct3";
					};
				};
			};

			gpio0: gpio@0 {
				compatible = "oxsemi,ox810se-gpio";
				reg = <0x000000 0x100000>;
				interrupts = <21>;
				#gpio-cells = <2>;
				gpio-controller;
				interrupt-controller;
				#interrupt-cells = <2>;
				ngpios = <32>;
				oxsemi,gpio-bank = <0>;
				gpio-ranges = <&pinctrl 0 0 32>;
			};

			gpio1: gpio@100000 {
				compatible = "oxsemi,ox810se-gpio";
				reg = <0x100000 0x100000>;
				interrupts = <22>;
				#gpio-cells = <2>;
				gpio-controller;
				interrupt-controller;
				#interrupt-cells = <2>;
				ngpios = <3>;
				oxsemi,gpio-bank = <1>;
				gpio-ranges = <&pinctrl 0 32 3>;
			};

			uart0: serial@200000 {
			       compatible = "ns16550a";
			       reg = <0x200000 0x100000>;
			       clocks = <&sysclk>;
			       interrupts = <23>;
			       reg-shift = <0>;
			       fifo-size = <16>;
			       reg-io-width = <1>;
			       current-speed = <115200>;
			       no-loopback-test;
			       status = "disabled";
			       resets = <&reset RESET_UART1>;
			};

			uart1: serial@300000 {
			       compatible = "ns16550a";
			       reg = <0x300000 0x100000>;
			       clocks = <&sysclk>;
			       interrupts = <24>;
			       reg-shift = <0>;
			       fifo-size = <16>;
			       reg-io-width = <1>;
			       current-speed = <115200>;
			       no-loopback-test;
			       status = "disabled";
			       resets = <&reset RESET_UART2>;
			};

			uart2: serial@900000 {
			       compatible = "ns16550a";
			       reg = <0x900000 0x100000>;
			       clocks = <&sysclk>;
			       interrupts = <29>;
			       reg-shift = <0>;
			       fifo-size = <16>;
			       reg-io-width = <1>;
			       current-speed = <115200>;
			       no-loopback-test;
			       status = "disabled";
			       resets = <&reset RESET_UART3>;
			};

			uart3: serial@a00000 {
			       compatible = "ns16550a";
			       reg = <0xa00000 0x100000>;
			       clocks = <&sysclk>;
			       interrupts = <30>;
			       reg-shift = <0>;
			       fifo-size = <16>;
			       reg-io-width = <1>;
			       current-speed = <115200>;
			       no-loopback-test;
			       status = "disabled";
			       resets = <&reset RESET_UART4>;
			};
		};

		apb-bridge@45000000 {
			#address-cells = <1>;
			#size-cells = <1>;
			compatible = "simple-bus";
			ranges = <0 0x45000000 0x1000000>;

			sys: sys-ctrl@0 {
				compatible = "oxsemi,ox810se-sys-ctrl", "syscon", "simple-mfd";
				reg = <0x000000 0x100000>;

				reset: reset-controller {
					compatible = "oxsemi,ox810se-reset";
					#reset-cells = <1>;
				};

				stdclk: stdclk {
					compatible = "oxsemi,ox810se-stdclk";
					#clock-cells = <1>;
				};
			};

			rps@300000 {
				#address-cells = <1>;
				#size-cells = <1>;
				compatible = "simple-bus";
				ranges = <0 0x300000 0x100000>;

				intc: interrupt-controller@0 {
					compatible = "oxsemi,ox810se-rps-irq";
					interrupt-controller;
					reg = <0 0x200>;
					#interrupt-cells = <1>;
					valid-mask = <0xFFFFFFFF>;
					clear-mask = <0>;
				};

				timer0: timer@200 {
					compatible = "oxsemi,ox810se-rps-timer";
					reg = <0x200 0x40>;
					clocks = <&rpsclk>;
					interrupts = <4 5>;
				};
			};
		};
	};
};
Commit	Line	Data
84316f4e NA	1	/*
	2	* ox810se.dtsi - Device tree file for Oxford Semiconductor OX810SE SoC
	3	*
	4	* Copyright (C) 2016 Neil Armstrong <narmstrong@baylibre.com>
	5	*
	6	* Licensed under GPLv2 or later
	7	*/
	8
	9	/include/ "skeleton.dtsi"
ed4d903d NA	10	#include <dt-bindings/clock/oxsemi,ox810se.h>
ed4d903d NA	11	#include <dt-bindings/reset/oxsemi,ox810se.h>
84316f4e NA	12
	13	/ {
	14	compatible = "oxsemi,ox810se";
	15
	16	cpus {
	17	#address-cells = <0>;
	18	#size-cells = <0>;
	19
	20	cpu {
	21	device_type = "cpu";
	22	compatible = "arm,arm926ej-s";
	23	clocks = <&armclk>;
	24	};
	25	};
	26
	27	memory {
	28	/* Max 256MB @ 0x48000000 */
	29	reg = <0x48000000 0x10000000>;
	30	};
	31
	32	clocks {
	33	osc: oscillator {
	34	compatible = "fixed-clock";
	35	#clock-cells = <0>;
	36	clock-frequency = <25000000>;
	37	};
	38
	39	gmacclk: gmacclk {
	40	compatible = "fixed-clock";
	41	#clock-cells = <0>;
	42	clock-frequency = <125000000>;
	43	};
	44
	45	rpsclk: rpsclk {
	46	compatible = "fixed-factor-clock";
	47	#clock-cells = <0>;
	48	clock-div = <1>;
	49	clock-mult = <1>;
	50	clocks = <&osc>;
	51	};
	52
	53	pll400: pll400 {
	54	compatible = "fixed-clock";
	55	#clock-cells = <0>;
	56	clock-frequency = <733333333>;
	57	};
	58
	59	sysclk: sysclk {
	60	compatible = "fixed-factor-clock";
	61	#clock-cells = <0>;
	62	clock-div = <4>;
	63	clock-mult = <1>;
	64	clocks = <&pll400>;
	65	};
	66
	67	armclk: armclk {
	68	compatible = "fixed-factor-clock";
	69	#clock-cells = <0>;
	70	clock-div = <2>;
	71	clock-mult = <1>;
	72	clocks = <&pll400>;
	73	};
	74	};
	75
76	soc {
77	#address-cells = <1>;
78	#size-cells = <1>;
79	compatible = "simple-bus";
80	ranges;
81	interrupt-parent = <&intc>;
82
83	apb-bridge@44000000 {
84	#address-cells = <1>;
85	#size-cells = <1>;
86	compatible = "simple-bus";
87	ranges = <0 0x44000000 0x1000000>;
88
89	pinctrl: pinctrl {
90	compatible = "oxsemi,ox810se-pinctrl";
91
92	/* Regmap for sys registers */
93	oxsemi,sys-ctrl = <&sys>;
94
95	pinctrl_uart0: uart0 {
96	uart0a {
97	pins = "gpio31";
98	function = "fct3";
99	};
100	uart0b {
101	pins = "gpio32";
102	function = "fct3";
103	};
104	};
105
106	pinctrl_uart0_modem: uart0_modem {
107	uart0c {
108	pins = "gpio27";
109	function = "fct3";
110	};
111	uart0d {
112	pins = "gpio28";
113	function = "fct3";
114	};
115	uart0e {
116	pins = "gpio29";
117	function = "fct3";
118	};
119	uart0f {
120	pins = "gpio30";
121	function = "fct3";
122	};
123	uart0g {
124	pins = "gpio33";
125	function = "fct3";
126	};
127	uart0h {
128	pins = "gpio34";
129	function = "fct3";
130	};
131	};
132
133	pinctrl_uart1: uart1 {
134	uart1a {
135	pins = "gpio20";
136	function = "fct3";
137	};
138	uart1b {
139	pins = "gpio22";
140	function = "fct3";
141	};
142	};
143
144	pinctrl_uart1_modem: uart1_modem {
145	uart1c {
146	pins = "gpio8";
147	function = "fct3";
148	};
149	uart1d {
150	pins = "gpio9";
151	function = "fct3";
152	};
153	uart1e {
154	pins = "gpio23";
155	function = "fct3";
156	};
157	uart1f {
158	pins = "gpio24";
159	function = "fct3";
160	};
161	uart1g {
162	pins = "gpio25";
163	function = "fct3";
164	};
165	uart1h {
166	pins = "gpio26";
167	function = "fct3";
168	};
169	};
170
171	pinctrl_uart2: uart2 {
172	uart2a {
173	pins = "gpio6";
174	function = "fct3";
175	};
176	uart2b {
177	pins = "gpio7";
178	function = "fct3";
179	};
180	};
181
182	pinctrl_uart2_modem: uart2_modem {
183	uart2c {
184	pins = "gpio0";
185	function = "fct3";
186	};
187	uart2d {
188	pins = "gpio1";
189	function = "fct3";
190	};
191	uart2e {
192	pins = "gpio2";
193	function = "fct3";
194	};
195	uart2f {
196	pins = "gpio3";
197	function = "fct3";
198	};
199	uart2g {
200	pins = "gpio4";
201	function = "fct3";
202	};
203	uart2h {
204	pins = "gpio5";
205	function = "fct3";
206	};
207	};
208	};
209
8dccafaa	210	gpio0: gpio@0 {
84316f4e NA	211	compatible = "oxsemi,ox810se-gpio";
	212	reg = <0x000000 0x100000>;
	213	interrupts = <21>;
	214	#gpio-cells = <2>;
	215	gpio-controller;
	216	interrupt-controller;
	217	#interrupt-cells = <2>;
	218	ngpios = <32>;
	219	oxsemi,gpio-bank = <0>;
	220	gpio-ranges = <&pinctrl 0 0 32>;
	221	};
	222
	223	gpio1: gpio@100000 {
	224	compatible = "oxsemi,ox810se-gpio";
	225	reg = <0x100000 0x100000>;
	226	interrupts = <22>;
	227	#gpio-cells = <2>;
	228	gpio-controller;
	229	interrupt-controller;
	230	#interrupt-cells = <2>;
	231	ngpios = <3>;
	232	oxsemi,gpio-bank = <1>;
	233	gpio-ranges = <&pinctrl 0 32 3>;
	234	};
	235
	236	uart0: serial@200000 {
	237	compatible = "ns16550a";
	238	reg = <0x200000 0x100000>;
	239	clocks = <&sysclk>;
	240	interrupts = <23>;
	241	reg-shift = <0>;
	242	fifo-size = <16>;
	243	reg-io-width = <1>;
	244	current-speed = <115200>;
	245	no-loopback-test;
	246	status = "disabled";
ed4d903d	247	resets = <&reset RESET_UART1>;
84316f4e NA	248	};
	249
	250	uart1: serial@300000 {
	251	compatible = "ns16550a";
	252	reg = <0x300000 0x100000>;
	253	clocks = <&sysclk>;
	254	interrupts = <24>;
	255	reg-shift = <0>;
	256	fifo-size = <16>;
	257	reg-io-width = <1>;
	258	current-speed = <115200>;
	259	no-loopback-test;
	260	status = "disabled";
ed4d903d	261	resets = <&reset RESET_UART2>;
84316f4e NA	262	};
	263
	264	uart2: serial@900000 {
	265	compatible = "ns16550a";
	266	reg = <0x900000 0x100000>;
	267	clocks = <&sysclk>;
	268	interrupts = <29>;
	269	reg-shift = <0>;
	270	fifo-size = <16>;
	271	reg-io-width = <1>;
	272	current-speed = <115200>;
	273	no-loopback-test;
	274	status = "disabled";
ed4d903d	275	resets = <&reset RESET_UART3>;
84316f4e NA	276	};
	277
	278	uart3: serial@a00000 {
	279	compatible = "ns16550a";
	280	reg = <0xa00000 0x100000>;
	281	clocks = <&sysclk>;
	282	interrupts = <30>;
	283	reg-shift = <0>;
	284	fifo-size = <16>;
	285	reg-io-width = <1>;
	286	current-speed = <115200>;
	287	no-loopback-test;
	288	status = "disabled";
ed4d903d	289	resets = <&reset RESET_UART4>;
84316f4e NA	290	};
	291	};
	292
	293	apb-bridge@45000000 {
	294	#address-cells = <1>;
	295	#size-cells = <1>;
	296	compatible = "simple-bus";
	297	ranges = <0 0x45000000 0x1000000>;
	298
8dccafaa	299	sys: sys-ctrl@0 {
84316f4e NA	300	compatible = "oxsemi,ox810se-sys-ctrl", "syscon", "simple-mfd";
	301	reg = <0x000000 0x100000>;
	302
	303	reset: reset-controller {
	304	compatible = "oxsemi,ox810se-reset";
	305	#reset-cells = <1>;
	306	};
	307
	308	stdclk: stdclk {
	309	compatible = "oxsemi,ox810se-stdclk";
	310	#clock-cells = <1>;
	311	};
	312	};
	313
	314	rps@300000 {
	315	#address-cells = <1>;
	316	#size-cells = <1>;
	317	compatible = "simple-bus";
	318	ranges = <0 0x300000 0x100000>;
	319
	320	intc: interrupt-controller@0 {
	321	compatible = "oxsemi,ox810se-rps-irq";
	322	interrupt-controller;
	323	reg = <0 0x200>;
	324	#interrupt-cells = <1>;
	325	valid-mask = <0xFFFFFFFF>;
	326	clear-mask = <0>;
	327	};
	328
	329	timer0: timer@200 {
	330	compatible = "oxsemi,ox810se-rps-timer";
	331	reg = <0x200 0x40>;
	332	clocks = <&rpsclk>;
	333	interrupts = <4 5>;
	334	};
	335	};
	336	};
	337	};
	338	};