[linux-block.git] / arch / arm / boot / dts / omap4.dtsi

// SPDX-License-Identifier: GPL-2.0-only
/*
 * Copyright (C) 2011 Texas Instruments Incorporated - http://www.ti.com/
 */

#include <dt-bindings/bus/ti-sysc.h>
#include <dt-bindings/clock/omap4.h>
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/pinctrl/omap.h>
#include <dt-bindings/clock/omap4.h>

/ {
	compatible = "ti,omap4430", "ti,omap4";
	interrupt-parent = <&wakeupgen>;
	#address-cells = <1>;
	#size-cells = <1>;
	chosen { };

	aliases {
		i2c0 = &i2c1;
		i2c1 = &i2c2;
		i2c2 = &i2c3;
		i2c3 = &i2c4;
		serial0 = &uart1;
		serial1 = &uart2;
		serial2 = &uart3;
		serial3 = &uart4;
	};

	cpus {
		#address-cells = <1>;
		#size-cells = <0>;

		cpu@0 {
			compatible = "arm,cortex-a9";
			device_type = "cpu";
			next-level-cache = <&L2>;
			reg = <0x0>;

			clocks = <&dpll_mpu_ck>;
			clock-names = "cpu";

			clock-latency = <300000>; /* From omap-cpufreq driver */
		};
		cpu@1 {
			compatible = "arm,cortex-a9";
			device_type = "cpu";
			next-level-cache = <&L2>;
			reg = <0x1>;
		};
	};

	/*
	 * Note that 4430 needs cross trigger interface (CTI) supported
	 * before we can configure the interrupts. This means sampling
	 * events are not supported for pmu. Note that 4460 does not use
	 * CTI, see also 4460.dtsi.
	 */
	pmu {
		compatible = "arm,cortex-a9-pmu";
		ti,hwmods = "debugss";
	};

	gic: interrupt-controller@48241000 {
		compatible = "arm,cortex-a9-gic";
		interrupt-controller;
		#interrupt-cells = <3>;
		reg = <0x48241000 0x1000>,
		      <0x48240100 0x0100>;
		interrupt-parent = <&gic>;
	};

	L2: l2-cache-controller@48242000 {
		compatible = "arm,pl310-cache";
		reg = <0x48242000 0x1000>;
		cache-unified;
		cache-level = <2>;
	};

	local-timer@48240600 {
		compatible = "arm,cortex-a9-twd-timer";
		clocks = <&mpu_periphclk>;
		reg = <0x48240600 0x20>;
		interrupts = <GIC_PPI 13 (GIC_CPU_MASK_RAW(3) | IRQ_TYPE_EDGE_RISING)>;
		interrupt-parent = <&gic>;
	};

	wakeupgen: interrupt-controller@48281000 {
		compatible = "ti,omap4-wugen-mpu";
		interrupt-controller;
		#interrupt-cells = <3>;
		reg = <0x48281000 0x1000>;
		interrupt-parent = <&gic>;
	};

	/*
	 * The soc node represents the soc top level view. It is used for IPs
	 * that are not memory mapped in the MPU view or for the MPU itself.
	 */
	soc {
		compatible = "ti,omap-infra";
		mpu {
			compatible = "ti,omap4-mpu";
			ti,hwmods = "mpu";
			sram = <&ocmcram>;
		};

		dsp {
			compatible = "ti,omap3-c64";
			ti,hwmods = "dsp";
		};

		iva {
			compatible = "ti,ivahd";
			ti,hwmods = "iva";
		};
	};

	/*
	 * XXX: Use a flat representation of the OMAP4 interconnect.
	 * The real OMAP interconnect network is quite complex.
	 * Since it will not bring real advantage to represent that in DT for
	 * the moment, just use a fake OCP bus entry to represent the whole bus
	 * hierarchy.
	 */
	ocp {
		compatible = "ti,omap4-l3-noc", "simple-bus";
		#address-cells = <1>;
		#size-cells = <1>;
		ranges;
		ti,hwmods = "l3_main_1", "l3_main_2", "l3_main_3";
		reg = <0x44000000 0x1000>,
		      <0x44800000 0x2000>,
		      <0x45000000 0x1000>;
		interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>,
			     <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;

		l4_wkup: interconnect@4a300000 {
		};

		l4_cfg: interconnect@4a000000 {
		};

		l4_per: interconnect@48000000 {
		};

		l4_abe: interconnect@40100000 {
		};

		ocmcram: ocmcram@40304000 {
			compatible = "mmio-sram";
			reg = <0x40304000 0xa000>; /* 40k */
		};

		gpmc: gpmc@50000000 {
			compatible = "ti,omap4430-gpmc";
			reg = <0x50000000 0x1000>;
			#address-cells = <2>;
			#size-cells = <1>;
			interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
			dmas = <&sdma 4>;
			dma-names = "rxtx";
			gpmc,num-cs = <8>;
			gpmc,num-waitpins = <4>;
			ti,hwmods = "gpmc";
			ti,no-idle-on-init;
			clocks = <&l3_div_ck>;
			clock-names = "fck";
			interrupt-controller;
			#interrupt-cells = <2>;
			gpio-controller;
			#gpio-cells = <2>;
		};

		mmu_dsp: mmu@4a066000 {
			compatible = "ti,omap4-iommu";
			reg = <0x4a066000 0x100>;
			interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>;
			ti,hwmods = "mmu_dsp";
			#iommu-cells = <0>;
		};

		target-module@52000000 {
			compatible = "ti,sysc-omap4", "ti,sysc";
			ti,hwmods = "iss";
			reg = <0x52000000 0x4>,
			      <0x52000010 0x4>;
			reg-names = "rev", "sysc";
			ti,sysc-mask = <SYSC_OMAP4_SOFTRESET>;
			ti,sysc-midle = <SYSC_IDLE_FORCE>,
					<SYSC_IDLE_NO>,
					<SYSC_IDLE_SMART>,
					<SYSC_IDLE_SMART_WKUP>;
			ti,sysc-sidle = <SYSC_IDLE_FORCE>,
					<SYSC_IDLE_NO>,
					<SYSC_IDLE_SMART>,
					<SYSC_IDLE_SMART_WKUP>;
			ti,sysc-delay-us = <2>;
			clocks = <&iss_clkctrl OMAP4_ISS_CLKCTRL 0>;
			clock-names = "fck";
			#address-cells = <1>;
			#size-cells = <1>;
			ranges = <0 0x52000000 0x1000000>;

			/* No child device binding, driver in staging */
		};

		mmu_ipu: mmu@55082000 {
			compatible = "ti,omap4-iommu";
			reg = <0x55082000 0x100>;
			interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>;
			ti,hwmods = "mmu_ipu";
			#iommu-cells = <0>;
			ti,iommu-bus-err-back;
		};
		target-module@4012c000 {
			compatible = "ti,sysc-omap4", "ti,sysc";
			ti,hwmods = "slimbus1";
			reg = <0x4012c000 0x4>,
			      <0x4012c010 0x4>;
			reg-names = "rev", "sysc";
			ti,sysc-mask = <SYSC_OMAP4_SOFTRESET>;
			ti,sysc-sidle = <SYSC_IDLE_FORCE>,
					<SYSC_IDLE_NO>,
					<SYSC_IDLE_SMART>,
					<SYSC_IDLE_SMART_WKUP>;
			clocks = <&abe_clkctrl OMAP4_SLIMBUS1_CLKCTRL 0>;
			clock-names = "fck";
			#address-cells = <1>;
			#size-cells = <1>;
			ranges = <0x00000000 0x4012c000 0x1000>, /* MPU */
				 <0x4902c000 0x4902c000 0x1000>; /* L3 */

			/* No child device binding or driver in mainline */
		};

		dmm@4e000000 {
			compatible = "ti,omap4-dmm";
			reg = <0x4e000000 0x800>;
			interrupts = <0 113 0x4>;
			ti,hwmods = "dmm";
		};

		emif1: emif@4c000000 {
			compatible = "ti,emif-4d";
			reg = <0x4c000000 0x100>;
			interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>;
			ti,hwmods = "emif1";
			ti,no-idle-on-init;
			phy-type = <1>;
			hw-caps-read-idle-ctrl;
			hw-caps-ll-interface;
			hw-caps-temp-alert;
		};

		emif2: emif@4d000000 {
			compatible = "ti,emif-4d";
			reg = <0x4d000000 0x100>;
			interrupts = <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>;
			ti,hwmods = "emif2";
			ti,no-idle-on-init;
			phy-type = <1>;
			hw-caps-read-idle-ctrl;
			hw-caps-ll-interface;
			hw-caps-temp-alert;
		};

		aes1: aes@4b501000 {
			compatible = "ti,omap4-aes";
			ti,hwmods = "aes1";
			reg = <0x4b501000 0xa0>;
			interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>;
			dmas = <&sdma 111>, <&sdma 110>;
			dma-names = "tx", "rx";
		};

		aes2: aes@4b701000 {
			compatible = "ti,omap4-aes";
			ti,hwmods = "aes2";
			reg = <0x4b701000 0xa0>;
			interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>;
			dmas = <&sdma 114>, <&sdma 113>;
			dma-names = "tx", "rx";
		};

		des: des@480a5000 {
			compatible = "ti,omap4-des";
			ti,hwmods = "des";
			reg = <0x480a5000 0xa0>;
			interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>;
			dmas = <&sdma 117>, <&sdma 116>;
			dma-names = "tx", "rx";
		};

		sham: sham@4b100000 {
			compatible = "ti,omap4-sham";
			ti,hwmods = "sham";
			reg = <0x4b100000 0x300>;
			interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>;
			dmas = <&sdma 119>;
			dma-names = "rx";
		};

		abb_mpu: regulator-abb-mpu {
			compatible = "ti,abb-v2";
			regulator-name = "abb_mpu";
			#address-cells = <0>;
			#size-cells = <0>;
			ti,tranxdone-status-mask = <0x80>;
			clocks = <&sys_clkin_ck>;
			ti,settling-time = <50>;
			ti,clock-cycles = <16>;

			status = "disabled";
		};

		abb_iva: regulator-abb-iva {
			compatible = "ti,abb-v2";
			regulator-name = "abb_iva";
			#address-cells = <0>;
			#size-cells = <0>;
			ti,tranxdone-status-mask = <0x80000000>;
			clocks = <&sys_clkin_ck>;
			ti,settling-time = <50>;
			ti,clock-cycles = <16>;

			status = "disabled";
		};

		target-module@56000000 {
			compatible = "ti,sysc-omap4", "ti,sysc";
			ti,hwmods = "gpu";
			reg = <0x5601fc00 0x4>,
			      <0x5601fc10 0x4>;
			reg-names = "rev", "sysc";
			ti,sysc-midle = <SYSC_IDLE_FORCE>,
					<SYSC_IDLE_NO>,
					<SYSC_IDLE_SMART>,
					<SYSC_IDLE_SMART_WKUP>;
			ti,sysc-sidle = <SYSC_IDLE_FORCE>,
					<SYSC_IDLE_NO>,
					<SYSC_IDLE_SMART>,
					<SYSC_IDLE_SMART_WKUP>;
			clocks = <&l3_gfx_clkctrl OMAP4_GPU_CLKCTRL 0>;
			clock-names = "fck";
			#address-cells = <1>;
			#size-cells = <1>;
			ranges = <0 0x56000000 0x2000000>;

			/*
			 * Closed source PowerVR driver, no child device
			 * binding or driver in mainline
			 */
		};

		dss: dss@58000000 {
			compatible = "ti,omap4-dss";
			reg = <0x58000000 0x80>;
			status = "disabled";
			ti,hwmods = "dss_core";
			clocks = <&l3_dss_clkctrl OMAP4_DSS_CORE_CLKCTRL 8>;
			clock-names = "fck";
			#address-cells = <1>;
			#size-cells = <1>;
			ranges;

			dispc@58001000 {
				compatible = "ti,omap4-dispc";
				reg = <0x58001000 0x1000>;
				interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
				ti,hwmods = "dss_dispc";
				clocks = <&l3_dss_clkctrl OMAP4_DSS_CORE_CLKCTRL 8>;
				clock-names = "fck";
			};

			rfbi: encoder@58002000  {
				compatible = "ti,omap4-rfbi";
				reg = <0x58002000 0x1000>;
				status = "disabled";
				ti,hwmods = "dss_rfbi";
				clocks = <&l3_dss_clkctrl OMAP4_DSS_CORE_CLKCTRL 8>, <&l3_div_ck>;
				clock-names = "fck", "ick";
			};

			venc: encoder@58003000 {
				compatible = "ti,omap4-venc";
				reg = <0x58003000 0x1000>;
				status = "disabled";
				ti,hwmods = "dss_venc";
				clocks = <&l3_dss_clkctrl OMAP4_DSS_CORE_CLKCTRL 11>;
				clock-names = "fck";
			};

			dsi1: encoder@58004000 {
				compatible = "ti,omap4-dsi";
				reg = <0x58004000 0x200>,
				      <0x58004200 0x40>,
				      <0x58004300 0x20>;
				reg-names = "proto", "phy", "pll";
				interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>;
				status = "disabled";
				ti,hwmods = "dss_dsi1";
				clocks = <&l3_dss_clkctrl OMAP4_DSS_CORE_CLKCTRL 8>,
					 <&l3_dss_clkctrl OMAP4_DSS_CORE_CLKCTRL 10>;
				clock-names = "fck", "sys_clk";
			};

			dsi2: encoder@58005000 {
				compatible = "ti,omap4-dsi";
				reg = <0x58005000 0x200>,
				      <0x58005200 0x40>,
				      <0x58005300 0x20>;
				reg-names = "proto", "phy", "pll";
				interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>;
				status = "disabled";
				ti,hwmods = "dss_dsi2";
				clocks = <&l3_dss_clkctrl OMAP4_DSS_CORE_CLKCTRL 8>,
					 <&l3_dss_clkctrl OMAP4_DSS_CORE_CLKCTRL 10>;
				clock-names = "fck", "sys_clk";
			};

			hdmi: encoder@58006000 {
				compatible = "ti,omap4-hdmi";
				reg = <0x58006000 0x200>,
				      <0x58006200 0x100>,
				      <0x58006300 0x100>,
				      <0x58006400 0x1000>;
				reg-names = "wp", "pll", "phy", "core";
				interrupts = <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>;
				status = "disabled";
				ti,hwmods = "dss_hdmi";
				clocks = <&l3_dss_clkctrl OMAP4_DSS_CORE_CLKCTRL 9>,
					 <&l3_dss_clkctrl OMAP4_DSS_CORE_CLKCTRL 10>;
				clock-names = "fck", "sys_clk";
				dmas = <&sdma 76>;
				dma-names = "audio_tx";
			};
		};
	};
};

#include "omap4-l4.dtsi"
#include "omap4-l4-abe.dtsi"
#include "omap44xx-clocks.dtsi"
Commit	Line	Data
d2912cb1	1	// SPDX-License-Identifier: GPL-2.0-only
d9fda07a BC	2	/*
d9fda07a BC	3	* Copyright (C) 2011 Texas Instruments Incorporated - http://www.ti.com/
d9fda07a BC	4	*/
d9fda07a BC	5
e14d7e53 TL	6	#include <dt-bindings/bus/ti-sysc.h>
e14d7e53 TL	7	#include <dt-bindings/clock/omap4.h>
6d624eab	8	#include <dt-bindings/gpio/gpio.h>
8fea7d5a	9	#include <dt-bindings/interrupt-controller/arm-gic.h>
bcd3cca7	10	#include <dt-bindings/pinctrl/omap.h>
a5c82a09	11	#include <dt-bindings/clock/omap4.h>
d9fda07a	12
d9fda07a BC	13	/ {
d9fda07a BC	14	compatible = "ti,omap4430", "ti,omap4";
7136d457	15	interrupt-parent = <&wakeupgen>;
da6269e7 JMC	16	#address-cells = <1>;
da6269e7 JMC	17	#size-cells = <1>;
6c565d1a	18	chosen { };
d9fda07a BC	19
d9fda07a BC	20	aliases {
20b80942 NM	21	i2c0 = &i2c1;
	22	i2c1 = &i2c2;
	23	i2c2 = &i2c3;
	24	i2c3 = &i2c4;
cf3c79de RN	25	serial0 = &uart1;
	26	serial1 = &uart2;
	27	serial2 = &uart3;
	28	serial3 = &uart4;
d9fda07a BC	29	};
d9fda07a BC	30
476b679a	31	cpus {
eeb25fd5 LP	32	#address-cells = <1>;
	33	#size-cells = <0>;
	34
476b679a BC	35	cpu@0 {
476b679a BC	36	compatible = "arm,cortex-a9";
eeb25fd5	37	device_type = "cpu";
926fd45b	38	next-level-cache = <&L2>;
eeb25fd5	39	reg = <0x0>;
8d766fa2 NM	40
	41	clocks = <&dpll_mpu_ck>;
	42	clock-names = "cpu";
	43
	44	clock-latency = <300000>; /* From omap-cpufreq driver */
476b679a BC	45	};
	46	cpu@1 {
	47	compatible = "arm,cortex-a9";
eeb25fd5	48	device_type = "cpu";
926fd45b	49	next-level-cache = <&L2>;
eeb25fd5	50	reg = <0x1>;
476b679a BC	51	};
	52	};
	53
b0142a10 TL	54	/*
	55	* Note that 4430 needs cross trigger interface (CTI) supported
	56	* before we can configure the interrupts. This means sampling
	57	* events are not supported for pmu. Note that 4460 does not use
	58	* CTI, see also 4460.dtsi.
	59	*/
	60	pmu {
	61	compatible = "arm,cortex-a9-pmu";
	62	ti,hwmods = "debugss";
	63	};
	64
5635121e BC	65	gic: interrupt-controller@48241000 {
	66	compatible = "arm,cortex-a9-gic";
	67	interrupt-controller;
	68	#interrupt-cells = <3>;
	69	reg = <0x48241000 0x1000>,
	70	<0x48240100 0x0100>;
7136d457	71	interrupt-parent = <&gic>;
5635121e BC	72	};
5635121e BC	73
926fd45b SS	74	L2: l2-cache-controller@48242000 {
	75	compatible = "arm,pl310-cache";
	76	reg = <0x48242000 0x1000>;
	77	cache-unified;
	78	cache-level = <2>;
	79	};
	80
75d71d46	81	local-timer@48240600 {
eed0de27	82	compatible = "arm,cortex-a9-twd-timer";
23c47378	83	clocks = <&mpu_periphclk>;
eed0de27	84	reg = <0x48240600 0x20>;
6b472574	85	interrupts = <GIC_PPI 13 (GIC_CPU_MASK_RAW(3) \| IRQ_TYPE_EDGE_RISING)>;
7136d457 MZ	86	interrupt-parent = <&gic>;
	87	};
	88
	89	wakeupgen: interrupt-controller@48281000 {
	90	compatible = "ti,omap4-wugen-mpu";
	91	interrupt-controller;
	92	#interrupt-cells = <3>;
	93	reg = <0x48281000 0x1000>;
	94	interrupt-parent = <&gic>;
eed0de27 SS	95	};
eed0de27 SS	96
d9fda07a	97	/*
5c5be9db	98	* The soc node represents the soc top level view. It is used for IPs
d9fda07a BC	99	* that are not memory mapped in the MPU view or for the MPU itself.
	100	*/
	101	soc {
	102	compatible = "ti,omap-infra";
476b679a BC	103	mpu {
	104	compatible = "ti,omap4-mpu";
	105	ti,hwmods = "mpu";
1306c08a	106	sram = <&ocmcram>;
476b679a BC	107	};
	108
	109	dsp {
	110	compatible = "ti,omap3-c64";
	111	ti,hwmods = "dsp";
	112	};
	113
	114	iva {
	115	compatible = "ti,ivahd";
	116	ti,hwmods = "iva";
	117	};
d9fda07a BC	118	};
	119
	120	/*
	121	* XXX: Use a flat representation of the OMAP4 interconnect.
	122	* The real OMAP interconnect network is quite complex.
b7ab524b	123	* Since it will not bring real advantage to represent that in DT for
d9fda07a BC	124	* the moment, just use a fake OCP bus entry to represent the whole bus
	125	* hierarchy.
	126	*/
	127	ocp {
ad8dfac6	128	compatible = "ti,omap4-l3-noc", "simple-bus";
d9fda07a BC	129	#address-cells = <1>;
	130	#size-cells = <1>;
	131	ranges;
ad8dfac6	132	ti,hwmods = "l3_main_1", "l3_main_2", "l3_main_3";
20a60eaa SS	133	reg = <0x44000000 0x1000>,
	134	<0x44800000 0x2000>,
	135	<0x45000000 0x1000>;
8fea7d5a FV	136	interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>,
8fea7d5a FV	137	<GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
d9fda07a	138
84badc5e TL	139	l4_wkup: interconnect@4a300000 {
84badc5e TL	140	};
1d6a332a	141
84badc5e TL	142	l4_cfg: interconnect@4a000000 {
84badc5e TL	143	};
1d6a332a	144
84badc5e	145	l4_per: interconnect@48000000 {
cd042fe5 B	146	};
cd042fe5 B	147
5b597531 TL	148	l4_abe: interconnect@40100000 {
	149	};
	150
8b9a2810 RN	151	ocmcram: ocmcram@40304000 {
	152	compatible = "mmio-sram";
	153	reg = <0x40304000 0xa000>; /* 40k */
	154	};
	155
1c7dbb55 JH	156	gpmc: gpmc@50000000 {
	157	compatible = "ti,omap4430-gpmc";
	158	reg = <0x50000000 0x1000>;
	159	#address-cells = <2>;
	160	#size-cells = <1>;
8fea7d5a	161	interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
201c7e33 FCJ	162	dmas = <&sdma 4>;
201c7e33 FCJ	163	dma-names = "rxtx";
1c7dbb55 JH	164	gpmc,num-cs = <8>;
	165	gpmc,num-waitpins = <4>;
	166	ti,hwmods = "gpmc";
f12ecbe2	167	ti,no-idle-on-init;
7b8b6af1 FV	168	clocks = <&l3_div_ck>;
7b8b6af1 FV	169	clock-names = "fck";
8c75b766 RQ	170	interrupt-controller;
	171	#interrupt-cells = <2>;
	172	gpio-controller;
	173	#gpio-cells = <2>;
1c7dbb55 JH	174	};
1c7dbb55 JH	175
21bd85a1 FV	176	mmu_dsp: mmu@4a066000 {
	177	compatible = "ti,omap4-iommu";
	178	reg = <0x4a066000 0x100>;
	179	interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>;
	180	ti,hwmods = "mmu_dsp";
22e3bcc6	181	#iommu-cells = <0>;
21bd85a1 FV	182	};
21bd85a1 FV	183
d23a163e	184	target-module@52000000 {
feffce1d	185	compatible = "ti,sysc-omap4", "ti,sysc";
d23a163e TL	186	ti,hwmods = "iss";
	187	reg = <0x52000000 0x4>,
	188	<0x52000010 0x4>;
	189	reg-names = "rev", "sysc";
e14d7e53 TL	190	ti,sysc-mask = <SYSC_OMAP4_SOFTRESET>;
	191	ti,sysc-midle = <SYSC_IDLE_FORCE>,
	192	<SYSC_IDLE_NO>,
	193	<SYSC_IDLE_SMART>,
	194	<SYSC_IDLE_SMART_WKUP>;
	195	ti,sysc-sidle = <SYSC_IDLE_FORCE>,
	196	<SYSC_IDLE_NO>,
	197	<SYSC_IDLE_SMART>,
	198	<SYSC_IDLE_SMART_WKUP>;
	199	ti,sysc-delay-us = <2>;
	200	clocks = <&iss_clkctrl OMAP4_ISS_CLKCTRL 0>;
	201	clock-names = "fck";
d23a163e TL	202	#address-cells = <1>;
	203	#size-cells = <1>;
	204	ranges = <0 0x52000000 0x1000000>;
	205
	206	/* No child device binding, driver in staging */
	207	};
	208
21bd85a1 FV	209	mmu_ipu: mmu@55082000 {
	210	compatible = "ti,omap4-iommu";
	211	reg = <0x55082000 0x100>;
	212	interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>;
	213	ti,hwmods = "mmu_ipu";
22e3bcc6	214	#iommu-cells = <0>;
21bd85a1 FV	215	ti,iommu-bus-err-back;
21bd85a1 FV	216	};
d23a163e	217	target-module@4012c000 {
feffce1d	218	compatible = "ti,sysc-omap4", "ti,sysc";
d23a163e TL	219	ti,hwmods = "slimbus1";
	220	reg = <0x4012c000 0x4>,
	221	<0x4012c010 0x4>;
	222	reg-names = "rev", "sysc";
e14d7e53 TL	223	ti,sysc-mask = <SYSC_OMAP4_SOFTRESET>;
	224	ti,sysc-sidle = <SYSC_IDLE_FORCE>,
	225	<SYSC_IDLE_NO>,
	226	<SYSC_IDLE_SMART>,
	227	<SYSC_IDLE_SMART_WKUP>;
	228	clocks = <&abe_clkctrl OMAP4_SLIMBUS1_CLKCTRL 0>;
	229	clock-names = "fck";
d23a163e TL	230	#address-cells = <1>;
	231	#size-cells = <1>;
	232	ranges = <0x00000000 0x4012c000 0x1000>, /* MPU */
	233	<0x4902c000 0x4902c000 0x1000>; /* L3 */
	234
	235	/* No child device binding or driver in mainline */
	236	};
	237
1a5fe3ca AT	238	dmm@4e000000 {
	239	compatible = "ti,omap4-dmm";
	240	reg = <0x4e000000 0x800>;
	241	interrupts = <0 113 0x4>;
	242	ti,hwmods = "dmm";
	243	};
	244
11c27069 A	245	emif1: emif@4c000000 {
11c27069 A	246	compatible = "ti,emif-4d";
48420dbc	247	reg = <0x4c000000 0x100>;
8fea7d5a	248	interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>;
11c27069	249	ti,hwmods = "emif1";
f12ecbe2	250	ti,no-idle-on-init;
11c27069 A	251	phy-type = <1>;
	252	hw-caps-read-idle-ctrl;
	253	hw-caps-ll-interface;
	254	hw-caps-temp-alert;
	255	};
	256
	257	emif2: emif@4d000000 {
	258	compatible = "ti,emif-4d";
48420dbc	259	reg = <0x4d000000 0x100>;
8fea7d5a	260	interrupts = <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>;
11c27069	261	ti,hwmods = "emif2";
f12ecbe2	262	ti,no-idle-on-init;
11c27069 A	263	phy-type = <1>;
	264	hw-caps-read-idle-ctrl;
	265	hw-caps-ll-interface;
	266	hw-caps-temp-alert;
	267	};
8f446a7a	268
25e6cfc8	269	aes1: aes@4b501000 {
dd6317df	270	compatible = "ti,omap4-aes";
25e6cfc8	271	ti,hwmods = "aes1";
dd6317df JF	272	reg = <0x4b501000 0xa0>;
	273	interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>;
	274	dmas = <&sdma 111>, <&sdma 110>;
	275	dma-names = "tx", "rx";
	276	};
806e9431	277
c6faccf2 TK	278	aes2: aes@4b701000 {
	279	compatible = "ti,omap4-aes";
	280	ti,hwmods = "aes2";
	281	reg = <0x4b701000 0xa0>;
	282	interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>;
	283	dmas = <&sdma 114>, <&sdma 113>;
	284	dma-names = "tx", "rx";
	285	};
	286
806e9431 JF	287	des: des@480a5000 {
	288	compatible = "ti,omap4-des";
	289	ti,hwmods = "des";
	290	reg = <0x480a5000 0xa0>;
	291	interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>;
	292	dmas = <&sdma 117>, <&sdma 116>;
	293	dma-names = "tx", "rx";
	294	};
e12c7737	295
45f1d5e3 TK	296	sham: sham@4b100000 {
	297	compatible = "ti,omap4-sham";
	298	ti,hwmods = "sham";
	299	reg = <0x4b100000 0x300>;
	300	interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>;
	301	dmas = <&sdma 119>;
	302	dma-names = "rx";
	303	};
	304
e12c7737 AT	305	abb_mpu: regulator-abb-mpu {
	306	compatible = "ti,abb-v2";
	307	regulator-name = "abb_mpu";
	308	#address-cells = <0>;
	309	#size-cells = <0>;
	310	ti,tranxdone-status-mask = <0x80>;
	311	clocks = <&sys_clkin_ck>;
	312	ti,settling-time = <50>;
	313	ti,clock-cycles = <16>;
	314
	315	status = "disabled";
	316	};
	317
	318	abb_iva: regulator-abb-iva {
	319	compatible = "ti,abb-v2";
	320	regulator-name = "abb_iva";
	321	#address-cells = <0>;
	322	#size-cells = <0>;
	323	ti,tranxdone-status-mask = <0x80000000>;
	324	clocks = <&sys_clkin_ck>;
	325	ti,settling-time = <50>;
	326	ti,clock-cycles = <16>;
	327
	328	status = "disabled";
	329	};
cfe86fcf	330
d23a163e	331	target-module@56000000 {
feffce1d	332	compatible = "ti,sysc-omap4", "ti,sysc";
d23a163e TL	333	ti,hwmods = "gpu";
	334	reg = <0x5601fc00 0x4>,
	335	<0x5601fc10 0x4>;
	336	reg-names = "rev", "sysc";
e14d7e53 TL	337	ti,sysc-midle = <SYSC_IDLE_FORCE>,
	338	<SYSC_IDLE_NO>,
	339	<SYSC_IDLE_SMART>,
	340	<SYSC_IDLE_SMART_WKUP>;
	341	ti,sysc-sidle = <SYSC_IDLE_FORCE>,
	342	<SYSC_IDLE_NO>,
	343	<SYSC_IDLE_SMART>,
	344	<SYSC_IDLE_SMART_WKUP>;
	345	clocks = <&l3_gfx_clkctrl OMAP4_GPU_CLKCTRL 0>;
	346	clock-names = "fck";
d23a163e TL	347	#address-cells = <1>;
	348	#size-cells = <1>;
	349	ranges = <0 0x56000000 0x2000000>;
	350
	351	/*
	352	* Closed source PowerVR driver, no child device
	353	* binding or driver in mainline
	354	*/
	355	};
	356
cfe86fcf TV	357	dss: dss@58000000 {
	358	compatible = "ti,omap4-dss";
	359	reg = <0x58000000 0x80>;
	360	status = "disabled";
	361	ti,hwmods = "dss_core";
a5c82a09	362	clocks = <&l3_dss_clkctrl OMAP4_DSS_CORE_CLKCTRL 8>;
cfe86fcf TV	363	clock-names = "fck";
	364	#address-cells = <1>;
	365	#size-cells = <1>;
	366	ranges;
	367
	368	dispc@58001000 {
	369	compatible = "ti,omap4-dispc";
	370	reg = <0x58001000 0x1000>;
	371	interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
	372	ti,hwmods = "dss_dispc";
a5c82a09	373	clocks = <&l3_dss_clkctrl OMAP4_DSS_CORE_CLKCTRL 8>;
cfe86fcf TV	374	clock-names = "fck";
	375	};
	376
	377	rfbi: encoder@58002000 {
	378	compatible = "ti,omap4-rfbi";
	379	reg = <0x58002000 0x1000>;
	380	status = "disabled";
	381	ti,hwmods = "dss_rfbi";
a5c82a09	382	clocks = <&l3_dss_clkctrl OMAP4_DSS_CORE_CLKCTRL 8>, <&l3_div_ck>;
cfe86fcf TV	383	clock-names = "fck", "ick";
	384	};
	385
	386	venc: encoder@58003000 {
	387	compatible = "ti,omap4-venc";
	388	reg = <0x58003000 0x1000>;
	389	status = "disabled";
	390	ti,hwmods = "dss_venc";
a5c82a09	391	clocks = <&l3_dss_clkctrl OMAP4_DSS_CORE_CLKCTRL 11>;
cfe86fcf TV	392	clock-names = "fck";
	393	};
	394
	395	dsi1: encoder@58004000 {
	396	compatible = "ti,omap4-dsi";
	397	reg = <0x58004000 0x200>,
	398	<0x58004200 0x40>,
	399	<0x58004300 0x20>;
	400	reg-names = "proto", "phy", "pll";
	401	interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>;
	402	status = "disabled";
	403	ti,hwmods = "dss_dsi1";
a5c82a09 TK	404	clocks = <&l3_dss_clkctrl OMAP4_DSS_CORE_CLKCTRL 8>,
a5c82a09 TK	405	<&l3_dss_clkctrl OMAP4_DSS_CORE_CLKCTRL 10>;
cfe86fcf TV	406	clock-names = "fck", "sys_clk";
	407	};
	408
	409	dsi2: encoder@58005000 {
	410	compatible = "ti,omap4-dsi";
	411	reg = <0x58005000 0x200>,
	412	<0x58005200 0x40>,
	413	<0x58005300 0x20>;
	414	reg-names = "proto", "phy", "pll";
	415	interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>;
	416	status = "disabled";
	417	ti,hwmods = "dss_dsi2";
a5c82a09 TK	418	clocks = <&l3_dss_clkctrl OMAP4_DSS_CORE_CLKCTRL 8>,
a5c82a09 TK	419	<&l3_dss_clkctrl OMAP4_DSS_CORE_CLKCTRL 10>;
cfe86fcf TV	420	clock-names = "fck", "sys_clk";
	421	};
	422
	423	hdmi: encoder@58006000 {
	424	compatible = "ti,omap4-hdmi";
	425	reg = <0x58006000 0x200>,
	426	<0x58006200 0x100>,
	427	<0x58006300 0x100>,
	428	<0x58006400 0x1000>;
	429	reg-names = "wp", "pll", "phy", "core";
	430	interrupts = <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>;
	431	status = "disabled";
	432	ti,hwmods = "dss_hdmi";
a5c82a09 TK	433	clocks = <&l3_dss_clkctrl OMAP4_DSS_CORE_CLKCTRL 9>,
a5c82a09 TK	434	<&l3_dss_clkctrl OMAP4_DSS_CORE_CLKCTRL 10>;
cfe86fcf	435	clock-names = "fck", "sys_clk";
53855b30 JS	436	dmas = <&sdma 76>;
53855b30 JS	437	dma-names = "audio_tx";
cfe86fcf TV	438	};
cfe86fcf TV	439	};
d9fda07a BC	440	};
d9fda07a BC	441	};
2488ff6c	442
84badc5e	443	#include "omap4-l4.dtsi"
5b597531	444	#include "omap4-l4-abe.dtsi"
a5c82a09	445	#include "omap44xx-clocks.dtsi"