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f0e15e2b VH |
1 | /* |
2 | * Copyright (C) 2011 Texas Instruments Incorporated - http://www.ti.com/ | |
3 | * | |
4 | * This program is free software; you can redistribute it and/or modify | |
5 | * it under the terms of the GNU General Public License version 2 as | |
6 | * published by the Free Software Foundation. | |
7 | */ | |
8 | /dts-v1/; | |
9 | ||
98ef7957 | 10 | #include "omap34xx.dtsi" |
465ce68b | 11 | #include "omap3-evm-common.dtsi" |
62fe1d33 | 12 | #include "omap3-evm-processor-common.dtsi" |
f0e15e2b VH |
13 | |
14 | / { | |
465ce68b | 15 | model = "TI OMAP35XX EVM (TMDSEVM3530)"; |
62fe1d33 DW |
16 | compatible = "ti,omap3-evm", "ti,omap3430", "ti,omap3"; |
17 | }; | |
18 | ||
19 | &omap3_pmx_core2 { | |
20 | pinctrl-names = "default"; | |
21 | pinctrl-0 = <&hsusb2_2_pins>; | |
22 | ||
23 | ehci_phy_pins: pinmux_ehci_phy_pins { | |
24 | pinctrl-single,pins = < | |
25 | ||
26 | /* EHCI PHY reset GPIO etk_d7.gpio_21 */ | |
27 | OMAP3430_CORE2_IOPAD(0x25ea, PIN_OUTPUT | MUX_MODE4) | |
28 | ||
29 | /* EHCI VBUS etk_d8.gpio_22 */ | |
30 | OMAP3430_CORE2_IOPAD(0x25ec, PIN_OUTPUT | MUX_MODE4) | |
31 | >; | |
32 | }; | |
33 | ||
34 | /* Used by OHCI and EHCI. OHCI won't work without external phy */ | |
35 | hsusb2_2_pins: pinmux_hsusb2_2_pins { | |
36 | pinctrl-single,pins = < | |
37 | ||
38 | /* etk_d10.hsusb2_clk */ | |
39 | OMAP3430_CORE2_IOPAD(0x25f0, PIN_OUTPUT | MUX_MODE3) | |
40 | ||
41 | /* etk_d11.hsusb2_stp */ | |
42 | OMAP3430_CORE2_IOPAD(0x25f2, PIN_OUTPUT | MUX_MODE3) | |
43 | ||
44 | /* etk_d12.hsusb2_dir */ | |
45 | OMAP3430_CORE2_IOPAD(0x25f4, PIN_INPUT_PULLDOWN | MUX_MODE3) | |
46 | ||
47 | /* etk_d13.hsusb2_nxt */ | |
48 | OMAP3430_CORE2_IOPAD(0x25f6, PIN_INPUT_PULLDOWN | MUX_MODE3) | |
49 | ||
50 | /* etk_d14.hsusb2_data0 */ | |
51 | OMAP3430_CORE2_IOPAD(0x25f8, PIN_INPUT_PULLDOWN | MUX_MODE3) | |
52 | ||
53 | /* etk_d15.hsusb2_data1 */ | |
54 | OMAP3430_CORE2_IOPAD(0x25fa, PIN_INPUT_PULLDOWN | MUX_MODE3) | |
55 | >; | |
56 | }; | |
57 | }; | |
58 | ||
59 | &gpmc { | |
60 | nand@0,0 { | |
61 | compatible = "ti,omap2-nand"; | |
62 | reg = <0 0 4>; /* CS0, offset 0, IO size 4 */ | |
63 | interrupt-parent = <&gpmc>; | |
64 | interrupts = <0 IRQ_TYPE_NONE>, /* fifoevent */ | |
65 | <1 IRQ_TYPE_NONE>; /* termcount */ | |
66 | linux,mtd-name= "micron,mt29f2g16abdhc"; | |
67 | nand-bus-width = <16>; | |
68 | gpmc,device-width = <2>; | |
69 | ti,nand-ecc-opt = "bch8"; | |
70 | ||
71 | gpmc,sync-clk-ps = <0>; | |
72 | gpmc,cs-on-ns = <0>; | |
73 | gpmc,cs-rd-off-ns = <44>; | |
74 | gpmc,cs-wr-off-ns = <44>; | |
75 | gpmc,adv-on-ns = <6>; | |
76 | gpmc,adv-rd-off-ns = <34>; | |
77 | gpmc,adv-wr-off-ns = <44>; | |
78 | gpmc,we-off-ns = <40>; | |
79 | gpmc,oe-off-ns = <54>; | |
80 | gpmc,access-ns = <64>; | |
81 | gpmc,rd-cycle-ns = <82>; | |
82 | gpmc,wr-cycle-ns = <82>; | |
83 | gpmc,wr-access-ns = <40>; | |
84 | gpmc,wr-data-mux-bus-ns = <0>; | |
f0e15e2b | 85 | |
62fe1d33 DW |
86 | #address-cells = <1>; |
87 | #size-cells = <1>; | |
f0e15e2b | 88 | }; |
ad871c10 | 89 | }; |