projects / linux-2.6-block.git / blame
| Commit | Line | Data |
|---|---|---|
| 3f187f82 PU |
1 | /* |
| 2 | * Device Tree Source for OMAP2420 SoC | |
| 3 | * | |
| 4 | * Copyright (C) 2012 Texas Instruments Incorporated - http://www.ti.com/ | |
| 5 | * | |
| 6 | * This file is licensed under the terms of the GNU General Public License | |
| 7 | * version 2. This program is licensed "as is" without any warranty of any | |
| 8 | * kind, whether express or implied. | |
| 9 | */ | |
| 10 | ||
| 98ef7957 | 11 | #include "omap2.dtsi" |
| 3f187f82 PU |
12 | |
| 13 | / { | |
| 14 | compatible = "ti,omap2420", "ti,omap2"; | |
| 15 | ||
| 16 | ocp { | |
| bc797691 TK |
17 | prcm: prcm@48008000 { |
| 18 | compatible = "ti,omap2-prcm"; | |
| 19 | reg = <0x48008000 0x1000>; | |
| 20 | ||
| 21 | prcm_clocks: clocks { | |
| 22 | #address-cells = <1>; | |
| 23 | #size-cells = <0>; | |
| 24 | }; | |
| 25 | ||
| 26 | prcm_clockdomains: clockdomains { | |
| 27 | }; | |
| 28 | }; | |
| 29 | ||
| 30 | scrm: scrm@48000000 { | |
| 31 | compatible = "ti,omap2-scrm"; | |
| 32 | reg = <0x48000000 0x1000>; | |
| 33 | ||
| 34 | scrm_clocks: clocks { | |
| 35 | #address-cells = <1>; | |
| 36 | #size-cells = <0>; | |
| 37 | }; | |
| 38 | ||
| 39 | scrm_clockdomains: clockdomains { | |
| 40 | }; | |
| 41 | }; | |
| 42 | ||
| 510c0ffd JH |
43 | counter32k: counter@48004000 { |
| 44 | compatible = "ti,omap-counter32k"; | |
| 45 | reg = <0x48004000 0x20>; | |
| 46 | ti,hwmods = "counter_32k"; | |
| 47 | }; | |
| 48 | ||
| 679e3310 TL |
49 | omap2420_pmx: pinmux@48000030 { |
| 50 | compatible = "ti,omap2420-padconf", "pinctrl-single"; | |
| 51 | reg = <0x48000030 0x0113>; | |
| 52 | #address-cells = <1>; | |
| 53 | #size-cells = <0>; | |
| 54 | pinctrl-single,register-width = <8>; | |
| 55 | pinctrl-single,function-mask = <0x3f>; | |
| 56 | }; | |
| 57 | ||
| 423182e3 JH |
58 | gpio1: gpio@48018000 { |
| 59 | compatible = "ti,omap2-gpio"; | |
| 60 | reg = <0x48018000 0x200>; | |
| 61 | interrupts = <29>; | |
| 62 | ti,hwmods = "gpio1"; | |
| e4b9b9f3 | 63 | ti,gpio-always-on; |
| 423182e3 JH |
64 | #gpio-cells = <2>; |
| 65 | gpio-controller; | |
| 66 | #interrupt-cells = <2>; | |
| 67 | interrupt-controller; | |
| 68 | }; | |
| 69 | ||
| 70 | gpio2: gpio@4801a000 { | |
| 71 | compatible = "ti,omap2-gpio"; | |
| 72 | reg = <0x4801a000 0x200>; | |
| 73 | interrupts = <30>; | |
| 74 | ti,hwmods = "gpio2"; | |
| e4b9b9f3 | 75 | ti,gpio-always-on; |
| 423182e3 JH |
76 | #gpio-cells = <2>; |
| 77 | gpio-controller; | |
| 78 | #interrupt-cells = <2>; | |
| 79 | interrupt-controller; | |
| 80 | }; | |
| 81 | ||
| 82 | gpio3: gpio@4801c000 { | |
| 83 | compatible = "ti,omap2-gpio"; | |
| 84 | reg = <0x4801c000 0x200>; | |
| 85 | interrupts = <31>; | |
| 86 | ti,hwmods = "gpio3"; | |
| e4b9b9f3 | 87 | ti,gpio-always-on; |
| 423182e3 JH |
88 | #gpio-cells = <2>; |
| 89 | gpio-controller; | |
| 90 | #interrupt-cells = <2>; | |
| 91 | interrupt-controller; | |
| 92 | }; | |
| 93 | ||
| 94 | gpio4: gpio@4801e000 { | |
| 95 | compatible = "ti,omap2-gpio"; | |
| 96 | reg = <0x4801e000 0x200>; | |
| 97 | interrupts = <32>; | |
| 98 | ti,hwmods = "gpio4"; | |
| e4b9b9f3 | 99 | ti,gpio-always-on; |
| 423182e3 JH |
100 | #gpio-cells = <2>; |
| 101 | gpio-controller; | |
| 102 | #interrupt-cells = <2>; | |
| 103 | interrupt-controller; | |
| 104 | }; | |
| 105 | ||
| 1c7dbb55 JH |
106 | gpmc: gpmc@6800a000 { |
| 107 | compatible = "ti,omap2420-gpmc"; | |
| 108 | reg = <0x6800a000 0x1000>; | |
| 109 | #address-cells = <2>; | |
| 110 | #size-cells = <1>; | |
| 111 | interrupts = <20>; | |
| 112 | gpmc,num-cs = <8>; | |
| 113 | gpmc,num-waitpins = <4>; | |
| 114 | ti,hwmods = "gpmc"; | |
| 115 | }; | |
| 116 | ||
| 3f187f82 PU |
117 | mcbsp1: mcbsp@48074000 { |
| 118 | compatible = "ti,omap2420-mcbsp"; | |
| 119 | reg = <0x48074000 0xff>; | |
| 120 | reg-names = "mpu"; | |
| 121 | interrupts = <59>, /* TX interrupt */ | |
| 122 | <60>; /* RX interrupt */ | |
| 123 | interrupt-names = "tx", "rx"; | |
| 3f187f82 | 124 | ti,hwmods = "mcbsp1"; |
| 4e4ead73 SG |
125 | dmas = <&sdma 31>, |
| 126 | <&sdma 32>; | |
| 127 | dma-names = "tx", "rx"; | |
| faa00deb | 128 | status = "disabled"; |
| 3f187f82 PU |
129 | }; |
| 130 | ||
| 131 | mcbsp2: mcbsp@48076000 { | |
| 132 | compatible = "ti,omap2420-mcbsp"; | |
| 133 | reg = <0x48076000 0xff>; | |
| 134 | reg-names = "mpu"; | |
| 135 | interrupts = <62>, /* TX interrupt */ | |
| 136 | <63>; /* RX interrupt */ | |
| 137 | interrupt-names = "tx", "rx"; | |
| 3f187f82 | 138 | ti,hwmods = "mcbsp2"; |
| 4e4ead73 SG |
139 | dmas = <&sdma 33>, |
| 140 | <&sdma 34>; | |
| 141 | dma-names = "tx", "rx"; | |
| faa00deb | 142 | status = "disabled"; |
| 3f187f82 | 143 | }; |
| fab8ad0b | 144 | |
| 467f4bd2 TL |
145 | msdi1: mmc@4809c000 { |
| 146 | compatible = "ti,omap2420-mmc"; | |
| 147 | ti,hwmods = "msdi1"; | |
| 148 | reg = <0x4809c000 0x80>; | |
| 149 | interrupts = <83>; | |
| 150 | dmas = <&sdma 61 &sdma 62>; | |
| 151 | dma-names = "tx", "rx"; | |
| 152 | }; | |
| 153 | ||
| 4fe5bd5d SA |
154 | mailbox: mailbox@48094000 { |
| 155 | compatible = "ti,omap2-mailbox"; | |
| 156 | reg = <0x48094000 0x200>; | |
| 157 | interrupts = <26>, <34>; | |
| 158 | interrupt-names = "dsp", "iva"; | |
| 159 | ti,hwmods = "mailbox"; | |
| 160 | }; | |
| 161 | ||
| fab8ad0b | 162 | timer1: timer@48028000 { |
| 002e1ec5 | 163 | compatible = "ti,omap2420-timer"; |
| fab8ad0b JH |
164 | reg = <0x48028000 0x400>; |
| 165 | interrupts = <37>; | |
| 166 | ti,hwmods = "timer1"; | |
| 167 | ti,timer-alwon; | |
| 168 | }; | |
| 467f4bd2 TL |
169 | |
| 170 | wd_timer2: wdt@48022000 { | |
| 171 | compatible = "ti,omap2-wdt"; | |
| 172 | ti,hwmods = "wd_timer2"; | |
| 173 | reg = <0x48022000 0x80>; | |
| 174 | }; | |
| 3f187f82 PU |
175 | }; |
| 176 | }; | |
| 467f4bd2 TL |
177 | |
| 178 | &i2c1 { | |
| 179 | compatible = "ti,omap2420-i2c"; | |
| 180 | }; | |
| 181 | ||
| 182 | &i2c2 { | |
| 183 | compatible = "ti,omap2420-i2c"; | |
| 184 | }; |