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1cf30709 | 1 | // SPDX-License-Identifier: GPL-2.0 |
31ac0d69 | 2 | /* |
a63e3d2a | 3 | * Copyright (c) 2017-2018 MediaTek Inc. |
571b9589 | 4 | * Author: John Crispin <john@phrozen.org> |
d4c794f3 | 5 | * Sean Wang <sean.wang@mediatek.com> |
31ac0d69 | 6 | * |
31ac0d69 JC |
7 | */ |
8 | ||
9 | #include <dt-bindings/interrupt-controller/irq.h> | |
10 | #include <dt-bindings/interrupt-controller/arm-gic.h> | |
fbf6ad10 | 11 | #include <dt-bindings/clock/mt2701-clk.h> |
7ed9672f | 12 | #include <dt-bindings/pinctrl/mt7623-pinfunc.h> |
608cc0c0 | 13 | #include <dt-bindings/power/mt2701-power.h> |
7ed9672f JC |
14 | #include <dt-bindings/gpio/gpio.h> |
15 | #include <dt-bindings/phy/phy.h> | |
fbf6ad10 | 16 | #include <dt-bindings/reset/mt2701-resets.h> |
f4ff257c | 17 | #include <dt-bindings/thermal/thermal.h> |
31ac0d69 JC |
18 | |
19 | / { | |
20 | compatible = "mediatek,mt7623"; | |
21 | interrupt-parent = <&sysirq>; | |
c0b0d540 SW |
22 | #address-cells = <2>; |
23 | #size-cells = <2>; | |
31ac0d69 | 24 | |
58b36967 | 25 | cpu_opp_table: opp-table { |
f4ff257c SW |
26 | compatible = "operating-points-v2"; |
27 | opp-shared; | |
28 | ||
29 | opp-98000000 { | |
30 | opp-hz = /bits/ 64 <98000000>; | |
31 | opp-microvolt = <1050000>; | |
32 | }; | |
33 | ||
34 | opp-198000000 { | |
35 | opp-hz = /bits/ 64 <198000000>; | |
36 | opp-microvolt = <1050000>; | |
37 | }; | |
38 | ||
39 | opp-398000000 { | |
40 | opp-hz = /bits/ 64 <398000000>; | |
41 | opp-microvolt = <1050000>; | |
42 | }; | |
43 | ||
44 | opp-598000000 { | |
45 | opp-hz = /bits/ 64 <598000000>; | |
46 | opp-microvolt = <1050000>; | |
47 | }; | |
48 | ||
49 | opp-747500000 { | |
50 | opp-hz = /bits/ 64 <747500000>; | |
51 | opp-microvolt = <1050000>; | |
52 | }; | |
53 | ||
54 | opp-1040000000 { | |
55 | opp-hz = /bits/ 64 <1040000000>; | |
56 | opp-microvolt = <1150000>; | |
57 | }; | |
58 | ||
59 | opp-1196000000 { | |
60 | opp-hz = /bits/ 64 <1196000000>; | |
61 | opp-microvolt = <1200000>; | |
62 | }; | |
63 | ||
64 | opp-1300000000 { | |
65 | opp-hz = /bits/ 64 <1300000000>; | |
66 | opp-microvolt = <1300000>; | |
67 | }; | |
68 | }; | |
69 | ||
31ac0d69 JC |
70 | cpus { |
71 | #address-cells = <1>; | |
72 | #size-cells = <0>; | |
27f99788 | 73 | enable-method = "mediatek,mt6589-smp"; |
31ac0d69 | 74 | |
c5749d34 | 75 | cpu0: cpu@0 { |
31ac0d69 JC |
76 | device_type = "cpu"; |
77 | compatible = "arm,cortex-a7"; | |
78 | reg = <0x0>; | |
f4ff257c SW |
79 | clocks = <&infracfg CLK_INFRA_CPUSEL>, |
80 | <&apmixedsys CLK_APMIXED_MAINPLL>; | |
81 | clock-names = "cpu", "intermediate"; | |
82 | operating-points-v2 = <&cpu_opp_table>; | |
83 | #cooling-cells = <2>; | |
63edf128 | 84 | clock-frequency = <1300000000>; |
31ac0d69 | 85 | }; |
dfff569a | 86 | |
c5749d34 | 87 | cpu1: cpu@1 { |
31ac0d69 JC |
88 | device_type = "cpu"; |
89 | compatible = "arm,cortex-a7"; | |
90 | reg = <0x1>; | |
8e908df6 SW |
91 | clocks = <&infracfg CLK_INFRA_CPUSEL>, |
92 | <&apmixedsys CLK_APMIXED_MAINPLL>; | |
93 | clock-names = "cpu", "intermediate"; | |
f4ff257c | 94 | operating-points-v2 = <&cpu_opp_table>; |
0c7f7a51 | 95 | #cooling-cells = <2>; |
63edf128 | 96 | clock-frequency = <1300000000>; |
31ac0d69 | 97 | }; |
dfff569a | 98 | |
c5749d34 | 99 | cpu2: cpu@2 { |
31ac0d69 JC |
100 | device_type = "cpu"; |
101 | compatible = "arm,cortex-a7"; | |
102 | reg = <0x2>; | |
8e908df6 SW |
103 | clocks = <&infracfg CLK_INFRA_CPUSEL>, |
104 | <&apmixedsys CLK_APMIXED_MAINPLL>; | |
105 | clock-names = "cpu", "intermediate"; | |
f4ff257c | 106 | operating-points-v2 = <&cpu_opp_table>; |
0c7f7a51 | 107 | #cooling-cells = <2>; |
63edf128 | 108 | clock-frequency = <1300000000>; |
31ac0d69 | 109 | }; |
dfff569a | 110 | |
c5749d34 | 111 | cpu3: cpu@3 { |
31ac0d69 JC |
112 | device_type = "cpu"; |
113 | compatible = "arm,cortex-a7"; | |
114 | reg = <0x3>; | |
8e908df6 SW |
115 | clocks = <&infracfg CLK_INFRA_CPUSEL>, |
116 | <&apmixedsys CLK_APMIXED_MAINPLL>; | |
117 | clock-names = "cpu", "intermediate"; | |
f4ff257c | 118 | operating-points-v2 = <&cpu_opp_table>; |
0c7f7a51 | 119 | #cooling-cells = <2>; |
63edf128 | 120 | clock-frequency = <1300000000>; |
31ac0d69 JC |
121 | }; |
122 | }; | |
123 | ||
124 | system_clk: dummy13m { | |
125 | compatible = "fixed-clock"; | |
126 | clock-frequency = <13000000>; | |
127 | #clock-cells = <0>; | |
128 | }; | |
129 | ||
1c8fadd3 | 130 | rtc32k: oscillator-1 { |
31ac0d69 | 131 | compatible = "fixed-clock"; |
31ac0d69 | 132 | #clock-cells = <0>; |
fbf6ad10 JC |
133 | clock-frequency = <32000>; |
134 | clock-output-names = "rtc32k"; | |
31ac0d69 JC |
135 | }; |
136 | ||
1c8fadd3 | 137 | clk26m: oscillator-0 { |
31ac0d69 | 138 | compatible = "fixed-clock"; |
31ac0d69 | 139 | #clock-cells = <0>; |
fbf6ad10 JC |
140 | clock-frequency = <26000000>; |
141 | clock-output-names = "clk26m"; | |
31ac0d69 JC |
142 | }; |
143 | ||
f4ff257c | 144 | thermal-zones { |
58b36967 | 145 | cpu_thermal: cpu-thermal { |
f4ff257c SW |
146 | polling-delay-passive = <1000>; |
147 | polling-delay = <1000>; | |
148 | ||
149 | thermal-sensors = <&thermal 0>; | |
150 | ||
151 | trips { | |
58b36967 | 152 | cpu_passive: cpu-passive { |
f4ff257c SW |
153 | temperature = <47000>; |
154 | hysteresis = <2000>; | |
155 | type = "passive"; | |
156 | }; | |
157 | ||
58b36967 | 158 | cpu_active: cpu-active { |
f4ff257c SW |
159 | temperature = <67000>; |
160 | hysteresis = <2000>; | |
161 | type = "active"; | |
162 | }; | |
163 | ||
58b36967 | 164 | cpu_hot: cpu-hot { |
f4ff257c SW |
165 | temperature = <87000>; |
166 | hysteresis = <2000>; | |
167 | type = "hot"; | |
168 | }; | |
169 | ||
58b36967 | 170 | cpu-crit { |
f4ff257c SW |
171 | temperature = <107000>; |
172 | hysteresis = <2000>; | |
173 | type = "critical"; | |
174 | }; | |
175 | }; | |
176 | ||
177 | cooling-maps { | |
178 | map0 { | |
179 | trip = <&cpu_passive>; | |
180 | cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; | |
181 | }; | |
dfff569a | 182 | |
f4ff257c SW |
183 | map1 { |
184 | trip = <&cpu_active>; | |
185 | cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; | |
186 | }; | |
dfff569a | 187 | |
f4ff257c SW |
188 | map2 { |
189 | trip = <&cpu_hot>; | |
190 | cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; | |
191 | }; | |
192 | }; | |
193 | }; | |
194 | }; | |
195 | ||
31ac0d69 JC |
196 | timer { |
197 | compatible = "arm,armv7-timer"; | |
198 | interrupt-parent = <&gic>; | |
199 | interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>, | |
200 | <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>, | |
201 | <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>, | |
202 | <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>; | |
7e6c7fe9 JC |
203 | clock-frequency = <13000000>; |
204 | arm,cpu-registers-not-fw-configured; | |
31ac0d69 JC |
205 | }; |
206 | ||
fbf6ad10 JC |
207 | topckgen: syscon@10000000 { |
208 | compatible = "mediatek,mt7623-topckgen", | |
209 | "mediatek,mt2701-topckgen", | |
210 | "syscon"; | |
211 | reg = <0 0x10000000 0 0x1000>; | |
212 | #clock-cells = <1>; | |
213 | }; | |
214 | ||
215 | infracfg: syscon@10001000 { | |
216 | compatible = "mediatek,mt7623-infracfg", | |
217 | "mediatek,mt2701-infracfg", | |
218 | "syscon"; | |
219 | reg = <0 0x10001000 0 0x1000>; | |
220 | #clock-cells = <1>; | |
221 | #reset-cells = <1>; | |
222 | }; | |
223 | ||
224 | pericfg: syscon@10003000 { | |
225 | compatible = "mediatek,mt7623-pericfg", | |
226 | "mediatek,mt2701-pericfg", | |
227 | "syscon"; | |
228 | reg = <0 0x10003000 0 0x1000>; | |
229 | #clock-cells = <1>; | |
230 | #reset-cells = <1>; | |
231 | }; | |
7ed9672f JC |
232 | |
233 | pio: pinctrl@10005000 { | |
eb54a522 | 234 | compatible = "mediatek,mt7623-pinctrl"; |
7ed9672f JC |
235 | reg = <0 0x1000b000 0 0x1000>; |
236 | mediatek,pctl-regmap = <&syscfg_pctl_a>; | |
237 | pins-are-numbered; | |
238 | gpio-controller; | |
239 | #gpio-cells = <2>; | |
240 | interrupt-controller; | |
241 | interrupt-parent = <&gic>; | |
242 | #interrupt-cells = <2>; | |
243 | interrupts = <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>, | |
244 | <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>; | |
245 | }; | |
246 | ||
247 | syscfg_pctl_a: syscfg@10005000 { | |
248 | compatible = "mediatek,mt7623-pctl-a-syscfg", "syscon"; | |
249 | reg = <0 0x10005000 0 0x1000>; | |
250 | }; | |
fbf6ad10 | 251 | |
608cc0c0 JC |
252 | scpsys: scpsys@10006000 { |
253 | compatible = "mediatek,mt7623-scpsys", | |
254 | "mediatek,mt2701-scpsys", | |
255 | "syscon"; | |
256 | #power-domain-cells = <1>; | |
257 | reg = <0 0x10006000 0 0x1000>; | |
258 | infracfg = <&infracfg>; | |
259 | clocks = <&topckgen CLK_TOP_MM_SEL>, | |
260 | <&topckgen CLK_TOP_MFG_SEL>, | |
261 | <&topckgen CLK_TOP_ETHIF_SEL>; | |
262 | clock-names = "mm", "mfg", "ethif"; | |
263 | }; | |
264 | ||
31ac0d69 JC |
265 | watchdog: watchdog@10007000 { |
266 | compatible = "mediatek,mt7623-wdt", | |
267 | "mediatek,mt6589-wdt"; | |
268 | reg = <0 0x10007000 0 0x100>; | |
269 | }; | |
270 | ||
271 | timer: timer@10008000 { | |
272 | compatible = "mediatek,mt7623-timer", | |
273 | "mediatek,mt6577-timer"; | |
274 | reg = <0 0x10008000 0 0x80>; | |
275 | interrupts = <GIC_SPI 112 IRQ_TYPE_LEVEL_LOW>; | |
fbf6ad10 | 276 | clocks = <&system_clk>, <&rtc32k>; |
31ac0d69 JC |
277 | clock-names = "system-clk", "rtc-clk"; |
278 | }; | |
279 | ||
cd294fb0 JC |
280 | pwrap: pwrap@1000d000 { |
281 | compatible = "mediatek,mt7623-pwrap", | |
282 | "mediatek,mt2701-pwrap"; | |
283 | reg = <0 0x1000d000 0 0x1000>; | |
284 | reg-names = "pwrap"; | |
285 | interrupts = <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>; | |
286 | resets = <&infracfg MT2701_INFRA_PMIC_WRAP_RST>; | |
287 | reset-names = "pwrap"; | |
288 | clocks = <&infracfg CLK_INFRA_PMICSPI>, | |
289 | <&infracfg CLK_INFRA_PMICWRAP>; | |
290 | clock-names = "spi", "wrap"; | |
291 | }; | |
292 | ||
f4ff257c | 293 | cir: cir@10013000 { |
91044f38 SW |
294 | compatible = "mediatek,mt7623-cir"; |
295 | reg = <0 0x10013000 0 0x1000>; | |
296 | interrupts = <GIC_SPI 87 IRQ_TYPE_LEVEL_LOW>; | |
297 | clocks = <&infracfg CLK_INFRA_IRRX>; | |
298 | clock-names = "clk"; | |
299 | status = "disabled"; | |
300 | }; | |
301 | ||
31ac0d69 JC |
302 | sysirq: interrupt-controller@10200100 { |
303 | compatible = "mediatek,mt7623-sysirq", | |
304 | "mediatek,mt6577-sysirq"; | |
305 | interrupt-controller; | |
306 | #interrupt-cells = <3>; | |
307 | interrupt-parent = <&gic>; | |
308 | reg = <0 0x10200100 0 0x1c>; | |
309 | }; | |
310 | ||
43c7a91b SW |
311 | efuse: efuse@10206000 { |
312 | compatible = "mediatek,mt7623-efuse", | |
313 | "mediatek,mt8173-efuse"; | |
f4ff257c | 314 | reg = <0 0x10206000 0 0x1000>; |
43c7a91b SW |
315 | #address-cells = <1>; |
316 | #size-cells = <1>; | |
317 | thermal_calibration_data: calib@424 { | |
318 | reg = <0x424 0xc>; | |
319 | }; | |
320 | }; | |
321 | ||
fbf6ad10 JC |
322 | apmixedsys: syscon@10209000 { |
323 | compatible = "mediatek,mt7623-apmixedsys", | |
324 | "mediatek,mt2701-apmixedsys", | |
325 | "syscon"; | |
326 | reg = <0 0x10209000 0 0x1000>; | |
327 | #clock-cells = <1>; | |
328 | }; | |
329 | ||
88b43a7b SW |
330 | rng: rng@1020f000 { |
331 | compatible = "mediatek,mt7623-rng"; | |
332 | reg = <0 0x1020f000 0 0x1000>; | |
333 | clocks = <&infracfg CLK_INFRA_TRNG>; | |
334 | clock-names = "rng"; | |
335 | }; | |
336 | ||
31ac0d69 JC |
337 | gic: interrupt-controller@10211000 { |
338 | compatible = "arm,cortex-a7-gic"; | |
339 | interrupt-controller; | |
340 | #interrupt-cells = <3>; | |
341 | interrupt-parent = <&gic>; | |
342 | reg = <0 0x10211000 0 0x1000>, | |
387720c9 | 343 | <0 0x10212000 0 0x2000>, |
31ac0d69 JC |
344 | <0 0x10214000 0 0x2000>, |
345 | <0 0x10216000 0 0x2000>; | |
346 | }; | |
347 | ||
38b244b5 SW |
348 | auxadc: adc@11001000 { |
349 | compatible = "mediatek,mt7623-auxadc", | |
350 | "mediatek,mt2701-auxadc"; | |
351 | reg = <0 0x11001000 0 0x1000>; | |
352 | clocks = <&pericfg CLK_PERI_AUXADC>; | |
353 | clock-names = "main"; | |
354 | #io-channel-cells = <1>; | |
355 | }; | |
356 | ||
31ac0d69 JC |
357 | uart0: serial@11002000 { |
358 | compatible = "mediatek,mt7623-uart", | |
359 | "mediatek,mt6577-uart"; | |
360 | reg = <0 0x11002000 0 0x400>; | |
361 | interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_LOW>; | |
fbf6ad10 JC |
362 | clocks = <&pericfg CLK_PERI_UART0_SEL>, |
363 | <&pericfg CLK_PERI_UART0>; | |
364 | clock-names = "baud", "bus"; | |
31ac0d69 JC |
365 | status = "disabled"; |
366 | }; | |
367 | ||
368 | uart1: serial@11003000 { | |
369 | compatible = "mediatek,mt7623-uart", | |
370 | "mediatek,mt6577-uart"; | |
371 | reg = <0 0x11003000 0 0x400>; | |
372 | interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_LOW>; | |
fbf6ad10 JC |
373 | clocks = <&pericfg CLK_PERI_UART1_SEL>, |
374 | <&pericfg CLK_PERI_UART1>; | |
375 | clock-names = "baud", "bus"; | |
31ac0d69 JC |
376 | status = "disabled"; |
377 | }; | |
378 | ||
379 | uart2: serial@11004000 { | |
380 | compatible = "mediatek,mt7623-uart", | |
381 | "mediatek,mt6577-uart"; | |
382 | reg = <0 0x11004000 0 0x400>; | |
383 | interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_LOW>; | |
fbf6ad10 JC |
384 | clocks = <&pericfg CLK_PERI_UART2_SEL>, |
385 | <&pericfg CLK_PERI_UART2>; | |
386 | clock-names = "baud", "bus"; | |
31ac0d69 JC |
387 | status = "disabled"; |
388 | }; | |
389 | ||
390 | uart3: serial@11005000 { | |
391 | compatible = "mediatek,mt7623-uart", | |
392 | "mediatek,mt6577-uart"; | |
393 | reg = <0 0x11005000 0 0x400>; | |
394 | interrupts = <GIC_SPI 54 IRQ_TYPE_LEVEL_LOW>; | |
fbf6ad10 JC |
395 | clocks = <&pericfg CLK_PERI_UART3_SEL>, |
396 | <&pericfg CLK_PERI_UART3>; | |
397 | clock-names = "baud", "bus"; | |
31ac0d69 JC |
398 | status = "disabled"; |
399 | }; | |
8bb656d9 | 400 | |
ffdbc3cf SW |
401 | pwm: pwm@11006000 { |
402 | compatible = "mediatek,mt7623-pwm"; | |
403 | reg = <0 0x11006000 0 0x1000>; | |
404 | #pwm-cells = <2>; | |
405 | clocks = <&topckgen CLK_TOP_PWM_SEL>, | |
406 | <&pericfg CLK_PERI_PWM>, | |
407 | <&pericfg CLK_PERI_PWM1>, | |
408 | <&pericfg CLK_PERI_PWM2>, | |
409 | <&pericfg CLK_PERI_PWM3>, | |
410 | <&pericfg CLK_PERI_PWM4>, | |
411 | <&pericfg CLK_PERI_PWM5>; | |
412 | clock-names = "top", "main", "pwm1", "pwm2", | |
413 | "pwm3", "pwm4", "pwm5"; | |
414 | status = "disabled"; | |
415 | }; | |
416 | ||
076f8710 JC |
417 | i2c0: i2c@11007000 { |
418 | compatible = "mediatek,mt7623-i2c", | |
419 | "mediatek,mt6577-i2c"; | |
420 | reg = <0 0x11007000 0 0x70>, | |
421 | <0 0x11000200 0 0x80>; | |
422 | interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_LOW>; | |
423 | clock-div = <16>; | |
424 | clocks = <&pericfg CLK_PERI_I2C0>, | |
425 | <&pericfg CLK_PERI_AP_DMA>; | |
426 | clock-names = "main", "dma"; | |
427 | #address-cells = <1>; | |
428 | #size-cells = <0>; | |
429 | status = "disabled"; | |
430 | }; | |
431 | ||
432 | i2c1: i2c@11008000 { | |
433 | compatible = "mediatek,mt7623-i2c", | |
434 | "mediatek,mt6577-i2c"; | |
435 | reg = <0 0x11008000 0 0x70>, | |
436 | <0 0x11000280 0 0x80>; | |
437 | interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_LOW>; | |
438 | clock-div = <16>; | |
439 | clocks = <&pericfg CLK_PERI_I2C1>, | |
440 | <&pericfg CLK_PERI_AP_DMA>; | |
441 | clock-names = "main", "dma"; | |
442 | #address-cells = <1>; | |
443 | #size-cells = <0>; | |
444 | status = "disabled"; | |
445 | }; | |
446 | ||
447 | i2c2: i2c@11009000 { | |
448 | compatible = "mediatek,mt7623-i2c", | |
449 | "mediatek,mt6577-i2c"; | |
450 | reg = <0 0x11009000 0 0x70>, | |
451 | <0 0x11000300 0 0x80>; | |
452 | interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_LOW>; | |
453 | clock-div = <16>; | |
454 | clocks = <&pericfg CLK_PERI_I2C2>, | |
455 | <&pericfg CLK_PERI_AP_DMA>; | |
456 | clock-names = "main", "dma"; | |
457 | #address-cells = <1>; | |
458 | #size-cells = <0>; | |
459 | status = "disabled"; | |
460 | }; | |
461 | ||
44893591 SW |
462 | spi0: spi@1100a000 { |
463 | compatible = "mediatek,mt7623-spi", | |
464 | "mediatek,mt2701-spi"; | |
465 | #address-cells = <1>; | |
466 | #size-cells = <0>; | |
467 | reg = <0 0x1100a000 0 0x100>; | |
468 | interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_LOW>; | |
469 | clocks = <&topckgen CLK_TOP_SYSPLL3_D2>, | |
470 | <&topckgen CLK_TOP_SPI0_SEL>, | |
471 | <&pericfg CLK_PERI_SPI0>; | |
472 | clock-names = "parent-clk", "sel-clk", "spi-clk"; | |
473 | status = "disabled"; | |
474 | }; | |
475 | ||
9794a090 SW |
476 | thermal: thermal@1100b000 { |
477 | #thermal-sensor-cells = <1>; | |
478 | compatible = "mediatek,mt7623-thermal", | |
479 | "mediatek,mt2701-thermal"; | |
480 | reg = <0 0x1100b000 0 0x1000>; | |
481 | interrupts = <0 70 IRQ_TYPE_LEVEL_LOW>; | |
482 | clocks = <&pericfg CLK_PERI_THERM>, <&pericfg CLK_PERI_AUXADC>; | |
483 | clock-names = "therm", "auxadc"; | |
484 | resets = <&pericfg MT2701_PERI_THERM_SW_RST>; | |
485 | reset-names = "therm"; | |
486 | mediatek,auxadc = <&auxadc>; | |
487 | mediatek,apmixedsys = <&apmixedsys>; | |
488 | nvmem-cells = <&thermal_calibration_data>; | |
489 | nvmem-cell-names = "calibration-data"; | |
490 | }; | |
491 | ||
a63e3d2a SW |
492 | btif: serial@1100c000 { |
493 | compatible = "mediatek,mt7623-btif", | |
494 | "mediatek,mtk-btif"; | |
495 | reg = <0 0x1100c000 0 0x1000>; | |
496 | interrupts = <GIC_SPI 50 IRQ_TYPE_LEVEL_LOW>; | |
497 | clocks = <&pericfg CLK_PERI_BTIF>; | |
498 | clock-names = "main"; | |
499 | reg-shift = <2>; | |
500 | reg-io-width = <4>; | |
501 | status = "disabled"; | |
502 | }; | |
503 | ||
dfff569a RL |
504 | nandc: nfi@1100d000 { |
505 | compatible = "mediatek,mt7623-nfc", | |
506 | "mediatek,mt2701-nfc"; | |
507 | reg = <0 0x1100d000 0 0x1000>; | |
508 | interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_LOW>; | |
509 | power-domains = <&scpsys MT2701_POWER_DOMAIN_IFR_MSC>; | |
510 | clocks = <&pericfg CLK_PERI_NFI>, | |
511 | <&pericfg CLK_PERI_NFI_PAD>; | |
512 | clock-names = "nfi_clk", "pad_clk"; | |
513 | status = "disabled"; | |
514 | ecc-engine = <&bch>; | |
515 | #address-cells = <1>; | |
516 | #size-cells = <0>; | |
517 | }; | |
518 | ||
519 | bch: ecc@1100e000 { | |
520 | compatible = "mediatek,mt7623-ecc", | |
521 | "mediatek,mt2701-ecc"; | |
522 | reg = <0 0x1100e000 0 0x1000>; | |
523 | interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_LOW>; | |
524 | clocks = <&pericfg CLK_PERI_NFI_ECC>; | |
525 | clock-names = "nfiecc_clk"; | |
526 | status = "disabled"; | |
527 | }; | |
528 | ||
a63e3d2a SW |
529 | nor_flash: spi@11014000 { |
530 | compatible = "mediatek,mt7623-nor", | |
531 | "mediatek,mt8173-nor"; | |
532 | reg = <0 0x11014000 0 0x1000>; | |
533 | clocks = <&pericfg CLK_PERI_FLASH>, | |
534 | <&topckgen CLK_TOP_FLASH_SEL>; | |
535 | clock-names = "spi", "sf"; | |
536 | #address-cells = <1>; | |
537 | #size-cells = <0>; | |
538 | status = "disabled"; | |
539 | }; | |
540 | ||
44893591 SW |
541 | spi1: spi@11016000 { |
542 | compatible = "mediatek,mt7623-spi", | |
543 | "mediatek,mt2701-spi"; | |
544 | #address-cells = <1>; | |
545 | #size-cells = <0>; | |
546 | reg = <0 0x11016000 0 0x100>; | |
547 | interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_LOW>; | |
548 | clocks = <&topckgen CLK_TOP_SYSPLL3_D2>, | |
549 | <&topckgen CLK_TOP_SPI1_SEL>, | |
550 | <&pericfg CLK_PERI_SPI1>; | |
551 | clock-names = "parent-clk", "sel-clk", "spi-clk"; | |
552 | status = "disabled"; | |
553 | }; | |
554 | ||
555 | spi2: spi@11017000 { | |
556 | compatible = "mediatek,mt7623-spi", | |
557 | "mediatek,mt2701-spi"; | |
558 | #address-cells = <1>; | |
559 | #size-cells = <0>; | |
560 | reg = <0 0x11017000 0 0x1000>; | |
561 | interrupts = <GIC_SPI 142 IRQ_TYPE_LEVEL_LOW>; | |
562 | clocks = <&topckgen CLK_TOP_SYSPLL3_D2>, | |
563 | <&topckgen CLK_TOP_SPI2_SEL>, | |
564 | <&pericfg CLK_PERI_SPI2>; | |
565 | clock-names = "parent-clk", "sel-clk", "spi-clk"; | |
566 | status = "disabled"; | |
567 | }; | |
568 | ||
8eef6dea RL |
569 | audsys: clock-controller@11220000 { |
570 | compatible = "mediatek,mt7623-audsys", | |
571 | "mediatek,mt2701-audsys", | |
572 | "syscon"; | |
573 | reg = <0 0x11220000 0 0x2000>; | |
574 | #clock-cells = <1>; | |
96c390a7 | 575 | |
8eef6dea RL |
576 | afe: audio-controller { |
577 | compatible = "mediatek,mt7623-audio", | |
578 | "mediatek,mt2701-audio"; | |
579 | interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_LOW>, | |
580 | <GIC_SPI 132 IRQ_TYPE_LEVEL_LOW>; | |
581 | interrupt-names = "afe", "asys"; | |
582 | power-domains = <&scpsys MT2701_POWER_DOMAIN_IFR_MSC>; | |
583 | ||
584 | clocks = <&infracfg CLK_INFRA_AUDIO>, | |
585 | <&topckgen CLK_TOP_AUD_MUX1_SEL>, | |
586 | <&topckgen CLK_TOP_AUD_MUX2_SEL>, | |
587 | <&topckgen CLK_TOP_AUD_48K_TIMING>, | |
588 | <&topckgen CLK_TOP_AUD_44K_TIMING>, | |
589 | <&topckgen CLK_TOP_AUD_K1_SRC_SEL>, | |
590 | <&topckgen CLK_TOP_AUD_K2_SRC_SEL>, | |
591 | <&topckgen CLK_TOP_AUD_K3_SRC_SEL>, | |
592 | <&topckgen CLK_TOP_AUD_K4_SRC_SEL>, | |
593 | <&topckgen CLK_TOP_AUD_K1_SRC_DIV>, | |
594 | <&topckgen CLK_TOP_AUD_K2_SRC_DIV>, | |
595 | <&topckgen CLK_TOP_AUD_K3_SRC_DIV>, | |
596 | <&topckgen CLK_TOP_AUD_K4_SRC_DIV>, | |
597 | <&topckgen CLK_TOP_AUD_I2S1_MCLK>, | |
598 | <&topckgen CLK_TOP_AUD_I2S2_MCLK>, | |
599 | <&topckgen CLK_TOP_AUD_I2S3_MCLK>, | |
600 | <&topckgen CLK_TOP_AUD_I2S4_MCLK>, | |
601 | <&audsys CLK_AUD_I2SO1>, | |
602 | <&audsys CLK_AUD_I2SO2>, | |
603 | <&audsys CLK_AUD_I2SO3>, | |
604 | <&audsys CLK_AUD_I2SO4>, | |
605 | <&audsys CLK_AUD_I2SIN1>, | |
606 | <&audsys CLK_AUD_I2SIN2>, | |
607 | <&audsys CLK_AUD_I2SIN3>, | |
608 | <&audsys CLK_AUD_I2SIN4>, | |
609 | <&audsys CLK_AUD_ASRCO1>, | |
610 | <&audsys CLK_AUD_ASRCO2>, | |
611 | <&audsys CLK_AUD_ASRCO3>, | |
612 | <&audsys CLK_AUD_ASRCO4>, | |
613 | <&audsys CLK_AUD_AFE>, | |
614 | <&audsys CLK_AUD_AFE_CONN>, | |
615 | <&audsys CLK_AUD_A1SYS>, | |
616 | <&audsys CLK_AUD_A2SYS>, | |
617 | <&audsys CLK_AUD_AFE_MRGIF>; | |
618 | ||
619 | clock-names = "infra_sys_audio_clk", | |
620 | "top_audio_mux1_sel", | |
621 | "top_audio_mux2_sel", | |
622 | "top_audio_a1sys_hp", | |
623 | "top_audio_a2sys_hp", | |
624 | "i2s0_src_sel", | |
625 | "i2s1_src_sel", | |
626 | "i2s2_src_sel", | |
627 | "i2s3_src_sel", | |
628 | "i2s0_src_div", | |
629 | "i2s1_src_div", | |
630 | "i2s2_src_div", | |
631 | "i2s3_src_div", | |
632 | "i2s0_mclk_en", | |
633 | "i2s1_mclk_en", | |
634 | "i2s2_mclk_en", | |
635 | "i2s3_mclk_en", | |
636 | "i2so0_hop_ck", | |
637 | "i2so1_hop_ck", | |
638 | "i2so2_hop_ck", | |
639 | "i2so3_hop_ck", | |
640 | "i2si0_hop_ck", | |
641 | "i2si1_hop_ck", | |
642 | "i2si2_hop_ck", | |
643 | "i2si3_hop_ck", | |
644 | "asrc0_out_ck", | |
645 | "asrc1_out_ck", | |
646 | "asrc2_out_ck", | |
647 | "asrc3_out_ck", | |
648 | "audio_afe_pd", | |
649 | "audio_afe_conn_pd", | |
650 | "audio_a1sys_pd", | |
651 | "audio_a2sys_pd", | |
652 | "audio_mrgif_pd"; | |
653 | ||
654 | assigned-clocks = <&topckgen CLK_TOP_AUD_MUX1_SEL>, | |
655 | <&topckgen CLK_TOP_AUD_MUX2_SEL>, | |
656 | <&topckgen CLK_TOP_AUD_MUX1_DIV>, | |
657 | <&topckgen CLK_TOP_AUD_MUX2_DIV>; | |
658 | assigned-clock-parents = <&topckgen CLK_TOP_AUD1PLL_98M>, | |
659 | <&topckgen CLK_TOP_AUD2PLL_90M>; | |
660 | assigned-clock-rates = <0>, <0>, <49152000>, <45158400>; | |
661 | }; | |
96c390a7 SW |
662 | }; |
663 | ||
ffa491c8 JC |
664 | mmc0: mmc@11230000 { |
665 | compatible = "mediatek,mt7623-mmc", | |
3e2af579 | 666 | "mediatek,mt2701-mmc"; |
ffa491c8 JC |
667 | reg = <0 0x11230000 0 0x1000>; |
668 | interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_LOW>; | |
669 | clocks = <&pericfg CLK_PERI_MSDC30_0>, | |
670 | <&topckgen CLK_TOP_MSDC30_0_SEL>; | |
671 | clock-names = "source", "hclk"; | |
672 | status = "disabled"; | |
673 | }; | |
674 | ||
675 | mmc1: mmc@11240000 { | |
676 | compatible = "mediatek,mt7623-mmc", | |
3e2af579 | 677 | "mediatek,mt2701-mmc"; |
ffa491c8 | 678 | reg = <0 0x11240000 0 0x1000>; |
6dec760f | 679 | interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_LOW>; |
ffa491c8 JC |
680 | clocks = <&pericfg CLK_PERI_MSDC30_1>, |
681 | <&topckgen CLK_TOP_MSDC30_1_SEL>; | |
682 | clock-names = "source", "hclk"; | |
683 | status = "disabled"; | |
684 | }; | |
685 | ||
dfff569a RL |
686 | hifsys: syscon@1a000000 { |
687 | compatible = "mediatek,mt7623-hifsys", | |
688 | "mediatek,mt2701-hifsys", | |
689 | "syscon"; | |
690 | reg = <0 0x1a000000 0 0x1000>; | |
691 | #clock-cells = <1>; | |
692 | #reset-cells = <1>; | |
693 | }; | |
694 | ||
c10a98c4 RL |
695 | pcie: pcie@1a140000 { |
696 | compatible = "mediatek,mt7623-pcie"; | |
697 | device_type = "pci"; | |
698 | reg = <0 0x1a140000 0 0x1000>, /* PCIe shared registers */ | |
699 | <0 0x1a142000 0 0x1000>, /* Port0 registers */ | |
700 | <0 0x1a143000 0 0x1000>, /* Port1 registers */ | |
701 | <0 0x1a144000 0 0x1000>; /* Port2 registers */ | |
702 | reg-names = "subsys", "port0", "port1", "port2"; | |
703 | #address-cells = <3>; | |
704 | #size-cells = <2>; | |
705 | #interrupt-cells = <1>; | |
706 | interrupt-map-mask = <0xf800 0 0 0>; | |
707 | interrupt-map = <0x0000 0 0 0 &sysirq GIC_SPI 193 IRQ_TYPE_LEVEL_LOW>, | |
708 | <0x0800 0 0 0 &sysirq GIC_SPI 194 IRQ_TYPE_LEVEL_LOW>, | |
709 | <0x1000 0 0 0 &sysirq GIC_SPI 195 IRQ_TYPE_LEVEL_LOW>; | |
710 | clocks = <&topckgen CLK_TOP_ETHIF_SEL>, | |
711 | <&hifsys CLK_HIFSYS_PCIE0>, | |
712 | <&hifsys CLK_HIFSYS_PCIE1>, | |
713 | <&hifsys CLK_HIFSYS_PCIE2>; | |
714 | clock-names = "free_ck", "sys_ck0", "sys_ck1", "sys_ck2"; | |
715 | resets = <&hifsys MT2701_HIFSYS_PCIE0_RST>, | |
716 | <&hifsys MT2701_HIFSYS_PCIE1_RST>, | |
717 | <&hifsys MT2701_HIFSYS_PCIE2_RST>; | |
718 | reset-names = "pcie-rst0", "pcie-rst1", "pcie-rst2"; | |
719 | phys = <&pcie0_port PHY_TYPE_PCIE>, | |
720 | <&pcie1_port PHY_TYPE_PCIE>, | |
721 | <&u3port1 PHY_TYPE_PCIE>; | |
722 | phy-names = "pcie-phy0", "pcie-phy1", "pcie-phy2"; | |
723 | power-domains = <&scpsys MT2701_POWER_DOMAIN_HIF>; | |
724 | bus-range = <0x00 0xff>; | |
725 | status = "disabled"; | |
726 | ranges = <0x81000000 0 0x1a160000 0 0x1a160000 0 0x00010000 | |
727 | 0x83000000 0 0x60000000 0 0x60000000 0 0x10000000>; | |
728 | ||
729 | pcie@0,0 { | |
730 | reg = <0x0000 0 0 0 0>; | |
731 | #address-cells = <3>; | |
732 | #size-cells = <2>; | |
733 | #interrupt-cells = <1>; | |
734 | interrupt-map-mask = <0 0 0 0>; | |
735 | interrupt-map = <0 0 0 0 &sysirq GIC_SPI 193 IRQ_TYPE_LEVEL_LOW>; | |
736 | ranges; | |
737 | num-lanes = <1>; | |
738 | status = "disabled"; | |
739 | }; | |
740 | ||
741 | pcie@1,0 { | |
742 | reg = <0x0800 0 0 0 0>; | |
743 | #address-cells = <3>; | |
744 | #size-cells = <2>; | |
745 | #interrupt-cells = <1>; | |
746 | interrupt-map-mask = <0 0 0 0>; | |
747 | interrupt-map = <0 0 0 0 &sysirq GIC_SPI 194 IRQ_TYPE_LEVEL_LOW>; | |
748 | ranges; | |
749 | num-lanes = <1>; | |
750 | status = "disabled"; | |
751 | }; | |
752 | ||
753 | pcie@2,0 { | |
754 | reg = <0x1000 0 0 0 0>; | |
755 | #address-cells = <3>; | |
756 | #size-cells = <2>; | |
757 | #interrupt-cells = <1>; | |
758 | interrupt-map-mask = <0 0 0 0>; | |
759 | interrupt-map = <0 0 0 0 &sysirq GIC_SPI 195 IRQ_TYPE_LEVEL_LOW>; | |
760 | ranges; | |
761 | num-lanes = <1>; | |
762 | status = "disabled"; | |
763 | }; | |
764 | }; | |
765 | ||
766 | pcie0_phy: pcie-phy@1a149000 { | |
767 | compatible = "mediatek,generic-tphy-v1"; | |
768 | reg = <0 0x1a149000 0 0x0700>; | |
769 | #address-cells = <2>; | |
770 | #size-cells = <2>; | |
771 | ranges; | |
772 | status = "disabled"; | |
773 | ||
774 | pcie0_port: pcie-phy@1a149900 { | |
775 | reg = <0 0x1a149900 0 0x0700>; | |
776 | clocks = <&clk26m>; | |
777 | clock-names = "ref"; | |
778 | #phy-cells = <1>; | |
779 | status = "okay"; | |
780 | }; | |
781 | }; | |
782 | ||
783 | pcie1_phy: pcie-phy@1a14a000 { | |
784 | compatible = "mediatek,generic-tphy-v1"; | |
785 | reg = <0 0x1a14a000 0 0x0700>; | |
786 | #address-cells = <2>; | |
787 | #size-cells = <2>; | |
788 | ranges; | |
789 | status = "disabled"; | |
790 | ||
791 | pcie1_port: pcie-phy@1a14a900 { | |
792 | reg = <0 0x1a14a900 0 0x0700>; | |
793 | clocks = <&clk26m>; | |
794 | clock-names = "ref"; | |
795 | #phy-cells = <1>; | |
796 | status = "okay"; | |
797 | }; | |
798 | }; | |
799 | ||
35fdd6c9 JC |
800 | usb1: usb@1a1c0000 { |
801 | compatible = "mediatek,mt7623-xhci", | |
802 | "mediatek,mt8173-xhci"; | |
803 | reg = <0 0x1a1c0000 0 0x1000>, | |
804 | <0 0x1a1c4700 0 0x0100>; | |
805 | reg-names = "mac", "ippc"; | |
806 | interrupts = <GIC_SPI 196 IRQ_TYPE_LEVEL_LOW>; | |
807 | clocks = <&hifsys CLK_HIFSYS_USB0PHY>, | |
808 | <&topckgen CLK_TOP_ETHIF_SEL>; | |
e4316d6f | 809 | clock-names = "sys_ck", "ref_ck"; |
35fdd6c9 JC |
810 | power-domains = <&scpsys MT2701_POWER_DOMAIN_HIF>; |
811 | phys = <&u2port0 PHY_TYPE_USB2>, <&u3port0 PHY_TYPE_USB3>; | |
812 | status = "disabled"; | |
813 | }; | |
814 | ||
815 | u3phy1: usb-phy@1a1c4000 { | |
f4ff257c SW |
816 | compatible = "mediatek,mt7623-u3phy", |
817 | "mediatek,mt2701-u3phy"; | |
35fdd6c9 | 818 | reg = <0 0x1a1c4000 0 0x0700>; |
35fdd6c9 JC |
819 | #address-cells = <2>; |
820 | #size-cells = <2>; | |
821 | ranges; | |
822 | status = "disabled"; | |
823 | ||
824 | u2port0: usb-phy@1a1c4800 { | |
825 | reg = <0 0x1a1c4800 0 0x0100>; | |
e4316d6f RL |
826 | clocks = <&topckgen CLK_TOP_USB_PHY48M>; |
827 | clock-names = "ref"; | |
35fdd6c9 JC |
828 | #phy-cells = <1>; |
829 | status = "okay"; | |
830 | }; | |
831 | ||
832 | u3port0: usb-phy@1a1c4900 { | |
833 | reg = <0 0x1a1c4900 0 0x0700>; | |
e4316d6f RL |
834 | clocks = <&clk26m>; |
835 | clock-names = "ref"; | |
35fdd6c9 JC |
836 | #phy-cells = <1>; |
837 | status = "okay"; | |
838 | }; | |
839 | }; | |
840 | ||
841 | usb2: usb@1a240000 { | |
842 | compatible = "mediatek,mt7623-xhci", | |
843 | "mediatek,mt8173-xhci"; | |
844 | reg = <0 0x1a240000 0 0x1000>, | |
845 | <0 0x1a244700 0 0x0100>; | |
846 | reg-names = "mac", "ippc"; | |
847 | interrupts = <GIC_SPI 197 IRQ_TYPE_LEVEL_LOW>; | |
848 | clocks = <&hifsys CLK_HIFSYS_USB1PHY>, | |
849 | <&topckgen CLK_TOP_ETHIF_SEL>; | |
e4316d6f | 850 | clock-names = "sys_ck", "ref_ck"; |
35fdd6c9 JC |
851 | power-domains = <&scpsys MT2701_POWER_DOMAIN_HIF>; |
852 | phys = <&u2port1 PHY_TYPE_USB2>, <&u3port1 PHY_TYPE_USB3>; | |
853 | status = "disabled"; | |
854 | }; | |
855 | ||
856 | u3phy2: usb-phy@1a244000 { | |
f4ff257c SW |
857 | compatible = "mediatek,mt7623-u3phy", |
858 | "mediatek,mt2701-u3phy"; | |
35fdd6c9 | 859 | reg = <0 0x1a244000 0 0x0700>; |
35fdd6c9 JC |
860 | #address-cells = <2>; |
861 | #size-cells = <2>; | |
862 | ranges; | |
863 | status = "disabled"; | |
864 | ||
865 | u2port1: usb-phy@1a244800 { | |
866 | reg = <0 0x1a244800 0 0x0100>; | |
e4316d6f RL |
867 | clocks = <&topckgen CLK_TOP_USB_PHY48M>; |
868 | clock-names = "ref"; | |
35fdd6c9 JC |
869 | #phy-cells = <1>; |
870 | status = "okay"; | |
871 | }; | |
872 | ||
873 | u3port1: usb-phy@1a244900 { | |
874 | reg = <0 0x1a244900 0 0x0700>; | |
e4316d6f RL |
875 | clocks = <&clk26m>; |
876 | clock-names = "ref"; | |
35fdd6c9 JC |
877 | #phy-cells = <1>; |
878 | status = "okay"; | |
879 | }; | |
880 | }; | |
881 | ||
8bb656d9 JC |
882 | ethsys: syscon@1b000000 { |
883 | compatible = "mediatek,mt7623-ethsys", | |
884 | "mediatek,mt2701-ethsys", | |
885 | "syscon"; | |
886 | reg = <0 0x1b000000 0 0x1000>; | |
887 | #clock-cells = <1>; | |
76a09ce2 | 888 | #reset-cells = <1>; |
8bb656d9 | 889 | }; |
687976ae | 890 | |
a63e3d2a SW |
891 | hsdma: dma-controller@1b007000 { |
892 | compatible = "mediatek,mt7623-hsdma"; | |
893 | reg = <0 0x1b007000 0 0x1000>; | |
894 | interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_LOW>; | |
895 | clocks = <ðsys CLK_ETHSYS_HSDMA>; | |
896 | clock-names = "hsdma"; | |
897 | power-domains = <&scpsys MT2701_POWER_DOMAIN_ETH>; | |
898 | #dma-cells = <1>; | |
899 | }; | |
900 | ||
687976ae | 901 | eth: ethernet@1b100000 { |
f4ff257c SW |
902 | compatible = "mediatek,mt7623-eth", |
903 | "mediatek,mt2701-eth", | |
904 | "syscon"; | |
687976ae SW |
905 | reg = <0 0x1b100000 0 0x20000>; |
906 | interrupts = <GIC_SPI 200 IRQ_TYPE_LEVEL_LOW>, | |
907 | <GIC_SPI 199 IRQ_TYPE_LEVEL_LOW>, | |
908 | <GIC_SPI 198 IRQ_TYPE_LEVEL_LOW>; | |
909 | clocks = <&topckgen CLK_TOP_ETHIF_SEL>, | |
910 | <ðsys CLK_ETHSYS_ESW>, | |
911 | <ðsys CLK_ETHSYS_GP1>, | |
912 | <ðsys CLK_ETHSYS_GP2>, | |
913 | <&apmixedsys CLK_APMIXED_TRGPLL>; | |
914 | clock-names = "ethif", "esw", "gp1", "gp2", "trgpll"; | |
d60129db SW |
915 | resets = <ðsys MT2701_ETHSYS_FE_RST>, |
916 | <ðsys MT2701_ETHSYS_GMAC_RST>, | |
917 | <ðsys MT2701_ETHSYS_PPE_RST>; | |
918 | reset-names = "fe", "gmac", "ppe"; | |
687976ae SW |
919 | power-domains = <&scpsys MT2701_POWER_DOMAIN_ETH>; |
920 | mediatek,ethsys = <ðsys>; | |
921 | mediatek,pctl = <&syscfg_pctl_a>; | |
922 | #address-cells = <1>; | |
923 | #size-cells = <0>; | |
924 | status = "disabled"; | |
925 | }; | |
465792e6 SW |
926 | |
927 | crypto: crypto@1b240000 { | |
a336ba44 | 928 | compatible = "mediatek,eip97-crypto"; |
465792e6 SW |
929 | reg = <0 0x1b240000 0 0x20000>; |
930 | interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_LOW>, | |
931 | <GIC_SPI 83 IRQ_TYPE_LEVEL_LOW>, | |
932 | <GIC_SPI 84 IRQ_TYPE_LEVEL_LOW>, | |
933 | <GIC_SPI 91 IRQ_TYPE_LEVEL_LOW>, | |
934 | <GIC_SPI 97 IRQ_TYPE_LEVEL_LOW>; | |
a336ba44 RL |
935 | clocks = <ðsys CLK_ETHSYS_CRYPTO>; |
936 | clock-names = "cryp"; | |
465792e6 | 937 | power-domains = <&scpsys MT2701_POWER_DOMAIN_ETH>; |
31ac0d69 JC |
938 | status = "disabled"; |
939 | }; | |
940 | }; | |
3f7dd2da SW |
941 | |
942 | &pio { | |
943 | cir_pins_a:cir-default { | |
944 | pins-cir { | |
945 | pinmux = <MT7623_PIN_46_IR_FUNC_IR>; | |
946 | bias-disable; | |
947 | }; | |
948 | }; | |
949 | ||
950 | i2c0_pins_a: i2c0-default { | |
951 | pins-i2c0 { | |
952 | pinmux = <MT7623_PIN_75_SDA0_FUNC_SDA0>, | |
953 | <MT7623_PIN_76_SCL0_FUNC_SCL0>; | |
954 | bias-disable; | |
955 | }; | |
956 | }; | |
957 | ||
958 | i2c1_pins_a: i2c1-default { | |
959 | pin-i2c1 { | |
960 | pinmux = <MT7623_PIN_57_SDA1_FUNC_SDA1>, | |
961 | <MT7623_PIN_58_SCL1_FUNC_SCL1>; | |
962 | bias-disable; | |
963 | }; | |
964 | }; | |
965 | ||
25fad0ef SW |
966 | i2c1_pins_b: i2c1-alt { |
967 | pin-i2c1 { | |
968 | pinmux = <MT7623_PIN_242_URTS2_FUNC_SCL1>, | |
969 | <MT7623_PIN_243_UCTS2_FUNC_SDA1>; | |
970 | bias-disable; | |
971 | }; | |
972 | }; | |
973 | ||
dd0dcf00 SW |
974 | i2c2_pins_a: i2c2-default { |
975 | pin-i2c2 { | |
976 | pinmux = <MT7623_PIN_77_SDA2_FUNC_SDA2>, | |
977 | <MT7623_PIN_78_SCL2_FUNC_SCL2>; | |
978 | bias-disable; | |
979 | }; | |
980 | }; | |
981 | ||
25fad0ef SW |
982 | i2c2_pins_b: i2c2-alt { |
983 | pin-i2c2 { | |
984 | pinmux = <MT7623_PIN_122_GPIO122_FUNC_SDA2>, | |
985 | <MT7623_PIN_123_HTPLG_FUNC_SCL2>; | |
986 | bias-disable; | |
987 | }; | |
988 | }; | |
989 | ||
3f7dd2da SW |
990 | i2s0_pins_a: i2s0-default { |
991 | pin-i2s0 { | |
992 | pinmux = <MT7623_PIN_49_I2S0_DATA_FUNC_I2S0_DATA>, | |
993 | <MT7623_PIN_72_I2S0_DATA_IN_FUNC_I2S0_DATA_IN>, | |
994 | <MT7623_PIN_73_I2S0_LRCK_FUNC_I2S0_LRCK>, | |
995 | <MT7623_PIN_74_I2S0_BCK_FUNC_I2S0_BCK>, | |
996 | <MT7623_PIN_126_I2S0_MCLK_FUNC_I2S0_MCLK>; | |
997 | drive-strength = <MTK_DRIVE_12mA>; | |
998 | bias-pull-down; | |
999 | }; | |
1000 | }; | |
1001 | ||
1002 | i2s1_pins_a: i2s1-default { | |
1003 | pin-i2s1 { | |
1004 | pinmux = <MT7623_PIN_33_I2S1_DATA_FUNC_I2S1_DATA>, | |
1005 | <MT7623_PIN_34_I2S1_DATA_IN_FUNC_I2S1_DATA_IN>, | |
1006 | <MT7623_PIN_35_I2S1_BCK_FUNC_I2S1_BCK>, | |
1007 | <MT7623_PIN_36_I2S1_LRCK_FUNC_I2S1_LRCK>, | |
1008 | <MT7623_PIN_37_I2S1_MCLK_FUNC_I2S1_MCLK>; | |
1009 | drive-strength = <MTK_DRIVE_12mA>; | |
1010 | bias-pull-down; | |
1011 | }; | |
1012 | }; | |
1013 | ||
1014 | key_pins_a: keys-alt { | |
1015 | pins-keys { | |
1016 | pinmux = <MT7623_PIN_256_GPIO256_FUNC_GPIO256>, | |
1017 | <MT7623_PIN_257_GPIO257_FUNC_GPIO257> ; | |
1018 | input-enable; | |
1019 | }; | |
1020 | }; | |
1021 | ||
1022 | led_pins_a: leds-alt { | |
1023 | pins-leds { | |
1024 | pinmux = <MT7623_PIN_239_EXT_SDIO0_FUNC_GPIO239>, | |
1025 | <MT7623_PIN_240_EXT_XCS_FUNC_GPIO240>, | |
1026 | <MT7623_PIN_241_EXT_SCK_FUNC_GPIO241>; | |
1027 | }; | |
1028 | }; | |
1029 | ||
1030 | mmc0_pins_default: mmc0default { | |
1031 | pins-cmd-dat { | |
1032 | pinmux = <MT7623_PIN_111_MSDC0_DAT7_FUNC_MSDC0_DAT7>, | |
1033 | <MT7623_PIN_112_MSDC0_DAT6_FUNC_MSDC0_DAT6>, | |
1034 | <MT7623_PIN_113_MSDC0_DAT5_FUNC_MSDC0_DAT5>, | |
1035 | <MT7623_PIN_114_MSDC0_DAT4_FUNC_MSDC0_DAT4>, | |
1036 | <MT7623_PIN_118_MSDC0_DAT3_FUNC_MSDC0_DAT3>, | |
1037 | <MT7623_PIN_119_MSDC0_DAT2_FUNC_MSDC0_DAT2>, | |
1038 | <MT7623_PIN_120_MSDC0_DAT1_FUNC_MSDC0_DAT1>, | |
1039 | <MT7623_PIN_121_MSDC0_DAT0_FUNC_MSDC0_DAT0>, | |
1040 | <MT7623_PIN_116_MSDC0_CMD_FUNC_MSDC0_CMD>; | |
1041 | input-enable; | |
1042 | bias-pull-up; | |
1043 | }; | |
1044 | ||
1045 | pins-clk { | |
1046 | pinmux = <MT7623_PIN_117_MSDC0_CLK_FUNC_MSDC0_CLK>; | |
1047 | bias-pull-down; | |
1048 | }; | |
1049 | ||
1050 | pins-rst { | |
1051 | pinmux = <MT7623_PIN_115_MSDC0_RSTB_FUNC_MSDC0_RSTB>; | |
1052 | bias-pull-up; | |
1053 | }; | |
1054 | }; | |
1055 | ||
1056 | mmc0_pins_uhs: mmc0 { | |
1057 | pins-cmd-dat { | |
1058 | pinmux = <MT7623_PIN_111_MSDC0_DAT7_FUNC_MSDC0_DAT7>, | |
1059 | <MT7623_PIN_112_MSDC0_DAT6_FUNC_MSDC0_DAT6>, | |
1060 | <MT7623_PIN_113_MSDC0_DAT5_FUNC_MSDC0_DAT5>, | |
1061 | <MT7623_PIN_114_MSDC0_DAT4_FUNC_MSDC0_DAT4>, | |
1062 | <MT7623_PIN_118_MSDC0_DAT3_FUNC_MSDC0_DAT3>, | |
1063 | <MT7623_PIN_119_MSDC0_DAT2_FUNC_MSDC0_DAT2>, | |
1064 | <MT7623_PIN_120_MSDC0_DAT1_FUNC_MSDC0_DAT1>, | |
1065 | <MT7623_PIN_121_MSDC0_DAT0_FUNC_MSDC0_DAT0>, | |
1066 | <MT7623_PIN_116_MSDC0_CMD_FUNC_MSDC0_CMD>; | |
1067 | input-enable; | |
1068 | drive-strength = <MTK_DRIVE_2mA>; | |
1069 | bias-pull-up = <MTK_PUPD_SET_R1R0_01>; | |
1070 | }; | |
1071 | ||
1072 | pins-clk { | |
1073 | pinmux = <MT7623_PIN_117_MSDC0_CLK_FUNC_MSDC0_CLK>; | |
1074 | drive-strength = <MTK_DRIVE_2mA>; | |
1075 | bias-pull-down = <MTK_PUPD_SET_R1R0_01>; | |
1076 | }; | |
1077 | ||
1078 | pins-rst { | |
1079 | pinmux = <MT7623_PIN_115_MSDC0_RSTB_FUNC_MSDC0_RSTB>; | |
1080 | bias-pull-up; | |
1081 | }; | |
1082 | }; | |
1083 | ||
1084 | mmc1_pins_default: mmc1default { | |
1085 | pins-cmd-dat { | |
1086 | pinmux = <MT7623_PIN_107_MSDC1_DAT0_FUNC_MSDC1_DAT0>, | |
1087 | <MT7623_PIN_108_MSDC1_DAT1_FUNC_MSDC1_DAT1>, | |
1088 | <MT7623_PIN_109_MSDC1_DAT2_FUNC_MSDC1_DAT2>, | |
1089 | <MT7623_PIN_110_MSDC1_DAT3_FUNC_MSDC1_DAT3>, | |
1090 | <MT7623_PIN_105_MSDC1_CMD_FUNC_MSDC1_CMD>; | |
1091 | input-enable; | |
1092 | drive-strength = <MTK_DRIVE_4mA>; | |
1093 | bias-pull-up = <MTK_PUPD_SET_R1R0_10>; | |
1094 | }; | |
1095 | ||
1096 | pins-clk { | |
1097 | pinmux = <MT7623_PIN_106_MSDC1_CLK_FUNC_MSDC1_CLK>; | |
1098 | bias-pull-down; | |
1099 | drive-strength = <MTK_DRIVE_4mA>; | |
1100 | }; | |
1101 | ||
1102 | pins-wp { | |
1103 | pinmux = <MT7623_PIN_29_EINT7_FUNC_MSDC1_WP>; | |
1104 | input-enable; | |
1105 | bias-pull-up; | |
1106 | }; | |
1107 | ||
1108 | pins-insert { | |
1109 | pinmux = <MT7623_PIN_261_MSDC1_INS_FUNC_GPIO261>; | |
1110 | bias-pull-up; | |
1111 | }; | |
1112 | }; | |
1113 | ||
1114 | mmc1_pins_uhs: mmc1 { | |
1115 | pins-cmd-dat { | |
1116 | pinmux = <MT7623_PIN_107_MSDC1_DAT0_FUNC_MSDC1_DAT0>, | |
1117 | <MT7623_PIN_108_MSDC1_DAT1_FUNC_MSDC1_DAT1>, | |
1118 | <MT7623_PIN_109_MSDC1_DAT2_FUNC_MSDC1_DAT2>, | |
1119 | <MT7623_PIN_110_MSDC1_DAT3_FUNC_MSDC1_DAT3>, | |
1120 | <MT7623_PIN_105_MSDC1_CMD_FUNC_MSDC1_CMD>; | |
1121 | input-enable; | |
1122 | drive-strength = <MTK_DRIVE_4mA>; | |
1123 | bias-pull-up = <MTK_PUPD_SET_R1R0_10>; | |
1124 | }; | |
1125 | ||
1126 | pins-clk { | |
1127 | pinmux = <MT7623_PIN_106_MSDC1_CLK_FUNC_MSDC1_CLK>; | |
1128 | drive-strength = <MTK_DRIVE_4mA>; | |
1129 | bias-pull-down = <MTK_PUPD_SET_R1R0_10>; | |
1130 | }; | |
1131 | }; | |
1132 | ||
1133 | nand_pins_default: nanddefault { | |
1134 | pins-ale { | |
1135 | pinmux = <MT7623_PIN_116_MSDC0_CMD_FUNC_NALE>; | |
1136 | drive-strength = <MTK_DRIVE_8mA>; | |
1137 | bias-pull-down = <MTK_PUPD_SET_R1R0_10>; | |
1138 | }; | |
1139 | ||
1140 | pins-dat { | |
1141 | pinmux = <MT7623_PIN_111_MSDC0_DAT7_FUNC_NLD7>, | |
1142 | <MT7623_PIN_112_MSDC0_DAT6_FUNC_NLD6>, | |
1143 | <MT7623_PIN_114_MSDC0_DAT4_FUNC_NLD4>, | |
1144 | <MT7623_PIN_118_MSDC0_DAT3_FUNC_NLD3>, | |
1145 | <MT7623_PIN_121_MSDC0_DAT0_FUNC_NLD0>, | |
1146 | <MT7623_PIN_120_MSDC0_DAT1_FUNC_NLD1>, | |
1147 | <MT7623_PIN_113_MSDC0_DAT5_FUNC_NLD5>, | |
1148 | <MT7623_PIN_115_MSDC0_RSTB_FUNC_NLD8>, | |
1149 | <MT7623_PIN_119_MSDC0_DAT2_FUNC_NLD2>; | |
1150 | input-enable; | |
1151 | drive-strength = <MTK_DRIVE_8mA>; | |
1152 | bias-pull-up; | |
1153 | }; | |
1154 | ||
1155 | pins-we { | |
1156 | pinmux = <MT7623_PIN_117_MSDC0_CLK_FUNC_NWEB>; | |
1157 | drive-strength = <MTK_DRIVE_8mA>; | |
1158 | bias-pull-up = <MTK_PUPD_SET_R1R0_10>; | |
1159 | }; | |
1160 | }; | |
1161 | ||
1162 | pcie_default: pcie_pin_default { | |
1163 | pins_cmd_dat { | |
1164 | pinmux = <MT7623_PIN_208_AUD_EXT_CK1_FUNC_PCIE0_PERST_N>, | |
1165 | <MT7623_PIN_209_AUD_EXT_CK2_FUNC_PCIE1_PERST_N>; | |
1166 | bias-disable; | |
1167 | }; | |
1168 | }; | |
1169 | ||
1170 | pwm_pins_a: pwm-default { | |
1171 | pins-pwm { | |
1172 | pinmux = <MT7623_PIN_203_PWM0_FUNC_PWM0>, | |
1173 | <MT7623_PIN_204_PWM1_FUNC_PWM1>, | |
1174 | <MT7623_PIN_205_PWM2_FUNC_PWM2>, | |
1175 | <MT7623_PIN_206_PWM3_FUNC_PWM3>, | |
1176 | <MT7623_PIN_207_PWM4_FUNC_PWM4>; | |
1177 | }; | |
1178 | }; | |
1179 | ||
1180 | spi0_pins_a: spi0-default { | |
1181 | pins-spi { | |
1182 | pinmux = <MT7623_PIN_53_SPI0_CSN_FUNC_SPI0_CS>, | |
1183 | <MT7623_PIN_54_SPI0_CK_FUNC_SPI0_CK>, | |
1184 | <MT7623_PIN_55_SPI0_MI_FUNC_SPI0_MI>, | |
1185 | <MT7623_PIN_56_SPI0_MO_FUNC_SPI0_MO>; | |
1186 | bias-disable; | |
1187 | }; | |
1188 | }; | |
1189 | ||
25fad0ef SW |
1190 | spi1_pins_a: spi1-default { |
1191 | pins-spi { | |
1192 | pinmux = <MT7623_PIN_7_SPI1_CSN_FUNC_SPI1_CS>, | |
1193 | <MT7623_PIN_199_SPI1_CK_FUNC_SPI1_CK>, | |
1194 | <MT7623_PIN_8_SPI1_MI_FUNC_SPI1_MI>, | |
1195 | <MT7623_PIN_9_SPI1_MO_FUNC_SPI1_MO>; | |
1196 | }; | |
1197 | }; | |
1198 | ||
dd0dcf00 SW |
1199 | spi2_pins_a: spi2-default { |
1200 | pins-spi { | |
1201 | pinmux = <MT7623_PIN_101_SPI2_CSN_FUNC_SPI2_CS>, | |
1202 | <MT7623_PIN_104_SPI2_CK_FUNC_SPI2_CK>, | |
1203 | <MT7623_PIN_102_SPI2_MI_FUNC_SPI2_MI>, | |
1204 | <MT7623_PIN_103_SPI2_MO_FUNC_SPI2_MO>; | |
1205 | }; | |
1206 | }; | |
1207 | ||
3f7dd2da SW |
1208 | uart0_pins_a: uart0-default { |
1209 | pins-dat { | |
1210 | pinmux = <MT7623_PIN_79_URXD0_FUNC_URXD0>, | |
1211 | <MT7623_PIN_80_UTXD0_FUNC_UTXD0>; | |
1212 | }; | |
1213 | }; | |
1214 | ||
1215 | uart1_pins_a: uart1-default { | |
1216 | pins-dat { | |
1217 | pinmux = <MT7623_PIN_81_URXD1_FUNC_URXD1>, | |
1218 | <MT7623_PIN_82_UTXD1_FUNC_UTXD1>; | |
1219 | }; | |
1220 | }; | |
1221 | ||
1222 | uart2_pins_a: uart2-default { | |
1223 | pins-dat { | |
1224 | pinmux = <MT7623_PIN_14_GPIO14_FUNC_URXD2>, | |
1225 | <MT7623_PIN_15_GPIO15_FUNC_UTXD2>; | |
1226 | }; | |
1227 | }; | |
25fad0ef SW |
1228 | |
1229 | uart2_pins_b: uart2-alt { | |
1230 | pins-dat { | |
1231 | pinmux = <MT7623_PIN_200_URXD2_FUNC_URXD2>, | |
1232 | <MT7623_PIN_201_UTXD2_FUNC_UTXD2>; | |
1233 | }; | |
1234 | }; | |
3f7dd2da | 1235 | }; |