projects / linux-2.6-block.git / blame
| Commit | Line | Data |
|---|---|---|
| 1cf30709 | 1 | // SPDX-License-Identifier: GPL-2.0 |
| 4542172e HC |
2 | /* |
| 3 | * Copyright (c) 2014 MediaTek Inc. | |
| 4 | * Author: Howard Chen <ibanezchen@gmail.com> | |
| 5 | * | |
| 4542172e HC |
6 | */ |
| 7 | ||
| 8 | #include <dt-bindings/interrupt-controller/irq.h> | |
| 9 | #include <dt-bindings/interrupt-controller/arm-gic.h> | |
| 10 | #include "skeleton.dtsi" | |
| 11 | ||
| 12 | / { | |
| 13 | compatible = "mediatek,mt6592"; | |
| c6b3a64f | 14 | interrupt-parent = <&sysirq>; |
| 4542172e HC |
15 | |
| 16 | cpus { | |
| 17 | #address-cells = <1>; | |
| 18 | #size-cells = <0>; | |
| 19 | ||
| 20 | cpu@0 { | |
| 21 | device_type = "cpu"; | |
| 22 | compatible = "arm,cortex-a7"; | |
| 23 | reg = <0x0>; | |
| 24 | }; | |
| 25 | cpu@1 { | |
| 26 | device_type = "cpu"; | |
| 27 | compatible = "arm,cortex-a7"; | |
| 28 | reg = <0x1>; | |
| 29 | }; | |
| 30 | cpu@2 { | |
| 31 | device_type = "cpu"; | |
| 32 | compatible = "arm,cortex-a7"; | |
| 33 | reg = <0x2>; | |
| 34 | }; | |
| 35 | cpu@3 { | |
| 36 | device_type = "cpu"; | |
| 37 | compatible = "arm,cortex-a7"; | |
| 38 | reg = <0x3>; | |
| 39 | }; | |
| 40 | cpu@4 { | |
| 41 | device_type = "cpu"; | |
| 42 | compatible = "arm,cortex-a7"; | |
| 43 | reg = <0x4>; | |
| 44 | }; | |
| 45 | cpu@5 { | |
| 46 | device_type = "cpu"; | |
| 47 | compatible = "arm,cortex-a7"; | |
| 48 | reg = <0x5>; | |
| 49 | }; | |
| 50 | cpu@6 { | |
| 51 | device_type = "cpu"; | |
| 52 | compatible = "arm,cortex-a7"; | |
| 53 | reg = <0x6>; | |
| 54 | }; | |
| 55 | cpu@7 { | |
| 56 | device_type = "cpu"; | |
| 57 | compatible = "arm,cortex-a7"; | |
| 58 | reg = <0x7>; | |
| 59 | }; | |
| 60 | }; | |
| 61 | ||
| 62 | system_clk: dummy13m { | |
| 63 | compatible = "fixed-clock"; | |
| 64 | clock-frequency = <13000000>; | |
| 65 | #clock-cells = <0>; | |
| 66 | }; | |
| 67 | ||
| 68 | rtc_clk: dummy32k { | |
| 69 | compatible = "fixed-clock"; | |
| 70 | clock-frequency = <32000>; | |
| 71 | #clock-cells = <0>; | |
| 72 | }; | |
| 73 | ||
| b8be5663 MB |
74 | uart_clk: dummy26m { |
| 75 | compatible = "fixed-clock"; | |
| 76 | clock-frequency = <26000000>; | |
| 77 | #clock-cells = <0>; | |
| 78 | }; | |
| 79 | ||
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80 | timer: timer@10008000 { |
| 81 | compatible = "mediatek,mt6577-timer"; | |
| 82 | reg = <0x10008000 0x80>; | |
| c6b3a64f | 83 | interrupts = <GIC_SPI 144 IRQ_TYPE_LEVEL_LOW>; |
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84 | clocks = <&system_clk>, <&rtc_clk>; |
| 85 | clock-names = "system-clk", "rtc-clk"; | |
| 86 | }; | |
| 87 | ||
| c6b3a64f HC |
88 | sysirq: interrupt-controller@10200220 { |
| 89 | compatible = "mediatek,mt6592-sysirq", "mediatek,mt6577-sysirq"; | |
| 90 | interrupt-controller; | |
| 91 | #interrupt-cells = <3>; | |
| 92 | interrupt-parent = <&gic>; | |
| 93 | reg = <0x10200220 0x1c>; | |
| 94 | }; | |
| 95 | ||
| 4542172e HC |
96 | gic: interrupt-controller@10211000 { |
| 97 | compatible = "arm,cortex-a7-gic"; | |
| 98 | interrupt-controller; | |
| 99 | #interrupt-cells = <3>; | |
| c6b3a64f | 100 | interrupt-parent = <&gic>; |
| 4542172e HC |
101 | reg = <0x10211000 0x1000>, |
| 102 | <0x10212000 0x1000>; | |
| 103 | }; | |
| b8be5663 MB |
104 | |
| 105 | uart0: serial@11002000 { | |
| 106 | compatible = "mediatek,mt6577-uart"; | |
| 107 | reg = <0x11002000 0x400>; | |
| 108 | interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_LOW>; | |
| 109 | clocks = <&uart_clk>; | |
| 110 | status = "disabled"; | |
| 111 | }; | |
| 112 | ||
| 113 | uart1: serial@11003000 { | |
| 114 | compatible = "mediatek,mt6577-uart"; | |
| 115 | reg = <0x11003000 0x400>; | |
| 116 | interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_LOW>; | |
| 117 | clocks = <&uart_clk>; | |
| 118 | status = "disabled"; | |
| 119 | }; | |
| 120 | ||
| 121 | uart2: serial@11004000 { | |
| 122 | compatible = "mediatek,mt6577-uart"; | |
| 123 | reg = <0x11004000 0x400>; | |
| 124 | interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_LOW>; | |
| 125 | clocks = <&uart_clk>; | |
| 126 | status = "disabled"; | |
| 127 | }; | |
| 128 | ||
| 129 | uart3: serial@11005000 { | |
| 130 | compatible = "mediatek,mt6577-uart"; | |
| 131 | reg = <0x11005000 0x400>; | |
| 132 | interrupts = <GIC_SPI 54 IRQ_TYPE_LEVEL_LOW>; | |
| 133 | clocks = <&uart_clk>; | |
| 134 | status = "disabled"; | |
| 135 | }; | |
| 4542172e | 136 | }; |