[linux-2.6-block.git] / arch / arm / boot / dts / mt2701.dtsi

/*
 * Copyright (c) 2015 MediaTek Inc.
 * Author: Erin.Lo <erin.lo@mediatek.com>
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License version 2 as
 * published by the Free Software Foundation.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 * GNU General Public License for more details.
 */

#include <dt-bindings/clock/mt2701-clk.h>
#include <dt-bindings/phy/phy.h>
#include <dt-bindings/power/mt2701-power.h>
#include <dt-bindings/interrupt-controller/irq.h>
#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/memory/mt2701-larb-port.h>
#include <dt-bindings/reset/mt2701-resets.h>
#include "skeleton64.dtsi"
#include "mt2701-pinfunc.h"

/ {
	compatible = "mediatek,mt2701";
	interrupt-parent = <&cirq>;

	cpus {
		#address-cells = <1>;
		#size-cells = <0>;
		enable-method = "mediatek,mt81xx-tz-smp";

		cpu@0 {
			device_type = "cpu";
			compatible = "arm,cortex-a7";
			reg = <0x0>;
		};
		cpu@1 {
			device_type = "cpu";
			compatible = "arm,cortex-a7";
			reg = <0x1>;
		};
		cpu@2 {
			device_type = "cpu";
			compatible = "arm,cortex-a7";
			reg = <0x2>;
		};
		cpu@3 {
			device_type = "cpu";
			compatible = "arm,cortex-a7";
			reg = <0x3>;
		};
	};

	reserved-memory {
		#address-cells = <2>;
		#size-cells = <2>;
		ranges;

		trustzone-bootinfo@80002000 {
			compatible = "mediatek,trustzone-bootinfo";
			reg = <0 0x80002000 0 0x1000>;
		};
	};

	system_clk: dummy13m {
		compatible = "fixed-clock";
		clock-frequency = <13000000>;
		#clock-cells = <0>;
	};

	rtc_clk: dummy32k {
		compatible = "fixed-clock";
		clock-frequency = <32000>;
		#clock-cells = <0>;
	};

	clk26m: oscillator@0 {
		compatible = "fixed-clock";
		#clock-cells = <0>;
		clock-frequency = <26000000>;
		clock-output-names = "clk26m";
	};

	rtc32k: oscillator@1 {
		compatible = "fixed-clock";
		#clock-cells = <0>;
		clock-frequency = <32000>;
		clock-output-names = "rtc32k";
	};

	thermal-zones {
		cpu_thermal: cpu_thermal {
			polling-delay-passive = <1000>; /* milliseconds */
			polling-delay = <1000>; /* milliseconds */

			thermal-sensors = <&thermal 0>;
			sustainable-power = <1000>;

			trips {
				threshold: trip-point@0 {
					temperature = <68000>;
					hysteresis = <2000>;
					type = "passive";
				};

				target: trip-point@1 {
					temperature = <85000>;
					hysteresis = <2000>;
					type = "passive";
				};

				cpu_crit: cpu_crit@0 {
					temperature = <115000>;
					hysteresis = <2000>;
					type = "critical";
				};
			};
		};
	};

	timer {
		compatible = "arm,armv7-timer";
		interrupt-parent = <&gic>;
		interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
			     <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
			     <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
			     <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
	};

	topckgen: syscon@10000000 {
		compatible = "mediatek,mt2701-topckgen", "syscon";
		reg = <0 0x10000000 0 0x1000>;
		#clock-cells = <1>;
	};

	infracfg: syscon@10001000 {
		compatible = "mediatek,mt2701-infracfg", "syscon";
		reg = <0 0x10001000 0 0x1000>;
		#clock-cells = <1>;
		#reset-cells = <1>;
	};

	pericfg: syscon@10003000 {
		compatible = "mediatek,mt2701-pericfg", "syscon";
		reg = <0 0x10003000 0 0x1000>;
		#clock-cells = <1>;
		#reset-cells = <1>;
	};

	syscfg_pctl_a: syscfg@10005000 {
		compatible = "mediatek,mt2701-pctl-a-syscfg", "syscon";
		reg = <0 0x10005000 0 0x1000>;
	};

	scpsys: scpsys@10006000 {
		compatible = "mediatek,mt2701-scpsys", "syscon";
		#power-domain-cells = <1>;
		reg = <0 0x10006000 0 0x1000>;
		infracfg = <&infracfg>;
		clocks = <&topckgen CLK_TOP_MM_SEL>,
			 <&topckgen CLK_TOP_MFG_SEL>,
			 <&topckgen CLK_TOP_ETHIF_SEL>;
		clock-names = "mm", "mfg", "ethif";
	};

	watchdog: watchdog@10007000 {
		compatible = "mediatek,mt2701-wdt",
			     "mediatek,mt6589-wdt";
		reg = <0 0x10007000 0 0x100>;
	};

	timer: timer@10008000 {
		compatible = "mediatek,mt2701-timer",
			     "mediatek,mt6577-timer";
		reg = <0 0x10008000 0 0x80>;
		interrupts = <GIC_SPI 112 IRQ_TYPE_LEVEL_LOW>;
		clocks = <&system_clk>, <&rtc_clk>;
		clock-names = "system-clk", "rtc-clk";
	};

	pio: pinctrl@1000b000 {
		compatible = "mediatek,mt2701-pinctrl";
		reg = <0 0x1000b000 0 0x1000>;
		mediatek,pctl-regmap = <&syscfg_pctl_a>;
		pins-are-numbered;
		gpio-controller;
		#gpio-cells = <2>;
		interrupt-controller;
		#interrupt-cells = <2>;
		interrupts = <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>,
			     <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>;
	};

	smi_common: smi@1000c000 {
		compatible = "mediatek,mt2701-smi-common";
		reg = <0 0x1000c000 0 0x1000>;
		clocks = <&infracfg CLK_INFRA_SMI>,
			 <&mmsys CLK_MM_SMI_COMMON>,
			 <&infracfg CLK_INFRA_SMI>;
		clock-names = "apb", "smi", "async";
		power-domains = <&scpsys MT2701_POWER_DOMAIN_DISP>;
	};

	sysirq: interrupt-controller@10200100 {
		compatible = "mediatek,mt2701-sysirq",
			     "mediatek,mt6577-sysirq";
		interrupt-controller;
		#interrupt-cells = <3>;
		interrupt-parent = <&gic>;
		reg = <0 0x10200100 0 0x1c>;
	};

	cirq: interrupt-controller@10204000 {
		compatible = "mediatek,mt2701-cirq",
			     "mediatek,mtk-cirq";
		interrupt-controller;
		#interrupt-cells = <3>;
		interrupt-parent = <&sysirq>;
		reg = <0 0x10204000 0 0x400>;
		mediatek,ext-irq-range = <32 200>;
	};

	iommu: mmsys_iommu@10205000 {
		compatible = "mediatek,mt2701-m4u";
		reg = <0 0x10205000 0 0x1000>;
		interrupts = <GIC_SPI 106 IRQ_TYPE_LEVEL_LOW>;
		clocks = <&infracfg CLK_INFRA_M4U>;
		clock-names = "bclk";
		mediatek,larbs = <&larb0 &larb1 &larb2>;
		#iommu-cells = <1>;
	};

	apmixedsys: syscon@10209000 {
		compatible = "mediatek,mt2701-apmixedsys", "syscon";
		reg = <0 0x10209000 0 0x1000>;
		#clock-cells = <1>;
	};

	gic: interrupt-controller@10211000 {
		compatible = "arm,cortex-a7-gic";
		interrupt-controller;
		#interrupt-cells = <3>;
		interrupt-parent = <&gic>;
		reg = <0 0x10211000 0 0x1000>,
		      <0 0x10212000 0 0x2000>,
		      <0 0x10214000 0 0x2000>,
		      <0 0x10216000 0 0x2000>;
	};

	auxadc: adc@11001000 {
		compatible = "mediatek,mt2701-auxadc";
		reg = <0 0x11001000 0 0x1000>;
		clocks = <&pericfg CLK_PERI_AUXADC>;
		clock-names = "main";
		#io-channel-cells = <1>;
		status = "disabled";
	};

	uart0: serial@11002000 {
		compatible = "mediatek,mt2701-uart",
			     "mediatek,mt6577-uart";
		reg = <0 0x11002000 0 0x400>;
		interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_LOW>;
		clocks = <&pericfg CLK_PERI_UART0_SEL>, <&pericfg CLK_PERI_UART0>;
		clock-names = "baud", "bus";
		status = "disabled";
	};

	uart1: serial@11003000 {
		compatible = "mediatek,mt2701-uart",
			     "mediatek,mt6577-uart";
		reg = <0 0x11003000 0 0x400>;
		interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_LOW>;
		clocks = <&pericfg CLK_PERI_UART1_SEL>, <&pericfg CLK_PERI_UART1>;
		clock-names = "baud", "bus";
		status = "disabled";
	};

	uart2: serial@11004000 {
		compatible = "mediatek,mt2701-uart",
			     "mediatek,mt6577-uart";
		reg = <0 0x11004000 0 0x400>;
		interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_LOW>;
		clocks = <&pericfg CLK_PERI_UART2_SEL>, <&pericfg CLK_PERI_UART2>;
		clock-names = "baud", "bus";
		status = "disabled";
	};

	uart3: serial@11005000 {
		compatible = "mediatek,mt2701-uart",
			     "mediatek,mt6577-uart";
		reg = <0 0x11005000 0 0x400>;
		interrupts = <GIC_SPI 54 IRQ_TYPE_LEVEL_LOW>;
		clocks = <&pericfg CLK_PERI_UART3_SEL>, <&pericfg CLK_PERI_UART3>;
		clock-names = "baud", "bus";
		status = "disabled";
	};

	i2c0: i2c@11007000 {
		compatible = "mediatek,mt2701-i2c",
			     "mediatek,mt6577-i2c";
		reg = <0 0x11007000 0 0x70>,
		      <0 0x11000200 0 0x80>;
		interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_LOW>;
		clock-div = <16>;
		clocks = <&pericfg CLK_PERI_I2C0>, <&pericfg CLK_PERI_AP_DMA>;
		clock-names = "main", "dma";
		#address-cells = <1>;
		#size-cells = <0>;
		status = "disabled";
	};

	i2c1: i2c@11008000 {
		compatible = "mediatek,mt2701-i2c",
			     "mediatek,mt6577-i2c";
		reg = <0 0x11008000 0 0x70>,
		      <0 0x11000280 0 0x80>;
		interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_LOW>;
		clock-div = <16>;
		clocks = <&pericfg CLK_PERI_I2C1>, <&pericfg CLK_PERI_AP_DMA>;
		clock-names = "main", "dma";
		#address-cells = <1>;
		#size-cells = <0>;
		status = "disabled";
	};

	i2c2: i2c@11009000 {
		compatible = "mediatek,mt2701-i2c",
			     "mediatek,mt6577-i2c";
		reg = <0 0x11009000 0 0x70>,
		      <0 0x11000300 0 0x80>;
		interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_LOW>;
		clock-div = <16>;
		clocks = <&pericfg CLK_PERI_I2C2>, <&pericfg CLK_PERI_AP_DMA>;
		clock-names = "main", "dma";
		#address-cells = <1>;
		#size-cells = <0>;
		status = "disabled";
	};

	spi0: spi@1100a000 {
		compatible = "mediatek,mt2701-spi";
		#address-cells = <1>;
		#size-cells = <0>;
		reg = <0 0x1100a000 0 0x100>;
		interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_LOW>;
		clocks = <&topckgen CLK_TOP_SYSPLL3_D2>,
			 <&topckgen CLK_TOP_SPI0_SEL>,
			 <&pericfg CLK_PERI_SPI0>;
		clock-names = "parent-clk", "sel-clk", "spi-clk";
		status = "disabled";
	};

	thermal: thermal@1100b000 {
		#thermal-sensor-cells = <0>;
		compatible = "mediatek,mt2701-thermal";
		reg = <0 0x1100b000 0 0x1000>;
		interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_LOW>;
		clocks = <&pericfg CLK_PERI_THERM>, <&pericfg CLK_PERI_AUXADC>;
		clock-names = "therm", "auxadc";
		resets = <&pericfg MT2701_PERI_THERM_SW_RST>;
		reset-names = "therm";
		mediatek,auxadc = <&auxadc>;
		mediatek,apmixedsys = <&apmixedsys>;
	};

	nandc: nfi@1100d000 {
		compatible = "mediatek,mt2701-nfc";
		reg = <0 0x1100d000 0 0x1000>;
		interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_LOW>;
		clocks = <&pericfg CLK_PERI_NFI>,
			 <&pericfg CLK_PERI_NFI_PAD>;
		clock-names = "nfi_clk", "pad_clk";
		status = "disabled";
		ecc-engine = <&bch>;
		#address-cells = <1>;
		#size-cells = <0>;
	};

	bch: ecc@1100e000 {
		compatible = "mediatek,mt2701-ecc";
		reg = <0 0x1100e000 0 0x1000>;
		interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_LOW>;
		clocks = <&pericfg CLK_PERI_NFI_ECC>;
		clock-names = "nfiecc_clk";
		status = "disabled";
	};

	nor_flash: spi@11014000 {
		compatible = "mediatek,mt2701-nor",
			     "mediatek,mt8173-nor";
		reg = <0 0x11014000 0 0xe0>;
		clocks = <&pericfg CLK_PERI_FLASH>,
			 <&topckgen CLK_TOP_FLASH_SEL>;
		clock-names = "spi", "sf";
		#address-cells = <1>;
		#size-cells = <0>;
		status = "disabled";
	};

	spi1: spi@11016000 {
		compatible = "mediatek,mt2701-spi";
		#address-cells = <1>;
		#size-cells = <0>;
		reg = <0 0x11016000 0 0x100>;
		interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_LOW>;
		clocks = <&topckgen CLK_TOP_SYSPLL3_D2>,
			 <&topckgen CLK_TOP_SPI1_SEL>,
			 <&pericfg CLK_PERI_SPI1>;
		clock-names = "parent-clk", "sel-clk", "spi-clk";
		status = "disabled";
	};

	spi2: spi@11017000 {
		compatible = "mediatek,mt2701-spi";
		#address-cells = <1>;
		#size-cells = <0>;
		reg = <0 0x11017000 0 0x1000>;
		interrupts = <GIC_SPI 142 IRQ_TYPE_LEVEL_LOW>;
		clocks = <&topckgen CLK_TOP_SYSPLL3_D2>,
			 <&topckgen CLK_TOP_SPI2_SEL>,
			 <&pericfg CLK_PERI_SPI2>;
		clock-names = "parent-clk", "sel-clk", "spi-clk";
		status = "disabled";
	};

	afe: audio-controller@11220000 {
		compatible = "mediatek,mt2701-audio";
		reg = <0 0x11220000 0 0x2000>,
		      <0 0x112a0000 0 0x20000>;
		interrupts = <GIC_SPI 132 IRQ_TYPE_LEVEL_LOW>;
		power-domains = <&scpsys MT2701_POWER_DOMAIN_IFR_MSC>;

		clocks = <&infracfg CLK_INFRA_AUDIO>,
			 <&topckgen CLK_TOP_AUD_MUX1_SEL>,
			 <&topckgen CLK_TOP_AUD_MUX2_SEL>,
			 <&topckgen CLK_TOP_AUD_MUX1_DIV>,
			 <&topckgen CLK_TOP_AUD_MUX2_DIV>,
			 <&topckgen CLK_TOP_AUD_48K_TIMING>,
			 <&topckgen CLK_TOP_AUD_44K_TIMING>,
			 <&topckgen CLK_TOP_AUDPLL_MUX_SEL>,
			 <&topckgen CLK_TOP_APLL_SEL>,
			 <&topckgen CLK_TOP_AUD1PLL_98M>,
			 <&topckgen CLK_TOP_AUD2PLL_90M>,
			 <&topckgen CLK_TOP_HADDS2PLL_98M>,
			 <&topckgen CLK_TOP_HADDS2PLL_294M>,
			 <&topckgen CLK_TOP_AUDPLL>,
			 <&topckgen CLK_TOP_AUDPLL_D4>,
			 <&topckgen CLK_TOP_AUDPLL_D8>,
			 <&topckgen CLK_TOP_AUDPLL_D16>,
			 <&topckgen CLK_TOP_AUDPLL_D24>,
			 <&topckgen CLK_TOP_AUDINTBUS_SEL>,
			 <&clk26m>,
			 <&topckgen CLK_TOP_SYSPLL1_D4>,
			 <&topckgen CLK_TOP_AUD_K1_SRC_SEL>,
			 <&topckgen CLK_TOP_AUD_K2_SRC_SEL>,
			 <&topckgen CLK_TOP_AUD_K3_SRC_SEL>,
			 <&topckgen CLK_TOP_AUD_K4_SRC_SEL>,
			 <&topckgen CLK_TOP_AUD_K5_SRC_SEL>,
			 <&topckgen CLK_TOP_AUD_K6_SRC_SEL>,
			 <&topckgen CLK_TOP_AUD_K1_SRC_DIV>,
			 <&topckgen CLK_TOP_AUD_K2_SRC_DIV>,
			 <&topckgen CLK_TOP_AUD_K3_SRC_DIV>,
			 <&topckgen CLK_TOP_AUD_K4_SRC_DIV>,
			 <&topckgen CLK_TOP_AUD_K5_SRC_DIV>,
			 <&topckgen CLK_TOP_AUD_K6_SRC_DIV>,
			 <&topckgen CLK_TOP_AUD_I2S1_MCLK>,
			 <&topckgen CLK_TOP_AUD_I2S2_MCLK>,
			 <&topckgen CLK_TOP_AUD_I2S3_MCLK>,
			 <&topckgen CLK_TOP_AUD_I2S4_MCLK>,
			 <&topckgen CLK_TOP_AUD_I2S5_MCLK>,
			 <&topckgen CLK_TOP_AUD_I2S6_MCLK>,
			 <&topckgen CLK_TOP_ASM_M_SEL>,
			 <&topckgen CLK_TOP_ASM_H_SEL>,
			 <&topckgen CLK_TOP_UNIVPLL2_D4>,
			 <&topckgen CLK_TOP_UNIVPLL2_D2>,
			 <&topckgen CLK_TOP_SYSPLL_D5>;

		clock-names = "infra_sys_audio_clk",
			 "top_audio_mux1_sel",
			 "top_audio_mux2_sel",
			 "top_audio_mux1_div",
			 "top_audio_mux2_div",
			 "top_audio_48k_timing",
			 "top_audio_44k_timing",
			 "top_audpll_mux_sel",
			 "top_apll_sel",
			 "top_aud1_pll_98M",
			 "top_aud2_pll_90M",
			 "top_hadds2_pll_98M",
			 "top_hadds2_pll_294M",
			 "top_audpll",
			 "top_audpll_d4",
			 "top_audpll_d8",
			 "top_audpll_d16",
			 "top_audpll_d24",
			 "top_audintbus_sel",
			 "clk_26m",
			 "top_syspll1_d4",
			 "top_aud_k1_src_sel",
			 "top_aud_k2_src_sel",
			 "top_aud_k3_src_sel",
			 "top_aud_k4_src_sel",
			 "top_aud_k5_src_sel",
			 "top_aud_k6_src_sel",
			 "top_aud_k1_src_div",
			 "top_aud_k2_src_div",
			 "top_aud_k3_src_div",
			 "top_aud_k4_src_div",
			 "top_aud_k5_src_div",
			 "top_aud_k6_src_div",
			 "top_aud_i2s1_mclk",
			 "top_aud_i2s2_mclk",
			 "top_aud_i2s3_mclk",
			 "top_aud_i2s4_mclk",
			 "top_aud_i2s5_mclk",
			 "top_aud_i2s6_mclk",
			 "top_asm_m_sel",
			 "top_asm_h_sel",
			 "top_univpll2_d4",
			 "top_univpll2_d2",
			 "top_syspll_d5";
	};

	mmsys: syscon@14000000 {
		compatible = "mediatek,mt2701-mmsys", "syscon";
		reg = <0 0x14000000 0 0x1000>;
		#clock-cells = <1>;
	};

	larb0: larb@14010000 {
		compatible = "mediatek,mt2701-smi-larb";
		reg = <0 0x14010000 0 0x1000>;
		mediatek,smi = <&smi_common>;
		mediatek,larb-id = <0>;
		clocks = <&mmsys CLK_MM_SMI_LARB0>,
			 <&mmsys CLK_MM_SMI_LARB0>;
		clock-names = "apb", "smi";
		power-domains = <&scpsys MT2701_POWER_DOMAIN_DISP>;
	};

	imgsys: syscon@15000000 {
		compatible = "mediatek,mt2701-imgsys", "syscon";
		reg = <0 0x15000000 0 0x1000>;
		#clock-cells = <1>;
	};

	larb2: larb@15001000 {
		compatible = "mediatek,mt2701-smi-larb";
		reg = <0 0x15001000 0 0x1000>;
		mediatek,smi = <&smi_common>;
		mediatek,larb-id = <2>;
		clocks = <&imgsys CLK_IMG_SMI_COMM>,
			 <&imgsys CLK_IMG_SMI_COMM>;
		clock-names = "apb", "smi";
		power-domains = <&scpsys MT2701_POWER_DOMAIN_ISP>;
	};

	jpegdec: jpegdec@15004000 {
		compatible = "mediatek,mt2701-jpgdec";
		reg = <0 0x15004000 0 0x1000>;
		interrupts = <GIC_SPI 143 IRQ_TYPE_LEVEL_LOW>;
		clocks =  <&imgsys CLK_IMG_JPGDEC_SMI>,
			  <&imgsys CLK_IMG_JPGDEC>;
		clock-names = "jpgdec-smi",
			      "jpgdec";
		power-domains = <&scpsys MT2701_POWER_DOMAIN_ISP>;
		mediatek,larb = <&larb2>;
		iommus = <&iommu MT2701_M4U_PORT_JPGDEC_WDMA>,
			 <&iommu MT2701_M4U_PORT_JPGDEC_BSDMA>;
	};

	vdecsys: syscon@16000000 {
		compatible = "mediatek,mt2701-vdecsys", "syscon";
		reg = <0 0x16000000 0 0x1000>;
		#clock-cells = <1>;
	};

	larb1: larb@16010000 {
		compatible = "mediatek,mt2701-smi-larb";
		reg = <0 0x16010000 0 0x1000>;
		mediatek,smi = <&smi_common>;
		mediatek,larb-id = <1>;
		clocks = <&vdecsys CLK_VDEC_CKGEN>,
			 <&vdecsys CLK_VDEC_LARB>;
		clock-names = "apb", "smi";
		power-domains = <&scpsys MT2701_POWER_DOMAIN_VDEC>;
	};

	hifsys: syscon@1a000000 {
		compatible = "mediatek,mt2701-hifsys", "syscon";
		reg = <0 0x1a000000 0 0x1000>;
		#clock-cells = <1>;
	};

	usb0: usb@1a1c0000 {
		compatible = "mediatek,mt8173-xhci";
		reg = <0 0x1a1c0000 0 0x1000>,
		      <0 0x1a1c4700 0 0x0100>;
		reg-names = "mac", "ippc";
		interrupts = <GIC_SPI 196 IRQ_TYPE_LEVEL_LOW>;
		clocks = <&hifsys CLK_HIFSYS_USB0PHY>,
			 <&topckgen CLK_TOP_ETHIF_SEL>;
		clock-names = "sys_ck", "ref_ck";
		power-domains = <&scpsys MT2701_POWER_DOMAIN_HIF>;
		phys = <&u2port0 PHY_TYPE_USB2>, <&u3port0 PHY_TYPE_USB3>;
		status = "disabled";
	};

	u3phy0: usb-phy@1a1c4000 {
		compatible = "mediatek,mt2701-u3phy";
		reg = <0 0x1a1c4000 0 0x0700>;
		#address-cells = <2>;
		#size-cells = <2>;
		ranges;
		status = "disabled";

		u2port0: usb-phy@1a1c4800 {
			reg = <0 0x1a1c4800 0 0x0100>;
			clocks = <&topckgen CLK_TOP_USB_PHY48M>;
			clock-names = "ref";
			#phy-cells = <1>;
			status = "okay";
		};

		u3port0: usb-phy@1a1c4900 {
			reg = <0 0x1a1c4900 0 0x0700>;
			clocks = <&clk26m>;
			clock-names = "ref";
			#phy-cells = <1>;
			status = "okay";
		};
	};

	usb1: usb@1a240000 {
		compatible = "mediatek,mt8173-xhci";
		reg = <0 0x1a240000 0 0x1000>,
		      <0 0x1a244700 0 0x0100>;
		reg-names = "mac", "ippc";
		interrupts = <GIC_SPI 197 IRQ_TYPE_LEVEL_LOW>;
		clocks = <&hifsys CLK_HIFSYS_USB1PHY>,
			 <&topckgen CLK_TOP_ETHIF_SEL>;
		clock-names = "sys_ck", "ref_ck";
		power-domains = <&scpsys MT2701_POWER_DOMAIN_HIF>;
		phys = <&u2port1 PHY_TYPE_USB2>, <&u3port1 PHY_TYPE_USB3>;
		status = "disabled";
	};

	u3phy1: usb-phy@1a244000 {
		compatible = "mediatek,mt2701-u3phy";
		reg = <0 0x1a244000 0 0x0700>;
		#address-cells = <2>;
		#size-cells = <2>;
		ranges;
		status = "disabled";

		u2port1: usb-phy@1a244800 {
			reg = <0 0x1a244800 0 0x0100>;
			clocks = <&topckgen CLK_TOP_USB_PHY48M>;
			clock-names = "ref";
			#phy-cells = <1>;
			status = "okay";
		};

		u3port1: usb-phy@1a244900 {
			reg = <0 0x1a244900 0 0x0700>;
			clocks = <&clk26m>;
			clock-names = "ref";
			#phy-cells = <1>;
			status = "okay";
		};
	};

	ethsys: syscon@1b000000 {
		compatible = "mediatek,mt2701-ethsys", "syscon";
		reg = <0 0x1b000000 0 0x1000>;
		#clock-cells = <1>;
	};

	eth: ethernet@1b100000 {
		compatible = "mediatek,mt2701-eth", "syscon";
		reg = <0 0x1b100000 0 0x20000>;
		interrupts = <GIC_SPI 200 IRQ_TYPE_LEVEL_LOW>,
			     <GIC_SPI 199 IRQ_TYPE_LEVEL_LOW>,
			     <GIC_SPI 198 IRQ_TYPE_LEVEL_LOW>;
		clocks = <&topckgen CLK_TOP_ETHIF_SEL>,
			 <&ethsys CLK_ETHSYS_ESW>,
			 <&ethsys CLK_ETHSYS_GP1>,
			 <&ethsys CLK_ETHSYS_GP2>,
			 <&apmixedsys CLK_APMIXED_TRGPLL>;
		clock-names = "ethif", "esw", "gp1", "gp2", "trgpll";
		resets = <&ethsys MT2701_ETHSYS_FE_RST>,
			 <&ethsys MT2701_ETHSYS_GMAC_RST>,
			 <&ethsys MT2701_ETHSYS_PPE_RST>;
		reset-names = "fe", "gmac", "ppe";
		power-domains = <&scpsys MT2701_POWER_DOMAIN_ETH>;
		mediatek,ethsys = <&ethsys>;
		mediatek,pctl = <&syscfg_pctl_a>;
		#address-cells = <1>;
		#size-cells = <0>;
		status = "disabled";
	};

	bdpsys: syscon@1c000000 {
		compatible = "mediatek,mt2701-bdpsys", "syscon";
		reg = <0 0x1c000000 0 0x1000>;
		#clock-cells = <1>;
	};
};
Commit	Line	Data
74d25721 EL	1	/*
	2	* Copyright (c) 2015 MediaTek Inc.
	3	* Author: Erin.Lo <erin.lo@mediatek.com>
	4	*
	5	* This program is free software; you can redistribute it and/or modify
	6	* it under the terms of the GNU General Public License version 2 as
	7	* published by the Free Software Foundation.
	8	*
	9	* This program is distributed in the hope that it will be useful,
	10	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	11	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	12	* GNU General Public License for more details.
	13	*/
	14
adf6eb77	15	#include <dt-bindings/clock/mt2701-clk.h>
295ad9fb	16	#include <dt-bindings/phy/phy.h>
9f3746af	17	#include <dt-bindings/power/mt2701-power.h>
74d25721 EL	18	#include <dt-bindings/interrupt-controller/irq.h>
74d25721 EL	19	#include <dt-bindings/interrupt-controller/arm-gic.h>
c56ee526	20	#include <dt-bindings/memory/mt2701-larb-port.h>
adf6eb77	21	#include <dt-bindings/reset/mt2701-resets.h>
74d25721	22	#include "skeleton64.dtsi"
8369337e	23	#include "mt2701-pinfunc.h"
74d25721 EL	24
	25	/ {
	26	compatible = "mediatek,mt2701";
1b813f3c	27	interrupt-parent = <&cirq>;
74d25721 EL	28
	29	cpus {
	30	#address-cells = <1>;
	31	#size-cells = <0>;
dfb89528	32	enable-method = "mediatek,mt81xx-tz-smp";
74d25721 EL	33
	34	cpu@0 {
	35	device_type = "cpu";
	36	compatible = "arm,cortex-a7";
	37	reg = <0x0>;
	38	};
	39	cpu@1 {
	40	device_type = "cpu";
	41	compatible = "arm,cortex-a7";
	42	reg = <0x1>;
	43	};
	44	cpu@2 {
	45	device_type = "cpu";
	46	compatible = "arm,cortex-a7";
	47	reg = <0x2>;
	48	};
	49	cpu@3 {
	50	device_type = "cpu";
	51	compatible = "arm,cortex-a7";
	52	reg = <0x3>;
	53	};
	54	};
	55
dfb89528 LY	56	reserved-memory {
	57	#address-cells = <2>;
	58	#size-cells = <2>;
	59	ranges;
	60
	61	trustzone-bootinfo@80002000 {
	62	compatible = "mediatek,trustzone-bootinfo";
	63	reg = <0 0x80002000 0 0x1000>;
	64	};
	65	};
	66
74d25721 EL	67	system_clk: dummy13m {
	68	compatible = "fixed-clock";
	69	clock-frequency = <13000000>;
	70	#clock-cells = <0>;
	71	};
	72
	73	rtc_clk: dummy32k {
	74	compatible = "fixed-clock";
	75	clock-frequency = <32000>;
	76	#clock-cells = <0>;
	77	};
	78
adf6eb77 JL	79	clk26m: oscillator@0 {
	80	compatible = "fixed-clock";
	81	#clock-cells = <0>;
	82	clock-frequency = <26000000>;
	83	clock-output-names = "clk26m";
	84	};
	85
	86	rtc32k: oscillator@1 {
	87	compatible = "fixed-clock";
	88	#clock-cells = <0>;
	89	clock-frequency = <32000>;
	90	clock-output-names = "rtc32k";
	91	};
	92
e348dc74 DC	93	thermal-zones {
	94	cpu_thermal: cpu_thermal {
	95	polling-delay-passive = <1000>; /* milliseconds */
	96	polling-delay = <1000>; /* milliseconds */
	97
	98	thermal-sensors = <&thermal 0>;
	99	sustainable-power = <1000>;
	100
	101	trips {
	102	threshold: trip-point@0 {
	103	temperature = <68000>;
	104	hysteresis = <2000>;
	105	type = "passive";
	106	};
	107
	108	target: trip-point@1 {
	109	temperature = <85000>;
	110	hysteresis = <2000>;
	111	type = "passive";
	112	};
	113
	114	cpu_crit: cpu_crit@0 {
	115	temperature = <115000>;
	116	hysteresis = <2000>;
	117	type = "critical";
	118	};
	119	};
	120	};
	121	};
	122
74d25721 EL	123	timer {
	124	compatible = "arm,armv7-timer";
	125	interrupt-parent = <&gic>;
	126	interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) \| IRQ_TYPE_LEVEL_HIGH)>,
	127	<GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) \| IRQ_TYPE_LEVEL_HIGH)>,
	128	<GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) \| IRQ_TYPE_LEVEL_HIGH)>,
	129	<GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) \| IRQ_TYPE_LEVEL_HIGH)>;
	130	};
	131
adf6eb77 JL	132	topckgen: syscon@10000000 {
	133	compatible = "mediatek,mt2701-topckgen", "syscon";
	134	reg = <0 0x10000000 0 0x1000>;
	135	#clock-cells = <1>;
	136	};
	137
	138	infracfg: syscon@10001000 {
	139	compatible = "mediatek,mt2701-infracfg", "syscon";
	140	reg = <0 0x10001000 0 0x1000>;
	141	#clock-cells = <1>;
	142	#reset-cells = <1>;
	143	};
	144
	145	pericfg: syscon@10003000 {
	146	compatible = "mediatek,mt2701-pericfg", "syscon";
	147	reg = <0 0x10003000 0 0x1000>;
	148	#clock-cells = <1>;
	149	#reset-cells = <1>;
	150	};
	151
42e4d6d5 JL	152	syscfg_pctl_a: syscfg@10005000 {
	153	compatible = "mediatek,mt2701-pctl-a-syscfg", "syscon";
	154	reg = <0 0x10005000 0 0x1000>;
	155	};
	156
9f3746af JL	157	scpsys: scpsys@10006000 {
	158	compatible = "mediatek,mt2701-scpsys", "syscon";
	159	#power-domain-cells = <1>;
	160	reg = <0 0x10006000 0 0x1000>;
	161	infracfg = <&infracfg>;
	162	clocks = <&topckgen CLK_TOP_MM_SEL>,
	163	<&topckgen CLK_TOP_MFG_SEL>,
	164	<&topckgen CLK_TOP_ETHIF_SEL>;
	165	clock-names = "mm", "mfg", "ethif";
	166	};
	167
74d25721 EL	168	watchdog: watchdog@10007000 {
	169	compatible = "mediatek,mt2701-wdt",
	170	"mediatek,mt6589-wdt";
	171	reg = <0 0x10007000 0 0x100>;
	172	};
	173
	174	timer: timer@10008000 {
	175	compatible = "mediatek,mt2701-timer",
	176	"mediatek,mt6577-timer";
	177	reg = <0 0x10008000 0 0x80>;
	178	interrupts = <GIC_SPI 112 IRQ_TYPE_LEVEL_LOW>;
	179	clocks = <&system_clk>, <&rtc_clk>;
	180	clock-names = "system-clk", "rtc-clk";
	181	};
	182
42e4d6d5 JL	183	pio: pinctrl@1000b000 {
	184	compatible = "mediatek,mt2701-pinctrl";
	185	reg = <0 0x1000b000 0 0x1000>;
	186	mediatek,pctl-regmap = <&syscfg_pctl_a>;
	187	pins-are-numbered;
	188	gpio-controller;
	189	#gpio-cells = <2>;
	190	interrupt-controller;
	191	#interrupt-cells = <2>;
	192	interrupts = <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>,
	193	<GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>;
	194	};
	195
f3cba0f4 HZ	196	smi_common: smi@1000c000 {
	197	compatible = "mediatek,mt2701-smi-common";
	198	reg = <0 0x1000c000 0 0x1000>;
	199	clocks = <&infracfg CLK_INFRA_SMI>,
	200	<&mmsys CLK_MM_SMI_COMMON>,
	201	<&infracfg CLK_INFRA_SMI>;
	202	clock-names = "apb", "smi", "async";
	203	power-domains = <&scpsys MT2701_POWER_DOMAIN_DISP>;
	204	};
	205
74d25721 EL	206	sysirq: interrupt-controller@10200100 {
	207	compatible = "mediatek,mt2701-sysirq",
	208	"mediatek,mt6577-sysirq";
	209	interrupt-controller;
	210	#interrupt-cells = <3>;
	211	interrupt-parent = <&gic>;
	212	reg = <0 0x10200100 0 0x1c>;
	213	};
	214
1b813f3c YP	215	cirq: interrupt-controller@10204000 {
	216	compatible = "mediatek,mt2701-cirq",
	217	"mediatek,mtk-cirq";
	218	interrupt-controller;
	219	#interrupt-cells = <3>;
	220	interrupt-parent = <&sysirq>;
	221	reg = <0 0x10204000 0 0x400>;
	222	mediatek,ext-irq-range = <32 200>;
	223	};
	224
f3cba0f4 HZ	225	iommu: mmsys_iommu@10205000 {
	226	compatible = "mediatek,mt2701-m4u";
	227	reg = <0 0x10205000 0 0x1000>;
	228	interrupts = <GIC_SPI 106 IRQ_TYPE_LEVEL_LOW>;
	229	clocks = <&infracfg CLK_INFRA_M4U>;
	230	clock-names = "bclk";
	231	mediatek,larbs = <&larb0 &larb1 &larb2>;
	232	#iommu-cells = <1>;
	233	};
	234
adf6eb77 JL	235	apmixedsys: syscon@10209000 {
	236	compatible = "mediatek,mt2701-apmixedsys", "syscon";
	237	reg = <0 0x10209000 0 0x1000>;
	238	#clock-cells = <1>;
	239	};
	240
74d25721 EL	241	gic: interrupt-controller@10211000 {
	242	compatible = "arm,cortex-a7-gic";
	243	interrupt-controller;
	244	#interrupt-cells = <3>;
	245	interrupt-parent = <&gic>;
	246	reg = <0 0x10211000 0 0x1000>,
387720c9	247	<0 0x10212000 0 0x2000>,
74d25721 EL	248	<0 0x10214000 0 0x2000>,
	249	<0 0x10216000 0 0x2000>;
	250	};
	251
301501d3 ZT	252	auxadc: adc@11001000 {
	253	compatible = "mediatek,mt2701-auxadc";
	254	reg = <0 0x11001000 0 0x1000>;
	255	clocks = <&pericfg CLK_PERI_AUXADC>;
	256	clock-names = "main";
	257	#io-channel-cells = <1>;
	258	status = "disabled";
	259	};
	260
74d25721 EL	261	uart0: serial@11002000 {
	262	compatible = "mediatek,mt2701-uart",
	263	"mediatek,mt6577-uart";
	264	reg = <0 0x11002000 0 0x400>;
	265	interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_LOW>;
28d6e364 EL	266	clocks = <&pericfg CLK_PERI_UART0_SEL>, <&pericfg CLK_PERI_UART0>;
28d6e364 EL	267	clock-names = "baud", "bus";
74d25721 EL	268	status = "disabled";
	269	};
	270
	271	uart1: serial@11003000 {
	272	compatible = "mediatek,mt2701-uart",
	273	"mediatek,mt6577-uart";
	274	reg = <0 0x11003000 0 0x400>;
	275	interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_LOW>;
28d6e364 EL	276	clocks = <&pericfg CLK_PERI_UART1_SEL>, <&pericfg CLK_PERI_UART1>;
28d6e364 EL	277	clock-names = "baud", "bus";
74d25721 EL	278	status = "disabled";
	279	};
	280
	281	uart2: serial@11004000 {
	282	compatible = "mediatek,mt2701-uart",
	283	"mediatek,mt6577-uart";
	284	reg = <0 0x11004000 0 0x400>;
	285	interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_LOW>;
28d6e364 EL	286	clocks = <&pericfg CLK_PERI_UART2_SEL>, <&pericfg CLK_PERI_UART2>;
28d6e364 EL	287	clock-names = "baud", "bus";
74d25721 EL	288	status = "disabled";
	289	};
	290
	291	uart3: serial@11005000 {
	292	compatible = "mediatek,mt2701-uart",
	293	"mediatek,mt6577-uart";
	294	reg = <0 0x11005000 0 0x400>;
	295	interrupts = <GIC_SPI 54 IRQ_TYPE_LEVEL_LOW>;
28d6e364 EL	296	clocks = <&pericfg CLK_PERI_UART3_SEL>, <&pericfg CLK_PERI_UART3>;
28d6e364 EL	297	clock-names = "baud", "bus";
74d25721 EL	298	status = "disabled";
74d25721 EL	299	};
f235c7e7	300
729b7f8d JG	301	i2c0: i2c@11007000 {
	302	compatible = "mediatek,mt2701-i2c",
	303	"mediatek,mt6577-i2c";
	304	reg = <0 0x11007000 0 0x70>,
	305	<0 0x11000200 0 0x80>;
	306	interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_LOW>;
	307	clock-div = <16>;
	308	clocks = <&pericfg CLK_PERI_I2C0>, <&pericfg CLK_PERI_AP_DMA>;
	309	clock-names = "main", "dma";
	310	#address-cells = <1>;
	311	#size-cells = <0>;
	312	status = "disabled";
	313	};
	314
	315	i2c1: i2c@11008000 {
	316	compatible = "mediatek,mt2701-i2c",
	317	"mediatek,mt6577-i2c";
	318	reg = <0 0x11008000 0 0x70>,
	319	<0 0x11000280 0 0x80>;
	320	interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_LOW>;
	321	clock-div = <16>;
	322	clocks = <&pericfg CLK_PERI_I2C1>, <&pericfg CLK_PERI_AP_DMA>;
	323	clock-names = "main", "dma";
	324	#address-cells = <1>;
	325	#size-cells = <0>;
	326	status = "disabled";
	327	};
	328
	329	i2c2: i2c@11009000 {
	330	compatible = "mediatek,mt2701-i2c",
	331	"mediatek,mt6577-i2c";
	332	reg = <0 0x11009000 0 0x70>,
	333	<0 0x11000300 0 0x80>;
	334	interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_LOW>;
	335	clock-div = <16>;
	336	clocks = <&pericfg CLK_PERI_I2C2>, <&pericfg CLK_PERI_AP_DMA>;
	337	clock-names = "main", "dma";
	338	#address-cells = <1>;
	339	#size-cells = <0>;
	340	status = "disabled";
	341	};
	342
159f5ae7 LL	343	spi0: spi@1100a000 {
	344	compatible = "mediatek,mt2701-spi";
	345	#address-cells = <1>;
	346	#size-cells = <0>;
	347	reg = <0 0x1100a000 0 0x100>;
	348	interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_LOW>;
	349	clocks = <&topckgen CLK_TOP_SYSPLL3_D2>,
	350	<&topckgen CLK_TOP_SPI0_SEL>,
	351	<&pericfg CLK_PERI_SPI0>;
	352	clock-names = "parent-clk", "sel-clk", "spi-clk";
	353	status = "disabled";
	354	};
	355
e348dc74 DC	356	thermal: thermal@1100b000 {
	357	#thermal-sensor-cells = <0>;
	358	compatible = "mediatek,mt2701-thermal";
	359	reg = <0 0x1100b000 0 0x1000>;
	360	interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_LOW>;
	361	clocks = <&pericfg CLK_PERI_THERM>, <&pericfg CLK_PERI_AUXADC>;
	362	clock-names = "therm", "auxadc";
	363	resets = <&pericfg MT2701_PERI_THERM_SW_RST>;
	364	reset-names = "therm";
	365	mediatek,auxadc = <&auxadc>;
	366	mediatek,apmixedsys = <&apmixedsys>;
	367	};
	368
111758b7 XL	369	nandc: nfi@1100d000 {
	370	compatible = "mediatek,mt2701-nfc";
	371	reg = <0 0x1100d000 0 0x1000>;
	372	interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_LOW>;
	373	clocks = <&pericfg CLK_PERI_NFI>,
	374	<&pericfg CLK_PERI_NFI_PAD>;
	375	clock-names = "nfi_clk", "pad_clk";
	376	status = "disabled";
	377	ecc-engine = <&bch>;
	378	#address-cells = <1>;
	379	#size-cells = <0>;
	380	};
	381
	382	bch: ecc@1100e000 {
	383	compatible = "mediatek,mt2701-ecc";
	384	reg = <0 0x1100e000 0 0x1000>;
	385	interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_LOW>;
	386	clocks = <&pericfg CLK_PERI_NFI_ECC>;
	387	clock-names = "nfiecc_clk";
	388	status = "disabled";
	389	};
	390
df3074f0 GM	391	nor_flash: spi@11014000 {
	392	compatible = "mediatek,mt2701-nor",
	393	"mediatek,mt8173-nor";
	394	reg = <0 0x11014000 0 0xe0>;
	395	clocks = <&pericfg CLK_PERI_FLASH>,
	396	<&topckgen CLK_TOP_FLASH_SEL>;
	397	clock-names = "spi", "sf";
	398	#address-cells = <1>;
	399	#size-cells = <0>;
	400	status = "disabled";
	401	};
	402
159f5ae7 LL	403	spi1: spi@11016000 {
	404	compatible = "mediatek,mt2701-spi";
	405	#address-cells = <1>;
	406	#size-cells = <0>;
	407	reg = <0 0x11016000 0 0x100>;
	408	interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_LOW>;
	409	clocks = <&topckgen CLK_TOP_SYSPLL3_D2>,
	410	<&topckgen CLK_TOP_SPI1_SEL>,
	411	<&pericfg CLK_PERI_SPI1>;
	412	clock-names = "parent-clk", "sel-clk", "spi-clk";
	413	status = "disabled";
	414	};
	415
	416	spi2: spi@11017000 {
	417	compatible = "mediatek,mt2701-spi";
	418	#address-cells = <1>;
	419	#size-cells = <0>;
	420	reg = <0 0x11017000 0 0x1000>;
	421	interrupts = <GIC_SPI 142 IRQ_TYPE_LEVEL_LOW>;
	422	clocks = <&topckgen CLK_TOP_SYSPLL3_D2>,
	423	<&topckgen CLK_TOP_SPI2_SEL>,
	424	<&pericfg CLK_PERI_SPI2>;
	425	clock-names = "parent-clk", "sel-clk", "spi-clk";
	426	status = "disabled";
	427	};
	428
aac5e972 GT	429	afe: audio-controller@11220000 {
	430	compatible = "mediatek,mt2701-audio";
	431	reg = <0 0x11220000 0 0x2000>,
	432	<0 0x112a0000 0 0x20000>;
	433	interrupts = <GIC_SPI 132 IRQ_TYPE_LEVEL_LOW>;
	434	power-domains = <&scpsys MT2701_POWER_DOMAIN_IFR_MSC>;
	435
	436	clocks = <&infracfg CLK_INFRA_AUDIO>,
	437	<&topckgen CLK_TOP_AUD_MUX1_SEL>,
	438	<&topckgen CLK_TOP_AUD_MUX2_SEL>,
	439	<&topckgen CLK_TOP_AUD_MUX1_DIV>,
	440	<&topckgen CLK_TOP_AUD_MUX2_DIV>,
	441	<&topckgen CLK_TOP_AUD_48K_TIMING>,
	442	<&topckgen CLK_TOP_AUD_44K_TIMING>,
	443	<&topckgen CLK_TOP_AUDPLL_MUX_SEL>,
	444	<&topckgen CLK_TOP_APLL_SEL>,
	445	<&topckgen CLK_TOP_AUD1PLL_98M>,
	446	<&topckgen CLK_TOP_AUD2PLL_90M>,
	447	<&topckgen CLK_TOP_HADDS2PLL_98M>,
	448	<&topckgen CLK_TOP_HADDS2PLL_294M>,
	449	<&topckgen CLK_TOP_AUDPLL>,
	450	<&topckgen CLK_TOP_AUDPLL_D4>,
	451	<&topckgen CLK_TOP_AUDPLL_D8>,
	452	<&topckgen CLK_TOP_AUDPLL_D16>,
	453	<&topckgen CLK_TOP_AUDPLL_D24>,
	454	<&topckgen CLK_TOP_AUDINTBUS_SEL>,
	455	<&clk26m>,
	456	<&topckgen CLK_TOP_SYSPLL1_D4>,
	457	<&topckgen CLK_TOP_AUD_K1_SRC_SEL>,
	458	<&topckgen CLK_TOP_AUD_K2_SRC_SEL>,
	459	<&topckgen CLK_TOP_AUD_K3_SRC_SEL>,
	460	<&topckgen CLK_TOP_AUD_K4_SRC_SEL>,
	461	<&topckgen CLK_TOP_AUD_K5_SRC_SEL>,
	462	<&topckgen CLK_TOP_AUD_K6_SRC_SEL>,
	463	<&topckgen CLK_TOP_AUD_K1_SRC_DIV>,
	464	<&topckgen CLK_TOP_AUD_K2_SRC_DIV>,
	465	<&topckgen CLK_TOP_AUD_K3_SRC_DIV>,
	466	<&topckgen CLK_TOP_AUD_K4_SRC_DIV>,
	467	<&topckgen CLK_TOP_AUD_K5_SRC_DIV>,
	468	<&topckgen CLK_TOP_AUD_K6_SRC_DIV>,
	469	<&topckgen CLK_TOP_AUD_I2S1_MCLK>,
	470	<&topckgen CLK_TOP_AUD_I2S2_MCLK>,
	471	<&topckgen CLK_TOP_AUD_I2S3_MCLK>,
	472	<&topckgen CLK_TOP_AUD_I2S4_MCLK>,
	473	<&topckgen CLK_TOP_AUD_I2S5_MCLK>,
	474	<&topckgen CLK_TOP_AUD_I2S6_MCLK>,
	475	<&topckgen CLK_TOP_ASM_M_SEL>,
	476	<&topckgen CLK_TOP_ASM_H_SEL>,
	477	<&topckgen CLK_TOP_UNIVPLL2_D4>,
	478	<&topckgen CLK_TOP_UNIVPLL2_D2>,
	479	<&topckgen CLK_TOP_SYSPLL_D5>;
	480
	481	clock-names = "infra_sys_audio_clk",
	482	"top_audio_mux1_sel",
	483	"top_audio_mux2_sel",
	484	"top_audio_mux1_div",
	485	"top_audio_mux2_div",
	486	"top_audio_48k_timing",
	487	"top_audio_44k_timing",
	488	"top_audpll_mux_sel",
	489	"top_apll_sel",
	490	"top_aud1_pll_98M",
	491	"top_aud2_pll_90M",
	492	"top_hadds2_pll_98M",
493	"top_hadds2_pll_294M",
494	"top_audpll",
495	"top_audpll_d4",
496	"top_audpll_d8",
497	"top_audpll_d16",
498	"top_audpll_d24",
499	"top_audintbus_sel",
500	"clk_26m",
501	"top_syspll1_d4",
502	"top_aud_k1_src_sel",
503	"top_aud_k2_src_sel",
504	"top_aud_k3_src_sel",
505	"top_aud_k4_src_sel",
506	"top_aud_k5_src_sel",
507	"top_aud_k6_src_sel",
508	"top_aud_k1_src_div",
509	"top_aud_k2_src_div",
510	"top_aud_k3_src_div",
511	"top_aud_k4_src_div",
512	"top_aud_k5_src_div",
513	"top_aud_k6_src_div",
514	"top_aud_i2s1_mclk",
515	"top_aud_i2s2_mclk",
516	"top_aud_i2s3_mclk",
517	"top_aud_i2s4_mclk",
518	"top_aud_i2s5_mclk",
519	"top_aud_i2s6_mclk",
520	"top_asm_m_sel",
521	"top_asm_h_sel",
522	"top_univpll2_d4",
523	"top_univpll2_d2",
524	"top_syspll_d5";
525	};
526
f235c7e7 JL	527	mmsys: syscon@14000000 {
	528	compatible = "mediatek,mt2701-mmsys", "syscon";
	529	reg = <0 0x14000000 0 0x1000>;
	530	#clock-cells = <1>;
	531	};
	532
f3cba0f4 HZ	533	larb0: larb@14010000 {
	534	compatible = "mediatek,mt2701-smi-larb";
	535	reg = <0 0x14010000 0 0x1000>;
	536	mediatek,smi = <&smi_common>;
f679871f	537	mediatek,larb-id = <0>;
f3cba0f4 HZ	538	clocks = <&mmsys CLK_MM_SMI_LARB0>,
	539	<&mmsys CLK_MM_SMI_LARB0>;
	540	clock-names = "apb", "smi";
	541	power-domains = <&scpsys MT2701_POWER_DOMAIN_DISP>;
	542	};
	543
f235c7e7 JL	544	imgsys: syscon@15000000 {
	545	compatible = "mediatek,mt2701-imgsys", "syscon";
	546	reg = <0 0x15000000 0 0x1000>;
	547	#clock-cells = <1>;
	548	};
	549
f3cba0f4 HZ	550	larb2: larb@15001000 {
	551	compatible = "mediatek,mt2701-smi-larb";
	552	reg = <0 0x15001000 0 0x1000>;
	553	mediatek,smi = <&smi_common>;
f679871f	554	mediatek,larb-id = <2>;
f3cba0f4 HZ	555	clocks = <&imgsys CLK_IMG_SMI_COMM>,
	556	<&imgsys CLK_IMG_SMI_COMM>;
	557	clock-names = "apb", "smi";
	558	power-domains = <&scpsys MT2701_POWER_DOMAIN_ISP>;
	559	};
	560
c56ee526 RC	561	jpegdec: jpegdec@15004000 {
	562	compatible = "mediatek,mt2701-jpgdec";
	563	reg = <0 0x15004000 0 0x1000>;
	564	interrupts = <GIC_SPI 143 IRQ_TYPE_LEVEL_LOW>;
	565	clocks = <&imgsys CLK_IMG_JPGDEC_SMI>,
	566	<&imgsys CLK_IMG_JPGDEC>;
	567	clock-names = "jpgdec-smi",
	568	"jpgdec";
	569	power-domains = <&scpsys MT2701_POWER_DOMAIN_ISP>;
	570	mediatek,larb = <&larb2>;
	571	iommus = <&iommu MT2701_M4U_PORT_JPGDEC_WDMA>,
	572	<&iommu MT2701_M4U_PORT_JPGDEC_BSDMA>;
	573	};
	574
f235c7e7 JL	575	vdecsys: syscon@16000000 {
	576	compatible = "mediatek,mt2701-vdecsys", "syscon";
	577	reg = <0 0x16000000 0 0x1000>;
	578	#clock-cells = <1>;
	579	};
	580
f3cba0f4 HZ	581	larb1: larb@16010000 {
	582	compatible = "mediatek,mt2701-smi-larb";
	583	reg = <0 0x16010000 0 0x1000>;
	584	mediatek,smi = <&smi_common>;
f679871f	585	mediatek,larb-id = <1>;
f3cba0f4 HZ	586	clocks = <&vdecsys CLK_VDEC_CKGEN>,
	587	<&vdecsys CLK_VDEC_LARB>;
	588	clock-names = "apb", "smi";
	589	power-domains = <&scpsys MT2701_POWER_DOMAIN_VDEC>;
	590	};
	591
f235c7e7 JL	592	hifsys: syscon@1a000000 {
	593	compatible = "mediatek,mt2701-hifsys", "syscon";
	594	reg = <0 0x1a000000 0 0x1000>;
	595	#clock-cells = <1>;
	596	};
	597
295ad9fb CY	598	usb0: usb@1a1c0000 {
	599	compatible = "mediatek,mt8173-xhci";
	600	reg = <0 0x1a1c0000 0 0x1000>,
	601	<0 0x1a1c4700 0 0x0100>;
	602	reg-names = "mac", "ippc";
	603	interrupts = <GIC_SPI 196 IRQ_TYPE_LEVEL_LOW>;
	604	clocks = <&hifsys CLK_HIFSYS_USB0PHY>,
	605	<&topckgen CLK_TOP_ETHIF_SEL>;
	606	clock-names = "sys_ck", "ref_ck";
	607	power-domains = <&scpsys MT2701_POWER_DOMAIN_HIF>;
	608	phys = <&u2port0 PHY_TYPE_USB2>, <&u3port0 PHY_TYPE_USB3>;
	609	status = "disabled";
	610	};
	611
	612	u3phy0: usb-phy@1a1c4000 {
	613	compatible = "mediatek,mt2701-u3phy";
	614	reg = <0 0x1a1c4000 0 0x0700>;
	615	#address-cells = <2>;
	616	#size-cells = <2>;
	617	ranges;
	618	status = "disabled";
	619
	620	u2port0: usb-phy@1a1c4800 {
	621	reg = <0 0x1a1c4800 0 0x0100>;
	622	clocks = <&topckgen CLK_TOP_USB_PHY48M>;
	623	clock-names = "ref";
	624	#phy-cells = <1>;
	625	status = "okay";
	626	};
	627
	628	u3port0: usb-phy@1a1c4900 {
	629	reg = <0 0x1a1c4900 0 0x0700>;
	630	clocks = <&clk26m>;
	631	clock-names = "ref";
	632	#phy-cells = <1>;
	633	status = "okay";
	634	};
	635	};
	636
	637	usb1: usb@1a240000 {
	638	compatible = "mediatek,mt8173-xhci";
	639	reg = <0 0x1a240000 0 0x1000>,
	640	<0 0x1a244700 0 0x0100>;
	641	reg-names = "mac", "ippc";
	642	interrupts = <GIC_SPI 197 IRQ_TYPE_LEVEL_LOW>;
	643	clocks = <&hifsys CLK_HIFSYS_USB1PHY>,
	644	<&topckgen CLK_TOP_ETHIF_SEL>;
	645	clock-names = "sys_ck", "ref_ck";
	646	power-domains = <&scpsys MT2701_POWER_DOMAIN_HIF>;
	647	phys = <&u2port1 PHY_TYPE_USB2>, <&u3port1 PHY_TYPE_USB3>;
	648	status = "disabled";
	649	};
	650
	651	u3phy1: usb-phy@1a244000 {
	652	compatible = "mediatek,mt2701-u3phy";
	653	reg = <0 0x1a244000 0 0x0700>;
	654	#address-cells = <2>;
	655	#size-cells = <2>;
	656	ranges;
	657	status = "disabled";
	658
	659	u2port1: usb-phy@1a244800 {
	660	reg = <0 0x1a244800 0 0x0100>;
	661	clocks = <&topckgen CLK_TOP_USB_PHY48M>;
662	clock-names = "ref";
663	#phy-cells = <1>;
664	status = "okay";
665	};
666
667	u3port1: usb-phy@1a244900 {
668	reg = <0 0x1a244900 0 0x0700>;
669	clocks = <&clk26m>;
670	clock-names = "ref";
671	#phy-cells = <1>;
672	status = "okay";
673	};
674	};
675
f235c7e7 JL	676	ethsys: syscon@1b000000 {
	677	compatible = "mediatek,mt2701-ethsys", "syscon";
	678	reg = <0 0x1b000000 0 0x1000>;
	679	#clock-cells = <1>;
	680	};
	681
7aa125ba SW	682	eth: ethernet@1b100000 {
	683	compatible = "mediatek,mt2701-eth", "syscon";
	684	reg = <0 0x1b100000 0 0x20000>;
	685	interrupts = <GIC_SPI 200 IRQ_TYPE_LEVEL_LOW>,
	686	<GIC_SPI 199 IRQ_TYPE_LEVEL_LOW>,
	687	<GIC_SPI 198 IRQ_TYPE_LEVEL_LOW>;
	688	clocks = <&topckgen CLK_TOP_ETHIF_SEL>,
	689	<&ethsys CLK_ETHSYS_ESW>,
	690	<&ethsys CLK_ETHSYS_GP1>,
	691	<&ethsys CLK_ETHSYS_GP2>,
	692	<&apmixedsys CLK_APMIXED_TRGPLL>;
	693	clock-names = "ethif", "esw", "gp1", "gp2", "trgpll";
	694	resets = <&ethsys MT2701_ETHSYS_FE_RST>,
	695	<&ethsys MT2701_ETHSYS_GMAC_RST>,
	696	<&ethsys MT2701_ETHSYS_PPE_RST>;
	697	reset-names = "fe", "gmac", "ppe";
	698	power-domains = <&scpsys MT2701_POWER_DOMAIN_ETH>;
	699	mediatek,ethsys = <&ethsys>;
	700	mediatek,pctl = <&syscfg_pctl_a>;
	701	#address-cells = <1>;
	702	#size-cells = <0>;
	703	status = "disabled";
	704	};
	705
f235c7e7 JL	706	bdpsys: syscon@1c000000 {
	707	compatible = "mediatek,mt2701-bdpsys", "syscon";
	708	reg = <0 0x1c000000 0 0x1000>;
	709	#clock-cells = <1>;
	710	};
74d25721	711	};