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804a5dd6 JE |
1 | /* |
2 | * Common base for NXP LPC18xx and LPC43xx devices. | |
3 | * | |
4 | * Copyright 2015 Joachim Eastwood <manabian@gmail.com> | |
5 | * | |
6 | * This code is released using a dual license strategy: BSD/GPL | |
7 | * You can choose the licence that better fits your requirements. | |
8 | * | |
9 | * Released under the terms of 3-clause BSD License | |
10 | * Released under the terms of GNU General Public License Version 2.0 | |
11 | * | |
12 | */ | |
13 | ||
14 | #include "armv7-m.dtsi" | |
15 | ||
ba2db535 JE |
16 | #include "dt-bindings/clock/lpc18xx-cgu.h" |
17 | #include "dt-bindings/clock/lpc18xx-ccu.h" | |
18 | ||
7836dce4 JE |
19 | #define LPC_PIN(port, pin) (0x##port * 32 + pin) |
20 | #define LPC_GPIO(port, pin) (port * 32 + pin) | |
21 | ||
804a5dd6 JE |
22 | / { |
23 | cpus { | |
24 | #address-cells = <1>; | |
25 | #size-cells = <0>; | |
26 | ||
27 | cpu@0 { | |
28 | compatible = "arm,cortex-m3"; | |
29 | device_type = "cpu"; | |
30 | reg = <0x0>; | |
ba2db535 | 31 | clocks = <&ccu1 CLK_CPU_CORE>; |
804a5dd6 JE |
32 | }; |
33 | }; | |
34 | ||
35 | clocks { | |
36 | xtal: xtal { | |
37 | compatible = "fixed-clock"; | |
38 | #clock-cells = <0>; | |
39 | clock-frequency = <12000000>; | |
40 | }; | |
41 | ||
ba2db535 JE |
42 | xtal32: xtal32 { |
43 | compatible = "fixed-clock"; | |
44 | #clock-cells = <0>; | |
45 | clock-frequency = <32768>; | |
46 | }; | |
47 | ||
48 | enet_rx_clk: enet_rx_clk { | |
49 | compatible = "fixed-clock"; | |
50 | #clock-cells = <0>; | |
51 | clock-frequency = <0>; | |
52 | clock-output-names = "enet_rx_clk"; | |
53 | }; | |
54 | ||
55 | enet_tx_clk: enet_tx_clk { | |
56 | compatible = "fixed-clock"; | |
57 | #clock-cells = <0>; | |
58 | clock-frequency = <0>; | |
59 | clock-output-names = "enet_tx_clk"; | |
60 | }; | |
61 | ||
62 | gp_clkin: gp_clkin { | |
63 | compatible = "fixed-clock"; | |
804a5dd6 | 64 | #clock-cells = <0>; |
ba2db535 JE |
65 | clock-frequency = <0>; |
66 | clock-output-names = "gp_clkin"; | |
804a5dd6 JE |
67 | }; |
68 | }; | |
69 | ||
70 | soc { | |
cd07154f JE |
71 | mmcsd: mmcsd@40004000 { |
72 | compatible = "snps,dw-mshc"; | |
73 | reg = <0x40004000 0x1000>; | |
74 | interrupts = <6>; | |
75 | num-slots = <1>; | |
76 | clocks = <&ccu2 CLK_SDIO>, <&ccu1 CLK_CPU_SDIO>; | |
77 | clock-names = "ciu", "biu"; | |
78 | status = "disabled"; | |
79 | }; | |
80 | ||
b06cdb79 JE |
81 | usb0: ehci@40006100 { |
82 | compatible = "nxp,lpc1850-ehci", "generic-ehci"; | |
83 | reg = <0x40006100 0x100>; | |
84 | interrupts = <8>; | |
85 | clocks = <&ccu1 CLK_CPU_USB0>; | |
6d6d6b55 JE |
86 | phys = <&usb0_otg_phy>; |
87 | phy-names = "usb"; | |
b06cdb79 JE |
88 | has-transaction-translator; |
89 | status = "disabled"; | |
90 | }; | |
91 | ||
92 | usb1: ehci@40007100 { | |
93 | compatible = "nxp,lpc1850-ehci", "generic-ehci"; | |
94 | reg = <0x40007100 0x100>; | |
95 | interrupts = <9>; | |
96 | clocks = <&ccu1 CLK_CPU_USB1>; | |
97 | status = "disabled"; | |
98 | }; | |
99 | ||
9cf6267d JE |
100 | lcdc: lcd-controller@40008000 { |
101 | compatible = "arm,pl111", "arm,primecell"; | |
102 | reg = <0x40008000 0x1000>; | |
103 | interrupts = <7>; | |
104 | interrupt-names = "combined"; | |
105 | clocks = <&cgu BASE_LCD_CLK>, <&ccu1 CLK_CPU_LCD>; | |
106 | clock-names = "clcdclk", "apb_pclk"; | |
107 | status = "disabled"; | |
108 | }; | |
109 | ||
fe968589 JE |
110 | mac: ethernet@40010000 { |
111 | compatible = "nxp,lpc1850-dwmac", "snps,dwmac-3.611", "snps,dwmac"; | |
112 | reg = <0x40010000 0x2000>; | |
113 | interrupts = <5>; | |
114 | interrupt-names = "macirq"; | |
115 | clocks = <&ccu1 CLK_CPU_ETHERNET>; | |
116 | clock-names = "stmmaceth"; | |
117 | status = "disabled"; | |
118 | }; | |
119 | ||
16df2b86 JE |
120 | creg: syscon@40043000 { |
121 | compatible = "nxp,lpc1850-creg", "syscon", "simple-mfd"; | |
122 | reg = <0x40043000 0x1000>; | |
123 | clocks = <&ccu1 CLK_CPU_CREG>; | |
6d6d6b55 JE |
124 | |
125 | usb0_otg_phy: phy@004 { | |
126 | compatible = "nxp,lpc1850-usb-otg-phy"; | |
127 | clocks = <&ccu1 CLK_USB0>; | |
128 | #phy-cells = <0>; | |
129 | }; | |
16df2b86 JE |
130 | }; |
131 | ||
ba2db535 JE |
132 | cgu: clock-controller@40050000 { |
133 | compatible = "nxp,lpc1850-cgu"; | |
134 | reg = <0x40050000 0x1000>; | |
135 | #clock-cells = <1>; | |
136 | clocks = <&xtal>, <&xtal32>, <&enet_rx_clk>, <&enet_tx_clk>, <&gp_clkin>; | |
137 | }; | |
138 | ||
139 | ccu1: clock-controller@40051000 { | |
140 | compatible = "nxp,lpc1850-ccu"; | |
141 | reg = <0x40051000 0x1000>; | |
142 | #clock-cells = <1>; | |
143 | clocks = <&cgu BASE_APB3_CLK>, <&cgu BASE_APB1_CLK>, | |
144 | <&cgu BASE_SPIFI_CLK>, <&cgu BASE_CPU_CLK>, | |
145 | <&cgu BASE_PERIPH_CLK>, <&cgu BASE_USB0_CLK>, | |
146 | <&cgu BASE_USB1_CLK>, <&cgu BASE_SPI_CLK>; | |
147 | clock-names = "base_apb3_clk", "base_apb1_clk", | |
148 | "base_spifi_clk", "base_cpu_clk", | |
149 | "base_periph_clk", "base_usb0_clk", | |
150 | "base_usb1_clk", "base_spi_clk"; | |
151 | }; | |
152 | ||
153 | ccu2: clock-controller@40052000 { | |
154 | compatible = "nxp,lpc1850-ccu"; | |
155 | reg = <0x40052000 0x1000>; | |
156 | #clock-cells = <1>; | |
157 | clocks = <&cgu BASE_AUDIO_CLK>, <&cgu BASE_UART3_CLK>, | |
158 | <&cgu BASE_UART2_CLK>, <&cgu BASE_UART1_CLK>, | |
159 | <&cgu BASE_UART0_CLK>, <&cgu BASE_SSP1_CLK>, | |
160 | <&cgu BASE_SSP0_CLK>, <&cgu BASE_SDIO_CLK>; | |
161 | clock-names = "base_audio_clk", "base_uart3_clk", | |
162 | "base_uart2_clk", "base_uart1_clk", | |
163 | "base_uart0_clk", "base_ssp1_clk", | |
164 | "base_ssp0_clk", "base_sdio_clk"; | |
165 | }; | |
166 | ||
804a5dd6 | 167 | uart0: serial@40081000 { |
f2b1c507 | 168 | compatible = "nxp,lpc1850-uart", "ns16550a"; |
804a5dd6 JE |
169 | reg = <0x40081000 0x1000>; |
170 | reg-shift = <2>; | |
171 | interrupts = <24>; | |
ba2db535 | 172 | clocks = <&ccu2 CLK_APB0_UART0>, <&ccu1 CLK_CPU_UART0>; |
f2b1c507 | 173 | clock-names = "uartclk", "reg"; |
804a5dd6 JE |
174 | status = "disabled"; |
175 | }; | |
176 | ||
177 | uart1: serial@40082000 { | |
f2b1c507 | 178 | compatible = "nxp,lpc1850-uart", "ns16550a"; |
804a5dd6 JE |
179 | reg = <0x40082000 0x1000>; |
180 | reg-shift = <2>; | |
181 | interrupts = <25>; | |
ba2db535 | 182 | clocks = <&ccu2 CLK_APB0_UART1>, <&ccu1 CLK_CPU_UART1>; |
f2b1c507 | 183 | clock-names = "uartclk", "reg"; |
804a5dd6 JE |
184 | status = "disabled"; |
185 | }; | |
186 | ||
5d2ea79c JE |
187 | ssp0: spi@40083000 { |
188 | compatible = "arm,pl022", "arm,primecell"; | |
189 | reg = <0x40083000 0x1000>; | |
190 | interrupts = <22>; | |
191 | clocks = <&ccu2 CLK_APB0_SSP0>, <&ccu1 CLK_CPU_SSP0>; | |
192 | clock-names = "sspclk", "apb_pclk"; | |
193 | #address-cells = <1>; | |
194 | #size-cells = <0>; | |
195 | status = "disabled"; | |
196 | }; | |
197 | ||
804a5dd6 JE |
198 | timer0: timer@40084000 { |
199 | compatible = "nxp,lpc3220-timer"; | |
200 | reg = <0x40084000 0x1000>; | |
201 | interrupts = <12>; | |
ba2db535 | 202 | clocks = <&ccu1 CLK_CPU_TIMER0>; |
804a5dd6 JE |
203 | clock-names = "timerclk"; |
204 | }; | |
205 | ||
206 | timer1: timer@40085000 { | |
207 | compatible = "nxp,lpc3220-timer"; | |
208 | reg = <0x40085000 0x1000>; | |
209 | interrupts = <13>; | |
ba2db535 | 210 | clocks = <&ccu1 CLK_CPU_TIMER1>; |
804a5dd6 JE |
211 | clock-names = "timerclk"; |
212 | }; | |
213 | ||
d881f5e2 JE |
214 | pinctrl: pinctrl@40086000 { |
215 | compatible = "nxp,lpc1850-scu"; | |
216 | reg = <0x40086000 0x1000>; | |
217 | clocks = <&ccu1 CLK_CPU_SCU>; | |
218 | }; | |
219 | ||
7e6c8376 JE |
220 | can1: can@400a4000 { |
221 | compatible = "bosch,c_can"; | |
222 | reg = <0x400a4000 0x1000>; | |
223 | interrupts = <43>; | |
224 | clocks = <&ccu1 CLK_APB1_CAN1>; | |
225 | status = "disabled"; | |
226 | }; | |
227 | ||
804a5dd6 | 228 | uart2: serial@400c1000 { |
f2b1c507 | 229 | compatible = "nxp,lpc1850-uart", "ns16550a"; |
804a5dd6 JE |
230 | reg = <0x400c1000 0x1000>; |
231 | reg-shift = <2>; | |
232 | interrupts = <26>; | |
ba2db535 | 233 | clocks = <&ccu2 CLK_APB2_UART2>, <&ccu1 CLK_CPU_UART2>; |
f2b1c507 | 234 | clock-names = "uartclk", "reg"; |
804a5dd6 JE |
235 | status = "disabled"; |
236 | }; | |
237 | ||
238 | uart3: serial@400c2000 { | |
f2b1c507 | 239 | compatible = "nxp,lpc1850-uart", "ns16550a"; |
804a5dd6 JE |
240 | reg = <0x400c2000 0x1000>; |
241 | reg-shift = <2>; | |
242 | interrupts = <27>; | |
ba2db535 | 243 | clocks = <&ccu2 CLK_APB2_UART3>, <&ccu1 CLK_CPU_UART3>; |
f2b1c507 | 244 | clock-names = "uartclk", "reg"; |
804a5dd6 JE |
245 | status = "disabled"; |
246 | }; | |
247 | ||
248 | timer2: timer@400c3000 { | |
249 | compatible = "nxp,lpc3220-timer"; | |
250 | reg = <0x400c3000 0x1000>; | |
251 | interrupts = <14>; | |
ba2db535 | 252 | clocks = <&ccu1 CLK_CPU_TIMER2>; |
804a5dd6 JE |
253 | clock-names = "timerclk"; |
254 | }; | |
255 | ||
256 | timer3: timer@400c4000 { | |
257 | compatible = "nxp,lpc3220-timer"; | |
258 | reg = <0x400c4000 0x1000>; | |
259 | interrupts = <15>; | |
ba2db535 | 260 | clocks = <&ccu1 CLK_CPU_TIMER3>; |
804a5dd6 JE |
261 | clock-names = "timerclk"; |
262 | }; | |
7836dce4 | 263 | |
5d2ea79c JE |
264 | ssp1: spi@400c5000 { |
265 | compatible = "arm,pl022", "arm,primecell"; | |
266 | reg = <0x400c5000 0x1000>; | |
267 | interrupts = <23>; | |
268 | clocks = <&ccu2 CLK_APB2_SSP1>, <&ccu1 CLK_CPU_SSP1>; | |
269 | clock-names = "sspclk", "apb_pclk"; | |
270 | #address-cells = <1>; | |
271 | #size-cells = <0>; | |
272 | status = "disabled"; | |
273 | }; | |
274 | ||
7e6c8376 JE |
275 | can0: can@400e2000 { |
276 | compatible = "bosch,c_can"; | |
277 | reg = <0x400e2000 0x1000>; | |
278 | interrupts = <51>; | |
279 | clocks = <&ccu1 CLK_APB3_CAN0>; | |
280 | status = "disabled"; | |
281 | }; | |
282 | ||
7836dce4 JE |
283 | gpio: gpio@400f4000 { |
284 | compatible = "nxp,lpc1850-gpio"; | |
285 | reg = <0x400f4000 0x4000>; | |
286 | clocks = <&ccu1 CLK_CPU_GPIO>; | |
287 | gpio-controller; | |
288 | #gpio-cells = <2>; | |
289 | gpio-ranges = <&pinctrl LPC_GPIO(0,0) LPC_PIN(0,0) 2>, | |
290 | <&pinctrl LPC_GPIO(0,4) LPC_PIN(1,0) 1>, | |
291 | <&pinctrl LPC_GPIO(0,8) LPC_PIN(1,1) 4>, | |
292 | <&pinctrl LPC_GPIO(1,8) LPC_PIN(1,5) 2>, | |
293 | <&pinctrl LPC_GPIO(1,0) LPC_PIN(1,7) 8>, | |
294 | <&pinctrl LPC_GPIO(0,2) LPC_PIN(1,15) 2>, | |
295 | <&pinctrl LPC_GPIO(0,12) LPC_PIN(1,17) 2>, | |
296 | <&pinctrl LPC_GPIO(0,15) LPC_PIN(1,20) 1>, | |
297 | <&pinctrl LPC_GPIO(5,0) LPC_PIN(2,0) 7>, | |
298 | <&pinctrl LPC_GPIO(0,7) LPC_PIN(2,7) 1>, | |
299 | <&pinctrl LPC_GPIO(5,7) LPC_PIN(2,8) 1>, | |
300 | <&pinctrl LPC_GPIO(1,10) LPC_PIN(2,9) 1>, | |
301 | <&pinctrl LPC_GPIO(0,14) LPC_PIN(2,10) 1>, | |
302 | <&pinctrl LPC_GPIO(1,11) LPC_PIN(2,11) 3>, | |
303 | <&pinctrl LPC_GPIO(5,8) LPC_PIN(3,1) 2>, | |
304 | <&pinctrl LPC_GPIO(1,14) LPC_PIN(3,4) 2>, | |
305 | <&pinctrl LPC_GPIO(0,6) LPC_PIN(3,6) 1>, | |
306 | <&pinctrl LPC_GPIO(5,10) LPC_PIN(3,7) 2>, | |
307 | <&pinctrl LPC_GPIO(2,0) LPC_PIN(4,0) 7>, | |
308 | <&pinctrl LPC_GPIO(5,12) LPC_PIN(4,8) 3>, | |
309 | <&pinctrl LPC_GPIO(2,9) LPC_PIN(5,0) 7>, | |
310 | <&pinctrl LPC_GPIO(2,7) LPC_PIN(5,7) 1>, | |
311 | <&pinctrl LPC_GPIO(3,0) LPC_PIN(6,1) 5>, | |
312 | <&pinctrl LPC_GPIO(0,5) LPC_PIN(6,6) 1>, | |
313 | <&pinctrl LPC_GPIO(5,15) LPC_PIN(6,7) 2>, | |
314 | <&pinctrl LPC_GPIO(3,5) LPC_PIN(6,9) 3>, | |
315 | <&pinctrl LPC_GPIO(2,8) LPC_PIN(6,12) 1>, | |
316 | <&pinctrl LPC_GPIO(3,8) LPC_PIN(7,0) 8>, | |
317 | <&pinctrl LPC_GPIO(4,0) LPC_PIN(8,0) 8>, | |
318 | <&pinctrl LPC_GPIO(4,12) LPC_PIN(9,0) 4>, | |
319 | <&pinctrl LPC_GPIO(5,17) LPC_PIN(9,4) 2>, | |
320 | <&pinctrl LPC_GPIO(4,11) LPC_PIN(9,6) 1>, | |
321 | <&pinctrl LPC_GPIO(4,8) LPC_PIN(a,1) 3>, | |
322 | <&pinctrl LPC_GPIO(5,19) LPC_PIN(a,4) 1>, | |
323 | <&pinctrl LPC_GPIO(5,20) LPC_PIN(b,0) 7>, | |
324 | <&pinctrl LPC_GPIO(6,0) LPC_PIN(c,1) 14>, | |
325 | <&pinctrl LPC_GPIO(6,14) LPC_PIN(d,0) 17>, | |
326 | <&pinctrl LPC_GPIO(7,0) LPC_PIN(e,0) 16>, | |
327 | <&pinctrl LPC_GPIO(7,16) LPC_PIN(f,1) 3>, | |
328 | <&pinctrl LPC_GPIO(7,19) LPC_PIN(f,5) 7>; | |
329 | }; | |
804a5dd6 JE |
330 | }; |
331 | }; |