[linux-2.6-block.git] / arch / arm / boot / dts / lpc18xx.dtsi

/*
 * Common base for NXP LPC18xx and LPC43xx devices.
 *
 * Copyright 2015 Joachim Eastwood <manabian@gmail.com>
 *
 * This code is released using a dual license strategy: BSD/GPL
 * You can choose the licence that better fits your requirements.
 *
 * Released under the terms of 3-clause BSD License
 * Released under the terms of GNU General Public License Version 2.0
 *
 */

#include "armv7-m.dtsi"

#include "dt-bindings/clock/lpc18xx-cgu.h"
#include "dt-bindings/clock/lpc18xx-ccu.h"

#define LPC_PIN(port, pin)	(0x##port * 32 + pin)
#define LPC_GPIO(port, pin)	(port * 32 + pin)

/ {
	cpus {
		#address-cells = <1>;
		#size-cells = <0>;

		cpu@0 {
			compatible = "arm,cortex-m3";
			device_type = "cpu";
			reg = <0x0>;
			clocks = <&ccu1 CLK_CPU_CORE>;
		};
	};

	clocks {
		xtal: xtal {
			compatible = "fixed-clock";
			#clock-cells = <0>;
			clock-frequency = <12000000>;
		};

		xtal32: xtal32 {
			compatible = "fixed-clock";
			#clock-cells = <0>;
			clock-frequency = <32768>;
		};

		enet_rx_clk: enet_rx_clk {
			compatible = "fixed-clock";
			#clock-cells = <0>;
			clock-frequency = <0>;
			clock-output-names = "enet_rx_clk";
		};

		enet_tx_clk: enet_tx_clk {
			compatible = "fixed-clock";
			#clock-cells = <0>;
			clock-frequency = <0>;
			clock-output-names = "enet_tx_clk";
		};

		gp_clkin: gp_clkin {
			compatible = "fixed-clock";
			#clock-cells = <0>;
			clock-frequency = <0>;
			clock-output-names = "gp_clkin";
		};
	};

	soc {
		dmac: dma-controller@40002000 {
			compatible = "arm,pl080", "arm,primecell";
			arm,primecell-periphid = <0x00041080>;
			reg = <0x40002000 0x1000>;
			interrupts = <2>;
			clocks = <&ccu1 CLK_CPU_DMA>;
			clock-names = "apb_pclk";
			resets = <&rgu 19>;
			#dma-cells = <2>;
			dma-channels = <8>;
			dma-requests = <16>;
			lli-bus-interface-ahb1;
			lli-bus-interface-ahb2;
			mem-bus-interface-ahb1;
			mem-bus-interface-ahb2;
			memcpy-burst-size = <256>;
			memcpy-bus-width = <32>;
		};

		spifi: flash-controller@40003000 {
			compatible = "nxp,lpc1773-spifi";
			reg = <0x40003000 0x1000>, <0x14000000 0x4000000>;
			reg-names = "spifi", "flash";
			interrupts = <30>;
			clocks = <&ccu1 CLK_SPIFI>, <&ccu1 CLK_CPU_SPIFI>;
			clock-names = "spifi", "reg";
			resets = <&rgu 53>;
			status = "disabled";
		};

		mmcsd: mmcsd@40004000 {
			compatible = "snps,dw-mshc";
			reg = <0x40004000 0x1000>;
			interrupts = <6>;
			num-slots = <1>;
			clocks = <&ccu2 CLK_SDIO>, <&ccu1 CLK_CPU_SDIO>;
			clock-names = "ciu", "biu";
			status = "disabled";
		};

		usb0: ehci@40006100 {
			compatible = "nxp,lpc1850-ehci", "generic-ehci";
			reg = <0x40006100 0x100>;
			interrupts = <8>;
			clocks = <&ccu1 CLK_CPU_USB0>;
			phys = <&usb0_otg_phy>;
			phy-names = "usb";
			has-transaction-translator;
			status = "disabled";
		};

		usb1: ehci@40007100 {
			compatible = "nxp,lpc1850-ehci", "generic-ehci";
			reg = <0x40007100 0x100>;
			interrupts = <9>;
			clocks = <&ccu1 CLK_CPU_USB1>;
			status = "disabled";
		};

		emc: memory-controller@40005000 {
			compatible = "arm,pl172", "arm,primecell";
			reg = <0x40005000 0x1000>;
			clocks = <&ccu1 CLK_CPU_EMCDIV>, <&ccu1 CLK_CPU_EMC>;
			clock-names = "mpmcclk", "apb_pclk";
			#address-cells = <2>;
			#size-cells = <1>;
			ranges = <0 0 0x1c000000 0x1000000
				  1 0 0x1d000000 0x1000000
				  2 0 0x1e000000 0x1000000
				  3 0 0x1f000000 0x1000000>;
			status = "disabled";
		};

		lcdc: lcd-controller@40008000 {
			compatible = "arm,pl111", "arm,primecell";
			reg = <0x40008000 0x1000>;
			interrupts = <7>;
			interrupt-names = "combined";
			clocks = <&cgu BASE_LCD_CLK>, <&ccu1 CLK_CPU_LCD>;
			clock-names = "clcdclk", "apb_pclk";
			status = "disabled";
		};

		mac: ethernet@40010000 {
			compatible = "nxp,lpc1850-dwmac", "snps,dwmac-3.611", "snps,dwmac";
			reg = <0x40010000 0x2000>;
			interrupts = <5>;
			interrupt-names	= "macirq";
			clocks = <&ccu1 CLK_CPU_ETHERNET>;
			clock-names = "stmmaceth";
			status = "disabled";
		};

		creg: syscon@40043000 {
			compatible = "nxp,lpc1850-creg", "syscon", "simple-mfd";
			reg = <0x40043000 0x1000>;
			clocks = <&ccu1 CLK_CPU_CREG>;

			usb0_otg_phy: phy@004 {
				compatible = "nxp,lpc1850-usb-otg-phy";
				clocks = <&ccu1 CLK_USB0>;
				#phy-cells = <0>;
			};
		};

		cgu: clock-controller@40050000 {
			compatible = "nxp,lpc1850-cgu";
			reg = <0x40050000 0x1000>;
			#clock-cells = <1>;
			clocks = <&xtal>, <&xtal32>, <&enet_rx_clk>, <&enet_tx_clk>, <&gp_clkin>;
		};

		ccu1: clock-controller@40051000 {
			compatible = "nxp,lpc1850-ccu";
			reg = <0x40051000 0x1000>;
			#clock-cells = <1>;
			clocks = <&cgu BASE_APB3_CLK>,   <&cgu BASE_APB1_CLK>,
				 <&cgu BASE_SPIFI_CLK>,  <&cgu BASE_CPU_CLK>,
				 <&cgu BASE_PERIPH_CLK>, <&cgu BASE_USB0_CLK>,
				 <&cgu BASE_USB1_CLK>,   <&cgu BASE_SPI_CLK>;
			clock-names = "base_apb3_clk",   "base_apb1_clk",
				      "base_spifi_clk",  "base_cpu_clk",
				      "base_periph_clk", "base_usb0_clk",
				      "base_usb1_clk",   "base_spi_clk";
		};

		ccu2: clock-controller@40052000 {
			compatible = "nxp,lpc1850-ccu";
			reg = <0x40052000 0x1000>;
			#clock-cells = <1>;
			clocks = <&cgu BASE_AUDIO_CLK>, <&cgu BASE_UART3_CLK>,
				 <&cgu BASE_UART2_CLK>, <&cgu BASE_UART1_CLK>,
				 <&cgu BASE_UART0_CLK>, <&cgu BASE_SSP1_CLK>,
				 <&cgu BASE_SSP0_CLK>,  <&cgu BASE_SDIO_CLK>;
			clock-names = "base_audio_clk", "base_uart3_clk",
				      "base_uart2_clk", "base_uart1_clk",
				      "base_uart0_clk", "base_ssp1_clk",
				      "base_ssp0_clk",  "base_sdio_clk";
		};

		rgu: reset-controller@40053000 {
			compatible = "nxp,lpc1850-rgu";
			reg = <0x40053000 0x1000>;
			clocks = <&cgu BASE_SAFE_CLK>, <&ccu1 CLK_CPU_BUS>;
			clock-names = "delay", "reg";
			#reset-cells = <1>;
		};

		uart0: serial@40081000 {
			compatible = "nxp,lpc1850-uart", "ns16550a";
			reg = <0x40081000 0x1000>;
			reg-shift = <2>;
			interrupts = <24>;
			clocks = <&ccu2 CLK_APB0_UART0>, <&ccu1 CLK_CPU_UART0>;
			clock-names = "uartclk", "reg";
			status = "disabled";
		};

		uart1: serial@40082000 {
			compatible = "nxp,lpc1850-uart", "ns16550a";
			reg = <0x40082000 0x1000>;
			reg-shift = <2>;
			interrupts = <25>;
			clocks = <&ccu2 CLK_APB0_UART1>, <&ccu1 CLK_CPU_UART1>;
			clock-names = "uartclk", "reg";
			status = "disabled";
		};

		ssp0: spi@40083000 {
			compatible = "arm,pl022", "arm,primecell";
			reg = <0x40083000 0x1000>;
			interrupts = <22>;
			clocks = <&ccu2 CLK_APB0_SSP0>, <&ccu1 CLK_CPU_SSP0>;
			clock-names = "sspclk", "apb_pclk";
			#address-cells = <1>;
			#size-cells = <0>;
			status = "disabled";
		};

		timer0: timer@40084000 {
			compatible = "nxp,lpc3220-timer";
			reg = <0x40084000 0x1000>;
			interrupts = <12>;
			clocks = <&ccu1 CLK_CPU_TIMER0>;
			clock-names = "timerclk";
		};

		timer1: timer@40085000 {
			compatible = "nxp,lpc3220-timer";
			reg = <0x40085000 0x1000>;
			interrupts = <13>;
			clocks = <&ccu1 CLK_CPU_TIMER1>;
			clock-names = "timerclk";
		};

		pinctrl: pinctrl@40086000 {
			compatible = "nxp,lpc1850-scu";
			reg = <0x40086000 0x1000>;
			clocks = <&ccu1 CLK_CPU_SCU>;
		};

		can1: can@400a4000 {
			compatible = "bosch,c_can";
			reg = <0x400a4000 0x1000>;
			interrupts = <43>;
			clocks = <&ccu1 CLK_APB1_CAN1>;
			status = "disabled";
		};

		uart2: serial@400c1000 {
			compatible = "nxp,lpc1850-uart", "ns16550a";
			reg = <0x400c1000 0x1000>;
			reg-shift = <2>;
			interrupts = <26>;
			clocks = <&ccu2 CLK_APB2_UART2>, <&ccu1 CLK_CPU_UART2>;
			clock-names = "uartclk", "reg";
			status = "disabled";
		};

		uart3: serial@400c2000 {
			compatible = "nxp,lpc1850-uart", "ns16550a";
			reg = <0x400c2000 0x1000>;
			reg-shift = <2>;
			interrupts = <27>;
			clocks = <&ccu2 CLK_APB2_UART3>, <&ccu1 CLK_CPU_UART3>;
			clock-names = "uartclk", "reg";
			status = "disabled";
		};

		timer2: timer@400c3000 {
			compatible = "nxp,lpc3220-timer";
			reg = <0x400c3000 0x1000>;
			interrupts = <14>;
			clocks = <&ccu1 CLK_CPU_TIMER2>;
			clock-names = "timerclk";
		};

		timer3: timer@400c4000 {
			compatible = "nxp,lpc3220-timer";
			reg = <0x400c4000 0x1000>;
			interrupts = <15>;
			clocks = <&ccu1 CLK_CPU_TIMER3>;
			clock-names = "timerclk";
		};

		ssp1: spi@400c5000 {
			compatible = "arm,pl022", "arm,primecell";
			reg = <0x400c5000 0x1000>;
			interrupts = <23>;
			clocks = <&ccu2 CLK_APB2_SSP1>, <&ccu1 CLK_CPU_SSP1>;
			clock-names = "sspclk", "apb_pclk";
			#address-cells = <1>;
			#size-cells = <0>;
			status = "disabled";
		};

		can0: can@400e2000 {
			compatible = "bosch,c_can";
			reg = <0x400e2000 0x1000>;
			interrupts = <51>;
			clocks = <&ccu1 CLK_APB3_CAN0>;
			status = "disabled";
		};

		gpio: gpio@400f4000 {
			compatible = "nxp,lpc1850-gpio";
			reg = <0x400f4000 0x4000>;
			clocks = <&ccu1 CLK_CPU_GPIO>;
			gpio-controller;
			#gpio-cells = <2>;
			gpio-ranges =	<&pinctrl LPC_GPIO(0,0)  LPC_PIN(0,0)  2>,
					<&pinctrl LPC_GPIO(0,4)  LPC_PIN(1,0)  1>,
					<&pinctrl LPC_GPIO(0,8)  LPC_PIN(1,1)  4>,
					<&pinctrl LPC_GPIO(1,8)  LPC_PIN(1,5)  2>,
					<&pinctrl LPC_GPIO(1,0)  LPC_PIN(1,7)  8>,
					<&pinctrl LPC_GPIO(0,2)  LPC_PIN(1,15) 2>,
					<&pinctrl LPC_GPIO(0,12) LPC_PIN(1,17) 2>,
					<&pinctrl LPC_GPIO(0,15) LPC_PIN(1,20) 1>,
					<&pinctrl LPC_GPIO(5,0)  LPC_PIN(2,0)  7>,
					<&pinctrl LPC_GPIO(0,7)  LPC_PIN(2,7)  1>,
					<&pinctrl LPC_GPIO(5,7)  LPC_PIN(2,8)  1>,
					<&pinctrl LPC_GPIO(1,10) LPC_PIN(2,9)  1>,
					<&pinctrl LPC_GPIO(0,14) LPC_PIN(2,10) 1>,
					<&pinctrl LPC_GPIO(1,11) LPC_PIN(2,11) 3>,
					<&pinctrl LPC_GPIO(5,8)  LPC_PIN(3,1)  2>,
					<&pinctrl LPC_GPIO(1,14) LPC_PIN(3,4)  2>,
					<&pinctrl LPC_GPIO(0,6)  LPC_PIN(3,6)  1>,
					<&pinctrl LPC_GPIO(5,10) LPC_PIN(3,7)  2>,
					<&pinctrl LPC_GPIO(2,0)  LPC_PIN(4,0)  7>,
					<&pinctrl LPC_GPIO(5,12) LPC_PIN(4,8)  3>,
					<&pinctrl LPC_GPIO(2,9)  LPC_PIN(5,0)  7>,
					<&pinctrl LPC_GPIO(2,7)  LPC_PIN(5,7)  1>,
					<&pinctrl LPC_GPIO(3,0)  LPC_PIN(6,1)  5>,
					<&pinctrl LPC_GPIO(0,5)  LPC_PIN(6,6)  1>,
					<&pinctrl LPC_GPIO(5,15) LPC_PIN(6,7)  2>,
					<&pinctrl LPC_GPIO(3,5)  LPC_PIN(6,9)  3>,
					<&pinctrl LPC_GPIO(2,8)  LPC_PIN(6,12) 1>,
					<&pinctrl LPC_GPIO(3,8)  LPC_PIN(7,0)  8>,
					<&pinctrl LPC_GPIO(4,0)  LPC_PIN(8,0)  8>,
					<&pinctrl LPC_GPIO(4,12) LPC_PIN(9,0)  4>,
					<&pinctrl LPC_GPIO(5,17) LPC_PIN(9,4)  2>,
					<&pinctrl LPC_GPIO(4,11) LPC_PIN(9,6)  1>,
					<&pinctrl LPC_GPIO(4,8)  LPC_PIN(a,1)  3>,
					<&pinctrl LPC_GPIO(5,19) LPC_PIN(a,4)  1>,
					<&pinctrl LPC_GPIO(5,20) LPC_PIN(b,0)  7>,
					<&pinctrl LPC_GPIO(6,0)  LPC_PIN(c,1) 14>,
					<&pinctrl LPC_GPIO(6,14) LPC_PIN(d,0) 17>,
					<&pinctrl LPC_GPIO(7,0)  LPC_PIN(e,0) 16>,
					<&pinctrl LPC_GPIO(7,16) LPC_PIN(f,1)  3>,
					<&pinctrl LPC_GPIO(7,19) LPC_PIN(f,5)  7>;
		};
	};
};
Commit	Line	Data
804a5dd6 JE	1	/*
	2	* Common base for NXP LPC18xx and LPC43xx devices.
	3	*
	4	* Copyright 2015 Joachim Eastwood <manabian@gmail.com>
	5	*
	6	* This code is released using a dual license strategy: BSD/GPL
	7	* You can choose the licence that better fits your requirements.
	8	*
	9	* Released under the terms of 3-clause BSD License
	10	* Released under the terms of GNU General Public License Version 2.0
	11	*
	12	*/
	13
	14	#include "armv7-m.dtsi"
	15
ba2db535 JE	16	#include "dt-bindings/clock/lpc18xx-cgu.h"
	17	#include "dt-bindings/clock/lpc18xx-ccu.h"
	18
7836dce4 JE	19	#define LPC_PIN(port, pin) (0x##port * 32 + pin)
	20	#define LPC_GPIO(port, pin) (port * 32 + pin)
	21
804a5dd6 JE	22	/ {
	23	cpus {
	24	#address-cells = <1>;
	25	#size-cells = <0>;
	26
	27	cpu@0 {
	28	compatible = "arm,cortex-m3";
	29	device_type = "cpu";
	30	reg = <0x0>;
ba2db535	31	clocks = <&ccu1 CLK_CPU_CORE>;
804a5dd6 JE	32	};
	33	};
	34
	35	clocks {
	36	xtal: xtal {
	37	compatible = "fixed-clock";
	38	#clock-cells = <0>;
	39	clock-frequency = <12000000>;
	40	};
	41
ba2db535 JE	42	xtal32: xtal32 {
	43	compatible = "fixed-clock";
	44	#clock-cells = <0>;
	45	clock-frequency = <32768>;
	46	};
	47
	48	enet_rx_clk: enet_rx_clk {
	49	compatible = "fixed-clock";
	50	#clock-cells = <0>;
	51	clock-frequency = <0>;
	52	clock-output-names = "enet_rx_clk";
	53	};
	54
	55	enet_tx_clk: enet_tx_clk {
	56	compatible = "fixed-clock";
	57	#clock-cells = <0>;
	58	clock-frequency = <0>;
	59	clock-output-names = "enet_tx_clk";
	60	};
	61
	62	gp_clkin: gp_clkin {
	63	compatible = "fixed-clock";
804a5dd6	64	#clock-cells = <0>;
ba2db535 JE	65	clock-frequency = <0>;
ba2db535 JE	66	clock-output-names = "gp_clkin";
804a5dd6 JE	67	};
	68	};
	69
	70	soc {
5924007c JE	71	dmac: dma-controller@40002000 {
	72	compatible = "arm,pl080", "arm,primecell";
	73	arm,primecell-periphid = <0x00041080>;
	74	reg = <0x40002000 0x1000>;
	75	interrupts = <2>;
	76	clocks = <&ccu1 CLK_CPU_DMA>;
	77	clock-names = "apb_pclk";
	78	resets = <&rgu 19>;
	79	#dma-cells = <2>;
	80	dma-channels = <8>;
	81	dma-requests = <16>;
	82	lli-bus-interface-ahb1;
	83	lli-bus-interface-ahb2;
	84	mem-bus-interface-ahb1;
	85	mem-bus-interface-ahb2;
	86	memcpy-burst-size = <256>;
	87	memcpy-bus-width = <32>;
	88	};
	89
4f85dd16 JE	90	spifi: flash-controller@40003000 {
	91	compatible = "nxp,lpc1773-spifi";
	92	reg = <0x40003000 0x1000>, <0x14000000 0x4000000>;
	93	reg-names = "spifi", "flash";
	94	interrupts = <30>;
	95	clocks = <&ccu1 CLK_SPIFI>, <&ccu1 CLK_CPU_SPIFI>;
	96	clock-names = "spifi", "reg";
	97	resets = <&rgu 53>;
	98	status = "disabled";
	99	};
	100
cd07154f JE	101	mmcsd: mmcsd@40004000 {
	102	compatible = "snps,dw-mshc";
	103	reg = <0x40004000 0x1000>;
	104	interrupts = <6>;
	105	num-slots = <1>;
	106	clocks = <&ccu2 CLK_SDIO>, <&ccu1 CLK_CPU_SDIO>;
	107	clock-names = "ciu", "biu";
	108	status = "disabled";
	109	};
	110
b06cdb79 JE	111	usb0: ehci@40006100 {
	112	compatible = "nxp,lpc1850-ehci", "generic-ehci";
	113	reg = <0x40006100 0x100>;
	114	interrupts = <8>;
	115	clocks = <&ccu1 CLK_CPU_USB0>;
6d6d6b55 JE	116	phys = <&usb0_otg_phy>;
6d6d6b55 JE	117	phy-names = "usb";
b06cdb79 JE	118	has-transaction-translator;
	119	status = "disabled";
	120	};
	121
	122	usb1: ehci@40007100 {
	123	compatible = "nxp,lpc1850-ehci", "generic-ehci";
	124	reg = <0x40007100 0x100>;
	125	interrupts = <9>;
	126	clocks = <&ccu1 CLK_CPU_USB1>;
	127	status = "disabled";
	128	};
	129
50016385 JE	130	emc: memory-controller@40005000 {
	131	compatible = "arm,pl172", "arm,primecell";
	132	reg = <0x40005000 0x1000>;
	133	clocks = <&ccu1 CLK_CPU_EMCDIV>, <&ccu1 CLK_CPU_EMC>;
	134	clock-names = "mpmcclk", "apb_pclk";
	135	#address-cells = <2>;
	136	#size-cells = <1>;
	137	ranges = <0 0 0x1c000000 0x1000000
	138	1 0 0x1d000000 0x1000000
	139	2 0 0x1e000000 0x1000000
	140	3 0 0x1f000000 0x1000000>;
	141	status = "disabled";
	142	};
	143
9cf6267d JE	144	lcdc: lcd-controller@40008000 {
	145	compatible = "arm,pl111", "arm,primecell";
	146	reg = <0x40008000 0x1000>;
	147	interrupts = <7>;
	148	interrupt-names = "combined";
	149	clocks = <&cgu BASE_LCD_CLK>, <&ccu1 CLK_CPU_LCD>;
	150	clock-names = "clcdclk", "apb_pclk";
	151	status = "disabled";
	152	};
	153
fe968589 JE	154	mac: ethernet@40010000 {
	155	compatible = "nxp,lpc1850-dwmac", "snps,dwmac-3.611", "snps,dwmac";
	156	reg = <0x40010000 0x2000>;
	157	interrupts = <5>;
	158	interrupt-names = "macirq";
	159	clocks = <&ccu1 CLK_CPU_ETHERNET>;
	160	clock-names = "stmmaceth";
	161	status = "disabled";
	162	};
	163
16df2b86 JE	164	creg: syscon@40043000 {
	165	compatible = "nxp,lpc1850-creg", "syscon", "simple-mfd";
	166	reg = <0x40043000 0x1000>;
	167	clocks = <&ccu1 CLK_CPU_CREG>;
6d6d6b55 JE	168
	169	usb0_otg_phy: phy@004 {
	170	compatible = "nxp,lpc1850-usb-otg-phy";
	171	clocks = <&ccu1 CLK_USB0>;
	172	#phy-cells = <0>;
	173	};
16df2b86 JE	174	};
16df2b86 JE	175
ba2db535 JE	176	cgu: clock-controller@40050000 {
	177	compatible = "nxp,lpc1850-cgu";
	178	reg = <0x40050000 0x1000>;
	179	#clock-cells = <1>;
	180	clocks = <&xtal>, <&xtal32>, <&enet_rx_clk>, <&enet_tx_clk>, <&gp_clkin>;
	181	};
	182
	183	ccu1: clock-controller@40051000 {
	184	compatible = "nxp,lpc1850-ccu";
	185	reg = <0x40051000 0x1000>;
	186	#clock-cells = <1>;
	187	clocks = <&cgu BASE_APB3_CLK>, <&cgu BASE_APB1_CLK>,
	188	<&cgu BASE_SPIFI_CLK>, <&cgu BASE_CPU_CLK>,
	189	<&cgu BASE_PERIPH_CLK>, <&cgu BASE_USB0_CLK>,
	190	<&cgu BASE_USB1_CLK>, <&cgu BASE_SPI_CLK>;
	191	clock-names = "base_apb3_clk", "base_apb1_clk",
	192	"base_spifi_clk", "base_cpu_clk",
	193	"base_periph_clk", "base_usb0_clk",
	194	"base_usb1_clk", "base_spi_clk";
	195	};
	196
	197	ccu2: clock-controller@40052000 {
	198	compatible = "nxp,lpc1850-ccu";
	199	reg = <0x40052000 0x1000>;
	200	#clock-cells = <1>;
	201	clocks = <&cgu BASE_AUDIO_CLK>, <&cgu BASE_UART3_CLK>,
	202	<&cgu BASE_UART2_CLK>, <&cgu BASE_UART1_CLK>,
	203	<&cgu BASE_UART0_CLK>, <&cgu BASE_SSP1_CLK>,
	204	<&cgu BASE_SSP0_CLK>, <&cgu BASE_SDIO_CLK>;
	205	clock-names = "base_audio_clk", "base_uart3_clk",
	206	"base_uart2_clk", "base_uart1_clk",
	207	"base_uart0_clk", "base_ssp1_clk",
	208	"base_ssp0_clk", "base_sdio_clk";
	209	};
	210
0745c702 JE	211	rgu: reset-controller@40053000 {
	212	compatible = "nxp,lpc1850-rgu";
	213	reg = <0x40053000 0x1000>;
	214	clocks = <&cgu BASE_SAFE_CLK>, <&ccu1 CLK_CPU_BUS>;
	215	clock-names = "delay", "reg";
	216	#reset-cells = <1>;
	217	};
	218
804a5dd6	219	uart0: serial@40081000 {
f2b1c507	220	compatible = "nxp,lpc1850-uart", "ns16550a";
804a5dd6 JE	221	reg = <0x40081000 0x1000>;
	222	reg-shift = <2>;
	223	interrupts = <24>;
ba2db535	224	clocks = <&ccu2 CLK_APB0_UART0>, <&ccu1 CLK_CPU_UART0>;
f2b1c507	225	clock-names = "uartclk", "reg";
804a5dd6 JE	226	status = "disabled";
	227	};
	228
	229	uart1: serial@40082000 {
f2b1c507	230	compatible = "nxp,lpc1850-uart", "ns16550a";
804a5dd6 JE	231	reg = <0x40082000 0x1000>;
	232	reg-shift = <2>;
	233	interrupts = <25>;
ba2db535	234	clocks = <&ccu2 CLK_APB0_UART1>, <&ccu1 CLK_CPU_UART1>;
f2b1c507	235	clock-names = "uartclk", "reg";
804a5dd6 JE	236	status = "disabled";
	237	};
	238
5d2ea79c JE	239	ssp0: spi@40083000 {
	240	compatible = "arm,pl022", "arm,primecell";
	241	reg = <0x40083000 0x1000>;
	242	interrupts = <22>;
	243	clocks = <&ccu2 CLK_APB0_SSP0>, <&ccu1 CLK_CPU_SSP0>;
	244	clock-names = "sspclk", "apb_pclk";
	245	#address-cells = <1>;
	246	#size-cells = <0>;
	247	status = "disabled";
	248	};
	249
804a5dd6 JE	250	timer0: timer@40084000 {
	251	compatible = "nxp,lpc3220-timer";
	252	reg = <0x40084000 0x1000>;
	253	interrupts = <12>;
ba2db535	254	clocks = <&ccu1 CLK_CPU_TIMER0>;
804a5dd6 JE	255	clock-names = "timerclk";
	256	};
	257
	258	timer1: timer@40085000 {
	259	compatible = "nxp,lpc3220-timer";
	260	reg = <0x40085000 0x1000>;
	261	interrupts = <13>;
ba2db535	262	clocks = <&ccu1 CLK_CPU_TIMER1>;
804a5dd6 JE	263	clock-names = "timerclk";
	264	};
	265
d881f5e2 JE	266	pinctrl: pinctrl@40086000 {
	267	compatible = "nxp,lpc1850-scu";
	268	reg = <0x40086000 0x1000>;
	269	clocks = <&ccu1 CLK_CPU_SCU>;
	270	};
	271
7e6c8376 JE	272	can1: can@400a4000 {
	273	compatible = "bosch,c_can";
	274	reg = <0x400a4000 0x1000>;
	275	interrupts = <43>;
	276	clocks = <&ccu1 CLK_APB1_CAN1>;
	277	status = "disabled";
	278	};
	279
804a5dd6	280	uart2: serial@400c1000 {
f2b1c507	281	compatible = "nxp,lpc1850-uart", "ns16550a";
804a5dd6 JE	282	reg = <0x400c1000 0x1000>;
	283	reg-shift = <2>;
	284	interrupts = <26>;
ba2db535	285	clocks = <&ccu2 CLK_APB2_UART2>, <&ccu1 CLK_CPU_UART2>;
f2b1c507	286	clock-names = "uartclk", "reg";
804a5dd6 JE	287	status = "disabled";
	288	};
	289
	290	uart3: serial@400c2000 {
f2b1c507	291	compatible = "nxp,lpc1850-uart", "ns16550a";
804a5dd6 JE	292	reg = <0x400c2000 0x1000>;
	293	reg-shift = <2>;
	294	interrupts = <27>;
ba2db535	295	clocks = <&ccu2 CLK_APB2_UART3>, <&ccu1 CLK_CPU_UART3>;
f2b1c507	296	clock-names = "uartclk", "reg";
804a5dd6 JE	297	status = "disabled";
	298	};
	299
	300	timer2: timer@400c3000 {
	301	compatible = "nxp,lpc3220-timer";
	302	reg = <0x400c3000 0x1000>;
	303	interrupts = <14>;
ba2db535	304	clocks = <&ccu1 CLK_CPU_TIMER2>;
804a5dd6 JE	305	clock-names = "timerclk";
	306	};
	307
	308	timer3: timer@400c4000 {
	309	compatible = "nxp,lpc3220-timer";
	310	reg = <0x400c4000 0x1000>;
	311	interrupts = <15>;
ba2db535	312	clocks = <&ccu1 CLK_CPU_TIMER3>;
804a5dd6 JE	313	clock-names = "timerclk";
804a5dd6 JE	314	};
7836dce4	315
5d2ea79c JE	316	ssp1: spi@400c5000 {
	317	compatible = "arm,pl022", "arm,primecell";
	318	reg = <0x400c5000 0x1000>;
	319	interrupts = <23>;
	320	clocks = <&ccu2 CLK_APB2_SSP1>, <&ccu1 CLK_CPU_SSP1>;
	321	clock-names = "sspclk", "apb_pclk";
	322	#address-cells = <1>;
	323	#size-cells = <0>;
	324	status = "disabled";
	325	};
	326
7e6c8376 JE	327	can0: can@400e2000 {
	328	compatible = "bosch,c_can";
	329	reg = <0x400e2000 0x1000>;
	330	interrupts = <51>;
	331	clocks = <&ccu1 CLK_APB3_CAN0>;
	332	status = "disabled";
	333	};
	334
7836dce4 JE	335	gpio: gpio@400f4000 {
	336	compatible = "nxp,lpc1850-gpio";
	337	reg = <0x400f4000 0x4000>;
	338	clocks = <&ccu1 CLK_CPU_GPIO>;
	339	gpio-controller;
	340	#gpio-cells = <2>;
	341	gpio-ranges = <&pinctrl LPC_GPIO(0,0) LPC_PIN(0,0) 2>,
	342	<&pinctrl LPC_GPIO(0,4) LPC_PIN(1,0) 1>,
	343	<&pinctrl LPC_GPIO(0,8) LPC_PIN(1,1) 4>,
	344	<&pinctrl LPC_GPIO(1,8) LPC_PIN(1,5) 2>,
	345	<&pinctrl LPC_GPIO(1,0) LPC_PIN(1,7) 8>,
	346	<&pinctrl LPC_GPIO(0,2) LPC_PIN(1,15) 2>,
	347	<&pinctrl LPC_GPIO(0,12) LPC_PIN(1,17) 2>,
	348	<&pinctrl LPC_GPIO(0,15) LPC_PIN(1,20) 1>,
	349	<&pinctrl LPC_GPIO(5,0) LPC_PIN(2,0) 7>,
	350	<&pinctrl LPC_GPIO(0,7) LPC_PIN(2,7) 1>,
	351	<&pinctrl LPC_GPIO(5,7) LPC_PIN(2,8) 1>,
	352	<&pinctrl LPC_GPIO(1,10) LPC_PIN(2,9) 1>,
	353	<&pinctrl LPC_GPIO(0,14) LPC_PIN(2,10) 1>,
	354	<&pinctrl LPC_GPIO(1,11) LPC_PIN(2,11) 3>,
	355	<&pinctrl LPC_GPIO(5,8) LPC_PIN(3,1) 2>,
	356	<&pinctrl LPC_GPIO(1,14) LPC_PIN(3,4) 2>,
	357	<&pinctrl LPC_GPIO(0,6) LPC_PIN(3,6) 1>,
	358	<&pinctrl LPC_GPIO(5,10) LPC_PIN(3,7) 2>,
	359	<&pinctrl LPC_GPIO(2,0) LPC_PIN(4,0) 7>,
	360	<&pinctrl LPC_GPIO(5,12) LPC_PIN(4,8) 3>,
	361	<&pinctrl LPC_GPIO(2,9) LPC_PIN(5,0) 7>,
	362	<&pinctrl LPC_GPIO(2,7) LPC_PIN(5,7) 1>,
	363	<&pinctrl LPC_GPIO(3,0) LPC_PIN(6,1) 5>,
	364	<&pinctrl LPC_GPIO(0,5) LPC_PIN(6,6) 1>,
	365	<&pinctrl LPC_GPIO(5,15) LPC_PIN(6,7) 2>,
	366	<&pinctrl LPC_GPIO(3,5) LPC_PIN(6,9) 3>,
	367	<&pinctrl LPC_GPIO(2,8) LPC_PIN(6,12) 1>,
	368	<&pinctrl LPC_GPIO(3,8) LPC_PIN(7,0) 8>,
	369	<&pinctrl LPC_GPIO(4,0) LPC_PIN(8,0) 8>,
	370	<&pinctrl LPC_GPIO(4,12) LPC_PIN(9,0) 4>,
	371	<&pinctrl LPC_GPIO(5,17) LPC_PIN(9,4) 2>,
	372	<&pinctrl LPC_GPIO(4,11) LPC_PIN(9,6) 1>,
	373	<&pinctrl LPC_GPIO(4,8) LPC_PIN(a,1) 3>,
	374	<&pinctrl LPC_GPIO(5,19) LPC_PIN(a,4) 1>,
	375	<&pinctrl LPC_GPIO(5,20) LPC_PIN(b,0) 7>,
	376	<&pinctrl LPC_GPIO(6,0) LPC_PIN(c,1) 14>,
	377	<&pinctrl LPC_GPIO(6,14) LPC_PIN(d,0) 17>,
	378	<&pinctrl LPC_GPIO(7,0) LPC_PIN(e,0) 16>,
	379	<&pinctrl LPC_GPIO(7,16) LPC_PIN(f,1) 3>,
	380	<&pinctrl LPC_GPIO(7,19) LPC_PIN(f,5) 7>;
	381	};
804a5dd6 JE	382	};
804a5dd6 JE	383	};