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a2067676 MK |
1 | /* |
2 | * Copyright 2013-2014 Texas Instruments, Inc. | |
3 | * | |
4 | * Keystone 2 Kepler/Hawking SoC clock nodes | |
5 | * | |
6 | * This program is free software; you can redistribute it and/or modify | |
7 | * it under the terms of the GNU General Public License version 2 as | |
8 | * published by the Free Software Foundation. | |
9 | */ | |
10 | ||
11 | clocks { | |
12 | armpllclk: armpllclk@2620370 { | |
13 | #clock-cells = <0>; | |
14 | compatible = "ti,keystone,pll-clock"; | |
15 | clocks = <&refclkarm>; | |
16 | clock-output-names = "arm-pll-clk"; | |
17 | reg = <0x02620370 4>; | |
18 | reg-names = "control"; | |
19 | }; | |
20 | ||
21 | mainpllclk: mainpllclk@2310110 { | |
22 | #clock-cells = <0>; | |
23 | compatible = "ti,keystone,main-pll-clock"; | |
24 | clocks = <&refclksys>; | |
25 | reg = <0x02620350 4>, <0x02310110 4>; | |
26 | reg-names = "control", "multiplier"; | |
27 | fixed-postdiv = <2>; | |
28 | }; | |
29 | ||
30 | papllclk: papllclk@2620358 { | |
31 | #clock-cells = <0>; | |
32 | compatible = "ti,keystone,pll-clock"; | |
33 | clocks = <&refclkpass>; | |
34 | clock-output-names = "pa-pll-clk"; | |
35 | reg = <0x02620358 4>; | |
36 | reg-names = "control"; | |
37 | }; | |
38 | ||
39 | ddr3apllclk: ddr3apllclk@2620360 { | |
40 | #clock-cells = <0>; | |
41 | compatible = "ti,keystone,pll-clock"; | |
42 | clocks = <&refclkddr3a>; | |
43 | clock-output-names = "ddr-3a-pll-clk"; | |
44 | reg = <0x02620360 4>; | |
45 | reg-names = "control"; | |
46 | }; | |
47 | ||
48 | ddr3bpllclk: ddr3bpllclk@2620368 { | |
49 | #clock-cells = <0>; | |
50 | compatible = "ti,keystone,pll-clock"; | |
51 | clocks = <&refclkddr3b>; | |
52 | clock-output-names = "ddr-3b-pll-clk"; | |
53 | reg = <0x02620368 4>; | |
54 | reg-names = "control"; | |
55 | }; | |
56 | ||
57 | clktsip: clktsip { | |
58 | #clock-cells = <0>; | |
59 | compatible = "ti,keystone,psc-clock"; | |
60 | clocks = <&chipclk16>; | |
61 | clock-output-names = "tsip"; | |
1f9f5201 | 62 | reg = <0x02350000 0xb00>, <0x02350000 0x400>; |
a2067676 MK |
63 | reg-names = "control", "domain"; |
64 | domain-id = <0>; | |
65 | }; | |
66 | ||
67 | clksrio: clksrio { | |
68 | #clock-cells = <0>; | |
69 | compatible = "ti,keystone,psc-clock"; | |
70 | clocks = <&chipclk1rstiso13>; | |
71 | clock-output-names = "srio"; | |
72 | reg = <0x0235002c 0xb00>, <0x02350010 0x400>; | |
73 | reg-names = "control", "domain"; | |
74 | domain-id = <4>; | |
75 | }; | |
76 | ||
77 | clkhyperlink0: clkhyperlink0 { | |
78 | #clock-cells = <0>; | |
79 | compatible = "ti,keystone,psc-clock"; | |
80 | clocks = <&chipclk12>; | |
81 | clock-output-names = "hyperlink-0"; | |
82 | reg = <0x02350030 0xb00>, <0x02350014 0x400>; | |
83 | reg-names = "control", "domain"; | |
84 | domain-id = <5>; | |
85 | }; | |
86 | ||
87 | clkgem1: clkgem1 { | |
88 | #clock-cells = <0>; | |
89 | compatible = "ti,keystone,psc-clock"; | |
90 | clocks = <&chipclk1>; | |
91 | clock-output-names = "gem1"; | |
92 | reg = <0x02350040 0xb00>, <0x02350024 0x400>; | |
93 | reg-names = "control", "domain"; | |
94 | domain-id = <9>; | |
95 | }; | |
96 | ||
97 | clkgem2: clkgem2 { | |
98 | #clock-cells = <0>; | |
99 | compatible = "ti,keystone,psc-clock"; | |
100 | clocks = <&chipclk1>; | |
101 | clock-output-names = "gem2"; | |
102 | reg = <0x02350044 0xb00>, <0x02350028 0x400>; | |
103 | reg-names = "control", "domain"; | |
104 | domain-id = <10>; | |
105 | }; | |
106 | ||
107 | clkgem3: clkgem3 { | |
108 | #clock-cells = <0>; | |
109 | compatible = "ti,keystone,psc-clock"; | |
110 | clocks = <&chipclk1>; | |
111 | clock-output-names = "gem3"; | |
112 | reg = <0x02350048 0xb00>, <0x0235002c 0x400>; | |
113 | reg-names = "control", "domain"; | |
114 | domain-id = <11>; | |
115 | }; | |
116 | ||
117 | clkgem4: clkgem4 { | |
118 | #clock-cells = <0>; | |
119 | compatible = "ti,keystone,psc-clock"; | |
120 | clocks = <&chipclk1>; | |
121 | clock-output-names = "gem4"; | |
122 | reg = <0x0235004c 0xb00>, <0x02350030 0x400>; | |
123 | reg-names = "control", "domain"; | |
124 | domain-id = <12>; | |
125 | }; | |
126 | ||
127 | clkgem5: clkgem5 { | |
128 | #clock-cells = <0>; | |
129 | compatible = "ti,keystone,psc-clock"; | |
130 | clocks = <&chipclk1>; | |
131 | clock-output-names = "gem5"; | |
132 | reg = <0x02350050 0xb00>, <0x02350034 0x400>; | |
133 | reg-names = "control", "domain"; | |
134 | domain-id = <13>; | |
135 | }; | |
136 | ||
137 | clkgem6: clkgem6 { | |
138 | #clock-cells = <0>; | |
139 | compatible = "ti,keystone,psc-clock"; | |
140 | clocks = <&chipclk1>; | |
141 | clock-output-names = "gem6"; | |
142 | reg = <0x02350054 0xb00>, <0x02350038 0x400>; | |
143 | reg-names = "control", "domain"; | |
144 | domain-id = <14>; | |
145 | }; | |
146 | ||
147 | clkgem7: clkgem7 { | |
148 | #clock-cells = <0>; | |
149 | compatible = "ti,keystone,psc-clock"; | |
150 | clocks = <&chipclk1>; | |
151 | clock-output-names = "gem7"; | |
152 | reg = <0x02350058 0xb00>, <0x0235003c 0x400>; | |
153 | reg-names = "control", "domain"; | |
154 | domain-id = <15>; | |
155 | }; | |
156 | ||
157 | clkddr31: clkddr31 { | |
158 | #clock-cells = <0>; | |
159 | compatible = "ti,keystone,psc-clock"; | |
160 | clocks = <&chipclk13>; | |
161 | clock-output-names = "ddr3-1"; | |
162 | reg = <0x02350060 0xb00>, <0x02350040 0x400>; | |
163 | reg-names = "control", "domain"; | |
164 | domain-id = <16>; | |
165 | }; | |
166 | ||
167 | clktac: clktac { | |
168 | #clock-cells = <0>; | |
169 | compatible = "ti,keystone,psc-clock"; | |
170 | clocks = <&chipclk13>; | |
171 | clock-output-names = "tac"; | |
172 | reg = <0x02350064 0xb00>, <0x02350044 0x400>; | |
173 | reg-names = "control", "domain"; | |
174 | domain-id = <17>; | |
175 | }; | |
176 | ||
177 | clkrac01: clkrac01 { | |
178 | #clock-cells = <0>; | |
179 | compatible = "ti,keystone,psc-clock"; | |
180 | clocks = <&chipclk13>; | |
181 | clock-output-names = "rac-01"; | |
182 | reg = <0x02350068 0xb00>, <0x02350044 0x400>; | |
183 | reg-names = "control", "domain"; | |
184 | domain-id = <17>; | |
185 | }; | |
186 | ||
187 | clkrac23: clkrac23 { | |
188 | #clock-cells = <0>; | |
189 | compatible = "ti,keystone,psc-clock"; | |
190 | clocks = <&chipclk13>; | |
191 | clock-output-names = "rac-23"; | |
192 | reg = <0x0235006c 0xb00>, <0x02350048 0x400>; | |
193 | reg-names = "control", "domain"; | |
194 | domain-id = <18>; | |
195 | }; | |
196 | ||
197 | clkfftc0: clkfftc0 { | |
198 | #clock-cells = <0>; | |
199 | compatible = "ti,keystone,psc-clock"; | |
200 | clocks = <&chipclk13>; | |
201 | clock-output-names = "fftc-0"; | |
202 | reg = <0x02350070 0xb00>, <0x0235004c 0x400>; | |
203 | reg-names = "control", "domain"; | |
204 | domain-id = <19>; | |
205 | }; | |
206 | ||
207 | clkfftc1: clkfftc1 { | |
208 | #clock-cells = <0>; | |
209 | compatible = "ti,keystone,psc-clock"; | |
210 | clocks = <&chipclk13>; | |
211 | clock-output-names = "fftc-1"; | |
754f67cd | 212 | reg = <0x02350074 0xb00>, <0x0235004c 0x400>; |
a2067676 MK |
213 | reg-names = "control", "domain"; |
214 | domain-id = <19>; | |
215 | }; | |
216 | ||
217 | clkfftc2: clkfftc2 { | |
218 | #clock-cells = <0>; | |
219 | compatible = "ti,keystone,psc-clock"; | |
220 | clocks = <&chipclk13>; | |
221 | clock-output-names = "fftc-2"; | |
222 | reg = <0x02350078 0xb00>, <0x02350050 0x400>; | |
223 | reg-names = "control", "domain"; | |
224 | domain-id = <20>; | |
225 | }; | |
226 | ||
227 | clkfftc3: clkfftc3 { | |
228 | #clock-cells = <0>; | |
229 | compatible = "ti,keystone,psc-clock"; | |
230 | clocks = <&chipclk13>; | |
231 | clock-output-names = "fftc-3"; | |
232 | reg = <0x0235007c 0xb00>, <0x02350050 0x400>; | |
233 | reg-names = "control", "domain"; | |
234 | domain-id = <20>; | |
235 | }; | |
236 | ||
237 | clkfftc4: clkfftc4 { | |
238 | #clock-cells = <0>; | |
239 | compatible = "ti,keystone,psc-clock"; | |
240 | clocks = <&chipclk13>; | |
241 | clock-output-names = "fftc-4"; | |
242 | reg = <0x02350080 0xb00>, <0x02350050 0x400>; | |
243 | reg-names = "control", "domain"; | |
244 | domain-id = <20>; | |
245 | }; | |
246 | ||
247 | clkfftc5: clkfftc5 { | |
248 | #clock-cells = <0>; | |
249 | compatible = "ti,keystone,psc-clock"; | |
250 | clocks = <&chipclk13>; | |
251 | clock-output-names = "fftc-5"; | |
252 | reg = <0x02350084 0xb00>, <0x02350050 0x400>; | |
253 | reg-names = "control", "domain"; | |
254 | domain-id = <20>; | |
255 | }; | |
256 | ||
257 | clkaif: clkaif { | |
258 | #clock-cells = <0>; | |
259 | compatible = "ti,keystone,psc-clock"; | |
260 | clocks = <&chipclk13>; | |
261 | clock-output-names = "aif"; | |
262 | reg = <0x02350088 0xb00>, <0x02350054 0x400>; | |
263 | reg-names = "control", "domain"; | |
264 | domain-id = <21>; | |
265 | }; | |
266 | ||
267 | clktcp3d0: clktcp3d0 { | |
268 | #clock-cells = <0>; | |
269 | compatible = "ti,keystone,psc-clock"; | |
270 | clocks = <&chipclk13>; | |
271 | clock-output-names = "tcp3d-0"; | |
272 | reg = <0x0235008c 0xb00>, <0x02350058 0x400>; | |
273 | reg-names = "control", "domain"; | |
274 | domain-id = <22>; | |
275 | }; | |
276 | ||
277 | clktcp3d1: clktcp3d1 { | |
278 | #clock-cells = <0>; | |
279 | compatible = "ti,keystone,psc-clock"; | |
280 | clocks = <&chipclk13>; | |
281 | clock-output-names = "tcp3d-1"; | |
282 | reg = <0x02350090 0xb00>, <0x02350058 0x400>; | |
283 | reg-names = "control", "domain"; | |
284 | domain-id = <22>; | |
285 | }; | |
286 | ||
287 | clktcp3d2: clktcp3d2 { | |
288 | #clock-cells = <0>; | |
289 | compatible = "ti,keystone,psc-clock"; | |
290 | clocks = <&chipclk13>; | |
291 | clock-output-names = "tcp3d-2"; | |
292 | reg = <0x02350094 0xb00>, <0x0235005c 0x400>; | |
293 | reg-names = "control", "domain"; | |
294 | domain-id = <23>; | |
295 | }; | |
296 | ||
297 | clktcp3d3: clktcp3d3 { | |
298 | #clock-cells = <0>; | |
299 | compatible = "ti,keystone,psc-clock"; | |
300 | clocks = <&chipclk13>; | |
301 | clock-output-names = "tcp3d-3"; | |
302 | reg = <0x02350098 0xb00>, <0x0235005c 0x400>; | |
303 | reg-names = "control", "domain"; | |
304 | domain-id = <23>; | |
305 | }; | |
306 | ||
307 | clkvcp0: clkvcp0 { | |
308 | #clock-cells = <0>; | |
309 | compatible = "ti,keystone,psc-clock"; | |
310 | clocks = <&chipclk13>; | |
311 | clock-output-names = "vcp-0"; | |
312 | reg = <0x0235009c 0xb00>, <0x02350060 0x400>; | |
313 | reg-names = "control", "domain"; | |
314 | domain-id = <24>; | |
315 | }; | |
316 | ||
317 | clkvcp1: clkvcp1 { | |
318 | #clock-cells = <0>; | |
319 | compatible = "ti,keystone,psc-clock"; | |
320 | clocks = <&chipclk13>; | |
321 | clock-output-names = "vcp-1"; | |
322 | reg = <0x023500a0 0xb00>, <0x02350060 0x400>; | |
323 | reg-names = "control", "domain"; | |
324 | domain-id = <24>; | |
325 | }; | |
326 | ||
327 | clkvcp2: clkvcp2 { | |
328 | #clock-cells = <0>; | |
329 | compatible = "ti,keystone,psc-clock"; | |
330 | clocks = <&chipclk13>; | |
331 | clock-output-names = "vcp-2"; | |
332 | reg = <0x023500a4 0xb00>, <0x02350060 0x400>; | |
333 | reg-names = "control", "domain"; | |
334 | domain-id = <24>; | |
335 | }; | |
336 | ||
337 | clkvcp3: clkvcp3 { | |
338 | #clock-cells = <0>; | |
339 | compatible = "ti,keystone,psc-clock"; | |
340 | clocks = <&chipclk13>; | |
341 | clock-output-names = "vcp-3"; | |
342 | reg = <0x023500a8 0xb00>, <0x02350060 0x400>; | |
343 | reg-names = "control", "domain"; | |
344 | domain-id = <24>; | |
345 | }; | |
346 | ||
347 | clkvcp4: clkvcp4 { | |
348 | #clock-cells = <0>; | |
349 | compatible = "ti,keystone,psc-clock"; | |
350 | clocks = <&chipclk13>; | |
351 | clock-output-names = "vcp-4"; | |
352 | reg = <0x023500ac 0xb00>, <0x02350064 0x400>; | |
353 | reg-names = "control", "domain"; | |
354 | domain-id = <25>; | |
355 | }; | |
356 | ||
357 | clkvcp5: clkvcp5 { | |
358 | #clock-cells = <0>; | |
359 | compatible = "ti,keystone,psc-clock"; | |
360 | clocks = <&chipclk13>; | |
361 | clock-output-names = "vcp-5"; | |
362 | reg = <0x023500b0 0xb00>, <0x02350064 0x400>; | |
363 | reg-names = "control", "domain"; | |
364 | domain-id = <25>; | |
365 | }; | |
366 | ||
367 | clkvcp6: clkvcp6 { | |
368 | #clock-cells = <0>; | |
369 | compatible = "ti,keystone,psc-clock"; | |
370 | clocks = <&chipclk13>; | |
371 | clock-output-names = "vcp-6"; | |
372 | reg = <0x023500b4 0xb00>, <0x02350064 0x400>; | |
373 | reg-names = "control", "domain"; | |
374 | domain-id = <25>; | |
375 | }; | |
376 | ||
377 | clkvcp7: clkvcp7 { | |
378 | #clock-cells = <0>; | |
379 | compatible = "ti,keystone,psc-clock"; | |
380 | clocks = <&chipclk13>; | |
381 | clock-output-names = "vcp-7"; | |
382 | reg = <0x023500b8 0xb00>, <0x02350064 0x400>; | |
383 | reg-names = "control", "domain"; | |
384 | domain-id = <25>; | |
385 | }; | |
386 | ||
387 | clkbcp: clkbcp { | |
388 | #clock-cells = <0>; | |
389 | compatible = "ti,keystone,psc-clock"; | |
390 | clocks = <&chipclk13>; | |
391 | clock-output-names = "bcp"; | |
392 | reg = <0x023500bc 0xb00>, <0x02350068 0x400>; | |
393 | reg-names = "control", "domain"; | |
394 | domain-id = <26>; | |
395 | }; | |
396 | ||
397 | clkdxb: clkdxb { | |
398 | #clock-cells = <0>; | |
399 | compatible = "ti,keystone,psc-clock"; | |
400 | clocks = <&chipclk13>; | |
401 | clock-output-names = "dxb"; | |
402 | reg = <0x023500c0 0xb00>, <0x0235006c 0x400>; | |
403 | reg-names = "control", "domain"; | |
404 | domain-id = <27>; | |
405 | }; | |
406 | ||
407 | clkhyperlink1: clkhyperlink1 { | |
408 | #clock-cells = <0>; | |
409 | compatible = "ti,keystone,psc-clock"; | |
410 | clocks = <&chipclk12>; | |
411 | clock-output-names = "hyperlink-1"; | |
412 | reg = <0x023500c4 0xb00>, <0x02350070 0x400>; | |
413 | reg-names = "control", "domain"; | |
414 | domain-id = <28>; | |
415 | }; | |
416 | ||
417 | clkxge: clkxge { | |
418 | #clock-cells = <0>; | |
419 | compatible = "ti,keystone,psc-clock"; | |
420 | clocks = <&chipclk13>; | |
421 | clock-output-names = "xge"; | |
422 | reg = <0x023500c8 0xb00>, <0x02350074 0x400>; | |
423 | reg-names = "control", "domain"; | |
424 | domain-id = <29>; | |
425 | }; | |
426 | }; |