Commit | Line | Data |
---|---|---|
b2441318 | 1 | // SPDX-License-Identifier: GPL-2.0 |
4980f9bc LW |
2 | /* |
3 | * Device Tree for the ARM Integrator/CP platform | |
4 | */ | |
5 | ||
6 | /dts-v1/; | |
7 | /include/ "integrator.dtsi" | |
8 | ||
9 | / { | |
10 | model = "ARM Integrator/CP"; | |
11 | compatible = "arm,integrator-cp"; | |
12 | ||
4980f9bc LW |
13 | chosen { |
14 | bootargs = "root=/dev/ram0 console=ttyAMA0,38400n8 earlyprintk"; | |
15 | }; | |
16 | ||
426610dd LW |
17 | cpus { |
18 | #address-cells = <1>; | |
19 | #size-cells = <0>; | |
20 | ||
21 | cpu@0 { | |
22 | device_type = "cpu"; | |
23 | /* | |
24 | * Since the board has pluggable CPU modules, we | |
25 | * cannot define a proper compatible here. Let the | |
26 | * boot loader fill in the apropriate compatible | |
27 | * string if necessary. | |
28 | */ | |
29 | /* compatible = "arm,arm920t"; */ | |
30 | reg = <0>; | |
31 | /* | |
32 | * TBD comment. | |
33 | */ | |
34 | /* kHz uV */ | |
35 | operating-points = <50000 0 | |
36 | 48000 0>; | |
37 | clocks = <&cmcore>; | |
38 | clock-names = "cpu"; | |
39 | clock-latency = <1000000>; /* 1 ms */ | |
40 | }; | |
41 | }; | |
42 | ||
b7929852 LW |
43 | /* |
44 | * The Integrator/CP overall clocking architecture can be found in | |
45 | * ARM DUI 0184B page 7-28 "Integrator/CP922T system clocks" which | |
46 | * appear to illustrate the layout used in most configurations. | |
47 | */ | |
48 | ||
49 | /* The codec chrystal operates at 24.576 MHz */ | |
50 | xtal_codec: xtal24.576@24.576M { | |
51 | #clock-cells = <0>; | |
52 | compatible = "fixed-clock"; | |
53 | clock-frequency = <24576000>; | |
54 | }; | |
55 | ||
56 | /* The chrystal is divided by 2 by the codec for the AACI bit clock */ | |
57 | aaci_bitclk: aaci_bitclk@12.288M { | |
58 | #clock-cells = <0>; | |
59 | compatible = "fixed-factor-clock"; | |
60 | clock-div = <2>; | |
61 | clock-mult = <1>; | |
62 | clocks = <&xtal_codec>; | |
63 | }; | |
64 | ||
65 | /* This is a 25MHz chrystal on the base board */ | |
66 | xtal25mhz: xtal25mhz@25M { | |
67 | #clock-cells = <0>; | |
68 | compatible = "fixed-clock"; | |
69 | clock-frequency = <25000000>; | |
70 | }; | |
71 | ||
72 | /* The UART clock is 14.74 MHz divided from 25MHz by an ICS525 */ | |
73 | uartclk: uartclk@14.74M { | |
74 | #clock-cells = <0>; | |
75 | compatible = "fixed-clock"; | |
76 | clock-frequency = <14745600>; | |
77 | }; | |
78 | ||
79 | /* Actually sysclk I think */ | |
80 | pclk: pclk@0 { | |
81 | #clock-cells = <0>; | |
82 | compatible = "fixed-clock"; | |
83 | clock-frequency = <0>; | |
84 | }; | |
85 | ||
86 | core-module@10000000 { | |
87 | /* 24 MHz chrystal on the core module */ | |
b2da116c | 88 | cm24mhz: cm24mhz@24M { |
b7929852 LW |
89 | #clock-cells = <0>; |
90 | compatible = "fixed-clock"; | |
91 | clock-frequency = <24000000>; | |
92 | }; | |
93 | ||
b2da116c LW |
94 | /* Oscillator on the core module, clocks the CPU core */ |
95 | cmcore: cmosc@24M { | |
96 | compatible = "arm,syscon-icst525-integratorcp-cm-core"; | |
b7929852 | 97 | #clock-cells = <0>; |
b2da116c LW |
98 | lock-offset = <0x14>; |
99 | vco-offset = <0x08>; | |
100 | clocks = <&cm24mhz>; | |
101 | }; | |
102 | ||
103 | /* Oscillator on the core module, clocks the memory bus */ | |
104 | cmmem: cmosc@24M { | |
105 | compatible = "arm,syscon-icst525-integratorcp-cm-mem"; | |
106 | #clock-cells = <0>; | |
107 | lock-offset = <0x14>; | |
108 | vco-offset = <0x08>; | |
109 | clocks = <&cm24mhz>; | |
110 | }; | |
111 | ||
112 | /* Auxilary oscillator on the core module, clocks the CLCD */ | |
113 | auxosc: auxosc@24M { | |
114 | compatible = "arm,syscon-icst525"; | |
b7929852 | 115 | #clock-cells = <0>; |
b2da116c LW |
116 | lock-offset = <0x14>; |
117 | vco-offset = <0x1c>; | |
118 | clocks = <&cm24mhz>; | |
b7929852 LW |
119 | }; |
120 | ||
121 | /* The KMI clock is the 24 MHz oscillator divided to 8MHz */ | |
122 | kmiclk: kmiclk@1M { | |
123 | #clock-cells = <0>; | |
124 | compatible = "fixed-factor-clock"; | |
125 | clock-div = <3>; | |
126 | clock-mult = <1>; | |
b2da116c | 127 | clocks = <&cm24mhz>; |
b7929852 LW |
128 | }; |
129 | ||
130 | /* The timer clock is the 24 MHz oscillator divided to 1MHz */ | |
131 | timclk: timclk@1M { | |
132 | #clock-cells = <0>; | |
133 | compatible = "fixed-factor-clock"; | |
134 | clock-div = <24>; | |
135 | clock-mult = <1>; | |
b2da116c | 136 | clocks = <&cm24mhz>; |
b7929852 LW |
137 | }; |
138 | }; | |
139 | ||
df36680f | 140 | syscon { |
83e484fc | 141 | compatible = "arm,integrator-cp-syscon", "syscon"; |
64100a03 LW |
142 | reg = <0xcb000000 0x100>; |
143 | }; | |
144 | ||
4980f9bc | 145 | timer0: timer@13000000 { |
b7929852 | 146 | /* TIMER0 runs directly on the 25MHz chrystal */ |
870e2928 | 147 | compatible = "arm,integrator-cp-timer"; |
b7929852 | 148 | clocks = <&xtal25mhz>; |
4980f9bc LW |
149 | }; |
150 | ||
151 | timer1: timer@13000100 { | |
29114fd7 | 152 | /* TIMER1 runs @ 1MHz */ |
870e2928 | 153 | compatible = "arm,integrator-cp-timer"; |
b7929852 | 154 | clocks = <&timclk>; |
4980f9bc LW |
155 | }; |
156 | ||
157 | timer2: timer@13000200 { | |
29114fd7 | 158 | /* TIMER2 runs @ 1MHz */ |
870e2928 | 159 | compatible = "arm,integrator-cp-timer"; |
b7929852 | 160 | clocks = <&timclk>; |
4980f9bc LW |
161 | }; |
162 | ||
163 | pic: pic@14000000 { | |
164 | valid-mask = <0x1fc003ff>; | |
165 | }; | |
166 | ||
167 | cic: cic@10000040 { | |
168 | compatible = "arm,versatile-fpga-irq"; | |
169 | #interrupt-cells = <1>; | |
170 | interrupt-controller; | |
171 | reg = <0x10000040 0x100>; | |
172 | clear-mask = <0xffffffff>; | |
173 | valid-mask = <0x00000007>; | |
174 | }; | |
175 | ||
8f6344fa | 176 | /* The SIC is cascaded off IRQ 26 on the PIC */ |
4980f9bc LW |
177 | sic: sic@ca000000 { |
178 | compatible = "arm,versatile-fpga-irq"; | |
8f6344fa LW |
179 | interrupt-parent = <&pic>; |
180 | interrupts = <26>; | |
4980f9bc LW |
181 | #interrupt-cells = <1>; |
182 | interrupt-controller; | |
183 | reg = <0xca000000 0x100>; | |
184 | clear-mask = <0x00000fff>; | |
185 | valid-mask = <0x00000fff>; | |
186 | }; | |
4672cddf | 187 | |
73efd530 LW |
188 | ethernet@c8000000 { |
189 | compatible = "smsc,lan91c111"; | |
190 | reg = <0xc8000000 0x10>; | |
191 | interrupt-parent = <&pic>; | |
192 | interrupts = <27>; | |
193 | }; | |
194 | ||
4672cddf LW |
195 | fpga { |
196 | /* | |
197 | * These PrimeCells are at the same location and using | |
198 | * the same interrupts in all Integrators, but in the CP | |
199 | * slightly newer versions are deployed. | |
200 | */ | |
201 | rtc@15000000 { | |
202 | compatible = "arm,pl031", "arm,primecell"; | |
b7929852 LW |
203 | clocks = <&pclk>; |
204 | clock-names = "apb_pclk"; | |
4672cddf LW |
205 | }; |
206 | ||
207 | uart@16000000 { | |
208 | compatible = "arm,pl011", "arm,primecell"; | |
b7929852 LW |
209 | clocks = <&uartclk>, <&pclk>; |
210 | clock-names = "uartclk", "apb_pclk"; | |
4672cddf LW |
211 | }; |
212 | ||
213 | uart@17000000 { | |
214 | compatible = "arm,pl011", "arm,primecell"; | |
b7929852 LW |
215 | clocks = <&uartclk>, <&pclk>; |
216 | clock-names = "uartclk", "apb_pclk"; | |
4672cddf LW |
217 | }; |
218 | ||
219 | kmi@18000000 { | |
220 | compatible = "arm,pl050", "arm,primecell"; | |
b7929852 LW |
221 | clocks = <&kmiclk>, <&pclk>; |
222 | clock-names = "KMIREFCLK", "apb_pclk"; | |
4672cddf LW |
223 | }; |
224 | ||
225 | kmi@19000000 { | |
226 | compatible = "arm,pl050", "arm,primecell"; | |
b7929852 LW |
227 | clocks = <&kmiclk>, <&pclk>; |
228 | clock-names = "KMIREFCLK", "apb_pclk"; | |
4672cddf LW |
229 | }; |
230 | ||
231 | /* | |
232 | * These PrimeCells are only available on the Integrator/CP | |
233 | */ | |
234 | mmc@1c000000 { | |
235 | compatible = "arm,pl180", "arm,primecell"; | |
236 | reg = <0x1c000000 0x1000>; | |
237 | interrupts = <23 24>; | |
238 | max-frequency = <515633>; | |
b7929852 LW |
239 | clocks = <&uartclk>, <&pclk>; |
240 | clock-names = "mclk", "apb_pclk"; | |
4672cddf LW |
241 | }; |
242 | ||
243 | aaci@1d000000 { | |
244 | compatible = "arm,pl041", "arm,primecell"; | |
245 | reg = <0x1d000000 0x1000>; | |
246 | interrupts = <25>; | |
b7929852 LW |
247 | clocks = <&pclk>; |
248 | clock-names = "apb_pclk"; | |
4672cddf LW |
249 | }; |
250 | ||
251 | clcd@c0000000 { | |
252 | compatible = "arm,pl110", "arm,primecell"; | |
253 | reg = <0xC0000000 0x1000>; | |
254 | interrupts = <22>; | |
b7929852 | 255 | clocks = <&auxosc>, <&pclk>; |
e3f61760 LW |
256 | clock-names = "clcdclk", "apb_pclk"; |
257 | ||
258 | port { | |
259 | /* | |
260 | * The VGA connected is implemented with a | |
261 | * THS8134A triple DAC that can be run in 24bit | |
262 | * or 16bit RGB mode. | |
263 | */ | |
264 | clcd_pads: endpoint { | |
265 | remote-endpoint = <&clcd_panel>; | |
266 | arm,pl11x,tft-r0g0b0-pads = <1 7 13>; | |
267 | }; | |
268 | }; | |
269 | ||
270 | panel { | |
271 | compatible = "panel-dpi"; | |
272 | ||
273 | port { | |
274 | clcd_panel: endpoint { | |
275 | remote-endpoint = <&clcd_pads>; | |
276 | }; | |
277 | }; | |
278 | ||
279 | /* Standard 640x480 VGA timings */ | |
280 | panel-timing { | |
281 | clock-frequency = <25175000>; | |
282 | hactive = <640>; | |
283 | hback-porch = <48>; | |
284 | hfront-porch = <16>; | |
285 | hsync-len = <96>; | |
286 | vactive = <480>; | |
287 | vback-porch = <33>; | |
288 | vfront-porch = <10>; | |
289 | vsync-len = <2>; | |
290 | }; | |
291 | }; | |
4672cddf LW |
292 | }; |
293 | }; | |
4980f9bc | 294 | }; |