Commit | Line | Data |
---|---|---|
4980f9bc LW |
1 | /* |
2 | * Device Tree for the ARM Integrator/CP platform | |
3 | */ | |
4 | ||
5 | /dts-v1/; | |
6 | /include/ "integrator.dtsi" | |
7 | ||
8 | / { | |
9 | model = "ARM Integrator/CP"; | |
10 | compatible = "arm,integrator-cp"; | |
11 | ||
4980f9bc LW |
12 | chosen { |
13 | bootargs = "root=/dev/ram0 console=ttyAMA0,38400n8 earlyprintk"; | |
14 | }; | |
15 | ||
426610dd LW |
16 | cpus { |
17 | #address-cells = <1>; | |
18 | #size-cells = <0>; | |
19 | ||
20 | cpu@0 { | |
21 | device_type = "cpu"; | |
22 | /* | |
23 | * Since the board has pluggable CPU modules, we | |
24 | * cannot define a proper compatible here. Let the | |
25 | * boot loader fill in the apropriate compatible | |
26 | * string if necessary. | |
27 | */ | |
28 | /* compatible = "arm,arm920t"; */ | |
29 | reg = <0>; | |
30 | /* | |
31 | * TBD comment. | |
32 | */ | |
33 | /* kHz uV */ | |
34 | operating-points = <50000 0 | |
35 | 48000 0>; | |
36 | clocks = <&cmcore>; | |
37 | clock-names = "cpu"; | |
38 | clock-latency = <1000000>; /* 1 ms */ | |
39 | }; | |
40 | }; | |
41 | ||
b7929852 LW |
42 | /* |
43 | * The Integrator/CP overall clocking architecture can be found in | |
44 | * ARM DUI 0184B page 7-28 "Integrator/CP922T system clocks" which | |
45 | * appear to illustrate the layout used in most configurations. | |
46 | */ | |
47 | ||
48 | /* The codec chrystal operates at 24.576 MHz */ | |
49 | xtal_codec: xtal24.576@24.576M { | |
50 | #clock-cells = <0>; | |
51 | compatible = "fixed-clock"; | |
52 | clock-frequency = <24576000>; | |
53 | }; | |
54 | ||
55 | /* The chrystal is divided by 2 by the codec for the AACI bit clock */ | |
56 | aaci_bitclk: aaci_bitclk@12.288M { | |
57 | #clock-cells = <0>; | |
58 | compatible = "fixed-factor-clock"; | |
59 | clock-div = <2>; | |
60 | clock-mult = <1>; | |
61 | clocks = <&xtal_codec>; | |
62 | }; | |
63 | ||
64 | /* This is a 25MHz chrystal on the base board */ | |
65 | xtal25mhz: xtal25mhz@25M { | |
66 | #clock-cells = <0>; | |
67 | compatible = "fixed-clock"; | |
68 | clock-frequency = <25000000>; | |
69 | }; | |
70 | ||
71 | /* The UART clock is 14.74 MHz divided from 25MHz by an ICS525 */ | |
72 | uartclk: uartclk@14.74M { | |
73 | #clock-cells = <0>; | |
74 | compatible = "fixed-clock"; | |
75 | clock-frequency = <14745600>; | |
76 | }; | |
77 | ||
78 | /* Actually sysclk I think */ | |
79 | pclk: pclk@0 { | |
80 | #clock-cells = <0>; | |
81 | compatible = "fixed-clock"; | |
82 | clock-frequency = <0>; | |
83 | }; | |
84 | ||
85 | core-module@10000000 { | |
86 | /* 24 MHz chrystal on the core module */ | |
b2da116c | 87 | cm24mhz: cm24mhz@24M { |
b7929852 LW |
88 | #clock-cells = <0>; |
89 | compatible = "fixed-clock"; | |
90 | clock-frequency = <24000000>; | |
91 | }; | |
92 | ||
b2da116c LW |
93 | /* Oscillator on the core module, clocks the CPU core */ |
94 | cmcore: cmosc@24M { | |
95 | compatible = "arm,syscon-icst525-integratorcp-cm-core"; | |
b7929852 | 96 | #clock-cells = <0>; |
b2da116c LW |
97 | lock-offset = <0x14>; |
98 | vco-offset = <0x08>; | |
99 | clocks = <&cm24mhz>; | |
100 | }; | |
101 | ||
102 | /* Oscillator on the core module, clocks the memory bus */ | |
103 | cmmem: cmosc@24M { | |
104 | compatible = "arm,syscon-icst525-integratorcp-cm-mem"; | |
105 | #clock-cells = <0>; | |
106 | lock-offset = <0x14>; | |
107 | vco-offset = <0x08>; | |
108 | clocks = <&cm24mhz>; | |
109 | }; | |
110 | ||
111 | /* Auxilary oscillator on the core module, clocks the CLCD */ | |
112 | auxosc: auxosc@24M { | |
113 | compatible = "arm,syscon-icst525"; | |
b7929852 | 114 | #clock-cells = <0>; |
b2da116c LW |
115 | lock-offset = <0x14>; |
116 | vco-offset = <0x1c>; | |
117 | clocks = <&cm24mhz>; | |
b7929852 LW |
118 | }; |
119 | ||
120 | /* The KMI clock is the 24 MHz oscillator divided to 8MHz */ | |
121 | kmiclk: kmiclk@1M { | |
122 | #clock-cells = <0>; | |
123 | compatible = "fixed-factor-clock"; | |
124 | clock-div = <3>; | |
125 | clock-mult = <1>; | |
b2da116c | 126 | clocks = <&cm24mhz>; |
b7929852 LW |
127 | }; |
128 | ||
129 | /* The timer clock is the 24 MHz oscillator divided to 1MHz */ | |
130 | timclk: timclk@1M { | |
131 | #clock-cells = <0>; | |
132 | compatible = "fixed-factor-clock"; | |
133 | clock-div = <24>; | |
134 | clock-mult = <1>; | |
b2da116c | 135 | clocks = <&cm24mhz>; |
b7929852 LW |
136 | }; |
137 | }; | |
138 | ||
df36680f | 139 | syscon { |
83e484fc | 140 | compatible = "arm,integrator-cp-syscon", "syscon"; |
64100a03 LW |
141 | reg = <0xcb000000 0x100>; |
142 | }; | |
143 | ||
4980f9bc | 144 | timer0: timer@13000000 { |
b7929852 | 145 | /* TIMER0 runs directly on the 25MHz chrystal */ |
870e2928 | 146 | compatible = "arm,integrator-cp-timer"; |
b7929852 | 147 | clocks = <&xtal25mhz>; |
4980f9bc LW |
148 | }; |
149 | ||
150 | timer1: timer@13000100 { | |
29114fd7 | 151 | /* TIMER1 runs @ 1MHz */ |
870e2928 | 152 | compatible = "arm,integrator-cp-timer"; |
b7929852 | 153 | clocks = <&timclk>; |
4980f9bc LW |
154 | }; |
155 | ||
156 | timer2: timer@13000200 { | |
29114fd7 | 157 | /* TIMER2 runs @ 1MHz */ |
870e2928 | 158 | compatible = "arm,integrator-cp-timer"; |
b7929852 | 159 | clocks = <&timclk>; |
4980f9bc LW |
160 | }; |
161 | ||
162 | pic: pic@14000000 { | |
163 | valid-mask = <0x1fc003ff>; | |
164 | }; | |
165 | ||
166 | cic: cic@10000040 { | |
167 | compatible = "arm,versatile-fpga-irq"; | |
168 | #interrupt-cells = <1>; | |
169 | interrupt-controller; | |
170 | reg = <0x10000040 0x100>; | |
171 | clear-mask = <0xffffffff>; | |
172 | valid-mask = <0x00000007>; | |
173 | }; | |
174 | ||
8f6344fa | 175 | /* The SIC is cascaded off IRQ 26 on the PIC */ |
4980f9bc LW |
176 | sic: sic@ca000000 { |
177 | compatible = "arm,versatile-fpga-irq"; | |
8f6344fa LW |
178 | interrupt-parent = <&pic>; |
179 | interrupts = <26>; | |
4980f9bc LW |
180 | #interrupt-cells = <1>; |
181 | interrupt-controller; | |
182 | reg = <0xca000000 0x100>; | |
183 | clear-mask = <0x00000fff>; | |
184 | valid-mask = <0x00000fff>; | |
185 | }; | |
4672cddf | 186 | |
73efd530 LW |
187 | ethernet@c8000000 { |
188 | compatible = "smsc,lan91c111"; | |
189 | reg = <0xc8000000 0x10>; | |
190 | interrupt-parent = <&pic>; | |
191 | interrupts = <27>; | |
192 | }; | |
193 | ||
4672cddf LW |
194 | fpga { |
195 | /* | |
196 | * These PrimeCells are at the same location and using | |
197 | * the same interrupts in all Integrators, but in the CP | |
198 | * slightly newer versions are deployed. | |
199 | */ | |
200 | rtc@15000000 { | |
201 | compatible = "arm,pl031", "arm,primecell"; | |
b7929852 LW |
202 | clocks = <&pclk>; |
203 | clock-names = "apb_pclk"; | |
4672cddf LW |
204 | }; |
205 | ||
206 | uart@16000000 { | |
207 | compatible = "arm,pl011", "arm,primecell"; | |
b7929852 LW |
208 | clocks = <&uartclk>, <&pclk>; |
209 | clock-names = "uartclk", "apb_pclk"; | |
4672cddf LW |
210 | }; |
211 | ||
212 | uart@17000000 { | |
213 | compatible = "arm,pl011", "arm,primecell"; | |
b7929852 LW |
214 | clocks = <&uartclk>, <&pclk>; |
215 | clock-names = "uartclk", "apb_pclk"; | |
4672cddf LW |
216 | }; |
217 | ||
218 | kmi@18000000 { | |
219 | compatible = "arm,pl050", "arm,primecell"; | |
b7929852 LW |
220 | clocks = <&kmiclk>, <&pclk>; |
221 | clock-names = "KMIREFCLK", "apb_pclk"; | |
4672cddf LW |
222 | }; |
223 | ||
224 | kmi@19000000 { | |
225 | compatible = "arm,pl050", "arm,primecell"; | |
b7929852 LW |
226 | clocks = <&kmiclk>, <&pclk>; |
227 | clock-names = "KMIREFCLK", "apb_pclk"; | |
4672cddf LW |
228 | }; |
229 | ||
230 | /* | |
231 | * These PrimeCells are only available on the Integrator/CP | |
232 | */ | |
233 | mmc@1c000000 { | |
234 | compatible = "arm,pl180", "arm,primecell"; | |
235 | reg = <0x1c000000 0x1000>; | |
236 | interrupts = <23 24>; | |
237 | max-frequency = <515633>; | |
b7929852 LW |
238 | clocks = <&uartclk>, <&pclk>; |
239 | clock-names = "mclk", "apb_pclk"; | |
4672cddf LW |
240 | }; |
241 | ||
242 | aaci@1d000000 { | |
243 | compatible = "arm,pl041", "arm,primecell"; | |
244 | reg = <0x1d000000 0x1000>; | |
245 | interrupts = <25>; | |
b7929852 LW |
246 | clocks = <&pclk>; |
247 | clock-names = "apb_pclk"; | |
4672cddf LW |
248 | }; |
249 | ||
250 | clcd@c0000000 { | |
251 | compatible = "arm,pl110", "arm,primecell"; | |
252 | reg = <0xC0000000 0x1000>; | |
253 | interrupts = <22>; | |
b7929852 | 254 | clocks = <&auxosc>, <&pclk>; |
e3f61760 LW |
255 | clock-names = "clcdclk", "apb_pclk"; |
256 | ||
257 | port { | |
258 | /* | |
259 | * The VGA connected is implemented with a | |
260 | * THS8134A triple DAC that can be run in 24bit | |
261 | * or 16bit RGB mode. | |
262 | */ | |
263 | clcd_pads: endpoint { | |
264 | remote-endpoint = <&clcd_panel>; | |
265 | arm,pl11x,tft-r0g0b0-pads = <1 7 13>; | |
266 | }; | |
267 | }; | |
268 | ||
269 | panel { | |
270 | compatible = "panel-dpi"; | |
271 | ||
272 | port { | |
273 | clcd_panel: endpoint { | |
274 | remote-endpoint = <&clcd_pads>; | |
275 | }; | |
276 | }; | |
277 | ||
278 | /* Standard 640x480 VGA timings */ | |
279 | panel-timing { | |
280 | clock-frequency = <25175000>; | |
281 | hactive = <640>; | |
282 | hback-porch = <48>; | |
283 | hfront-porch = <16>; | |
284 | hsync-len = <96>; | |
285 | vactive = <480>; | |
286 | vback-porch = <33>; | |
287 | vfront-porch = <10>; | |
288 | vsync-len = <2>; | |
289 | }; | |
290 | }; | |
4672cddf LW |
291 | }; |
292 | }; | |
4980f9bc | 293 | }; |