[linux-block.git] / arch / arm / boot / dts / integratorap.dts

// SPDX-License-Identifier: GPL-2.0
/*
 * Device Tree for the ARM Integrator/AP platform
 */

/dts-v1/;
/include/ "integrator.dtsi"

/ {
	model = "ARM Integrator/AP";
	compatible = "arm,integrator-ap";
	dma-ranges = <0x80000000 0x0 0x80000000>;

	cpus {
		#address-cells = <1>;
		#size-cells = <0>;

		cpu@0 {
			device_type = "cpu";
			/*
			 * Since the board has pluggable CPU modules, we
			 * cannot define a proper compatible here. Let the
			 * boot loader fill in the apropriate compatible
			 * string if necessary.
			 */
			/* compatible = "arm,arm926ej-s"; */
			reg = <0>;
			/*
			 * The documentation in ARM DUI 0138E page 3-12 states
			 * that the maximum frequency for this clock is 200 MHz
			 * but painful trial-and-error has proved to me that it
			 * is actually just hanging the system above 71 MHz.
			 * Sad but true.
			 */
					 /* kHz     uV   */
			operating-points = <71000  0
					    66000  0
					    60000  0
					    48000  0
					    36000  0
					    24000  0
					    12000  0>;
			clocks = <&cmosc>;
			clock-names = "cpu";
			clock-latency = <1000000>; /* 1 ms */
		};
	};

	aliases {
		arm,timer-primary = &timer2;
		arm,timer-secondary = &timer1;
	};

	chosen {
		bootargs = "root=/dev/ram0 console=ttyAM0,38400n8 earlyprintk";
	};

	/* 24 MHz chrystal on the Integrator/AP development board */
	xtal24mhz: xtal24mhz@24M {
		#clock-cells = <0>;
		compatible = "fixed-clock";
		clock-frequency = <24000000>;
	};

	pclk: pclk@0 {
		#clock-cells = <0>;
		compatible = "fixed-factor-clock";
		clock-div = <1>;
		clock-mult = <1>;
		clocks = <&xtal24mhz>;
	};

	/* The UART clock is 14.74 MHz divided by an ICS525 */
	uartclk: uartclk@14.74M {
		#clock-cells = <0>;
		compatible = "fixed-clock";
		clock-frequency = <14745600>;
		clocks = <&xtal24mhz>;
	};

	core-module@10000000 {
		/* 24 MHz chrystal on the core module */
		cm24mhz: cm24mhz@24M {
			#clock-cells = <0>;
			compatible = "fixed-clock";
			clock-frequency = <24000000>;
		};

		/* Oscillator on the core module, clocks the CPU core */
		cmosc: cmosc@24M {
			compatible = "arm,syscon-icst525-integratorap-cm";
			#clock-cells = <0>;
			lock-offset = <0x14>;
			vco-offset = <0x08>;
			clocks = <&cm24mhz>;
		};

		/* Auxilary oscillator on the core module, 32.369MHz at boot */
		auxosc: auxosc@24M {
			compatible = "arm,syscon-icst525";
			#clock-cells = <0>;
			lock-offset = <0x14>;
			vco-offset = <0x1c>;
			clocks = <&cm24mhz>;
		};
	};

	syscon {
		compatible = "arm,integrator-ap-syscon", "syscon";
		reg = <0x11000000 0x100>;
		interrupt-parent = <&pic>;
		/* These are the logical module IRQs */
		interrupts = <9>, <10>, <11>, <12>;

		/*
		 * SYSCLK clocks PCIv3 bridge, system controller and the
		 * logic modules.
		 */
		sysclk: apsys@24M {
			compatible = "arm,syscon-icst525-integratorap-sys";
			#clock-cells = <0>;
			lock-offset = <0x1c>;
			vco-offset = <0x04>;
			clocks = <&xtal24mhz>;
		};

		/* One-bit control for the PCI bus clock (33 or 25 MHz) */
		pciclk: pciclk@24M {
			compatible = "arm,syscon-icst525-integratorap-pci";
			#clock-cells = <0>;
			lock-offset = <0x1c>;
			vco-offset = <0x04>;
			clocks = <&xtal24mhz>;
		};
	};

	timer0: timer@13000000 {
		compatible = "arm,integrator-timer";
		clocks = <&xtal24mhz>;
	};

	timer1: timer@13000100 {
		compatible = "arm,integrator-timer";
		clocks = <&xtal24mhz>;
	};

	timer2: timer@13000200 {
		compatible = "arm,integrator-timer";
		clocks = <&xtal24mhz>;
	};

	pic: pic@14000000 {
		valid-mask = <0x003fffff>;
	};

	pci: pciv3@62000000 {
		compatible = "v3,v360epc-pci";
		#interrupt-cells = <1>;
		#size-cells = <2>;
		#address-cells = <3>;
		reg = <0x62000000 0x10000>;
		interrupt-parent = <&pic>;
		interrupts = <17>; /* Bus error IRQ */
		ranges = <0x00000000 0 0x61000000 /* config space */
			0x61000000 0 0x00100000 /* 16 MiB @ 61000000 */
			0x01000000 0 0x0 /* I/O space */
			0x60000000 0 0x00100000 /* 16 MiB @ 60000000 */
			0x02000000 0 0x00000000 /* non-prefectable memory */
			0x40000000 0 0x10000000 /* 256 MiB @ 40000000 */
			0x42000000 0 0x10000000 /* prefetchable memory */
			0x50000000 0 0x10000000>; /* 256 MiB @ 50000000 */
		interrupt-map-mask = <0xf800 0 0 0x7>;
		interrupt-map = <
		/* IDSEL 9 */
		0x4800 0 0 1 &pic 13 /* INT A on slot 9 is irq 13 */
		0x4800 0 0 2 &pic 14 /* INT B on slot 9 is irq 14 */
		0x4800 0 0 3 &pic 15 /* INT C on slot 9 is irq 15 */
		0x4800 0 0 4 &pic 16 /* INT D on slot 9 is irq 16 */
		/* IDSEL 10 */
		0x5000 0 0 1 &pic 14 /* INT A on slot 10 is irq 14 */
		0x5000 0 0 2 &pic 15 /* INT B on slot 10 is irq 15 */
		0x5000 0 0 3 &pic 16 /* INT C on slot 10 is irq 16 */
		0x5000 0 0 4 &pic 13 /* INT D on slot 10 is irq 13 */
		/* IDSEL 11 */
		0x5800 0 0 1 &pic 15 /* INT A on slot 11 is irq 15 */
		0x5800 0 0 2 &pic 16 /* INT B on slot 11 is irq 16 */
		0x5800 0 0 3 &pic 13 /* INT C on slot 11 is irq 13 */
		0x5800 0 0 4 &pic 14 /* INT D on slot 11 is irq 14 */
		/* IDSEL 12 */
		0x6000 0 0 1 &pic 16 /* INT A on slot 12 is irq 16 */
		0x6000 0 0 2 &pic 13 /* INT B on slot 12 is irq 13 */
		0x6000 0 0 3 &pic 14 /* INT C on slot 12 is irq 14 */
		0x6000 0 0 4 &pic 15 /* INT D on slot 12 is irq 15 */
		>;
	};

	fpga {
		/*
		 * The Integator/AP predates the idea to have magic numbers
		 * identifying the PrimeCell in hardware, thus we have to
		 * supply these from the device tree.
		 */
		rtc: rtc@15000000 {
			compatible = "arm,pl030", "arm,primecell";
			arm,primecell-periphid = <0x00041030>;
			clocks = <&pclk>;
			clock-names = "apb_pclk";
		};

		uart0: uart@16000000 {
			compatible = "arm,pl010", "arm,primecell";
			arm,primecell-periphid = <0x00041010>;
			clocks = <&uartclk>, <&pclk>;
			clock-names = "uartclk", "apb_pclk";
		};

		uart1: uart@17000000 {
			compatible = "arm,pl010", "arm,primecell";
			arm,primecell-periphid = <0x00041010>;
			clocks = <&uartclk>, <&pclk>;
			clock-names = "uartclk", "apb_pclk";
		};

		kmi0: kmi@18000000 {
			compatible = "arm,pl050", "arm,primecell";
			arm,primecell-periphid = <0x00041050>;
			clocks = <&xtal24mhz>, <&pclk>;
			clock-names = "KMIREFCLK", "apb_pclk";
		};

		kmi1: kmi@19000000 {
			compatible = "arm,pl050", "arm,primecell";
			arm,primecell-periphid = <0x00041050>;
			clocks = <&xtal24mhz>, <&pclk>;
			clock-names = "KMIREFCLK", "apb_pclk";
		};
	};
};
Commit	Line	Data
b2441318	1	// SPDX-License-Identifier: GPL-2.0
4980f9bc LW	2	/*
	3	* Device Tree for the ARM Integrator/AP platform
	4	*/
	5
	6	/dts-v1/;
	7	/include/ "integrator.dtsi"
	8
	9	/ {
	10	model = "ARM Integrator/AP";
	11	compatible = "arm,integrator-ap";
e6dc195c	12	dma-ranges = <0x80000000 0x0 0x80000000>;
4980f9bc	13
964971c8 LW	14	cpus {
	15	#address-cells = <1>;
	16	#size-cells = <0>;
	17
	18	cpu@0 {
	19	device_type = "cpu";
	20	/*
	21	* Since the board has pluggable CPU modules, we
	22	* cannot define a proper compatible here. Let the
	23	* boot loader fill in the apropriate compatible
	24	* string if necessary.
	25	*/
	26	/* compatible = "arm,arm926ej-s"; */
	27	reg = <0>;
	28	/*
	29	* The documentation in ARM DUI 0138E page 3-12 states
	30	* that the maximum frequency for this clock is 200 MHz
	31	* but painful trial-and-error has proved to me that it
	32	* is actually just hanging the system above 71 MHz.
	33	* Sad but true.
	34	*/
	35	/* kHz uV */
	36	operating-points = <71000 0
	37	66000 0
	38	60000 0
	39	48000 0
	40	36000 0
	41	24000 0
	42	12000 0>;
	43	clocks = <&cmosc>;
	44	clock-names = "cpu";
	45	clock-latency = <1000000>; /* 1 ms */
	46	};
	47	};
	48
4980f9bc LW	49	aliases {
	50	arm,timer-primary = &timer2;
	51	arm,timer-secondary = &timer1;
	52	};
	53
	54	chosen {
	55	bootargs = "root=/dev/ram0 console=ttyAM0,38400n8 earlyprintk";
	56	};
	57
257417ec	58	/* 24 MHz chrystal on the Integrator/AP development board */
b7929852 LW	59	xtal24mhz: xtal24mhz@24M {
	60	#clock-cells = <0>;
	61	compatible = "fixed-clock";
	62	clock-frequency = <24000000>;
	63	};
	64
	65	pclk: pclk@0 {
	66	#clock-cells = <0>;
	67	compatible = "fixed-factor-clock";
	68	clock-div = <1>;
	69	clock-mult = <1>;
	70	clocks = <&xtal24mhz>;
	71	};
	72
	73	/* The UART clock is 14.74 MHz divided by an ICS525 */
	74	uartclk: uartclk@14.74M {
	75	#clock-cells = <0>;
	76	compatible = "fixed-clock";
	77	clock-frequency = <14745600>;
e272b7ee	78	clocks = <&xtal24mhz>;
b7929852 LW	79	};
b7929852 LW	80
257417ec LW	81	core-module@10000000 {
	82	/* 24 MHz chrystal on the core module */
	83	cm24mhz: cm24mhz@24M {
	84	#clock-cells = <0>;
	85	compatible = "fixed-clock";
	86	clock-frequency = <24000000>;
	87	};
	88
	89	/* Oscillator on the core module, clocks the CPU core */
	90	cmosc: cmosc@24M {
	91	compatible = "arm,syscon-icst525-integratorap-cm";
	92	#clock-cells = <0>;
	93	lock-offset = <0x14>;
	94	vco-offset = <0x08>;
	95	clocks = <&cm24mhz>;
	96	};
	97
	98	/* Auxilary oscillator on the core module, 32.369MHz at boot */
	99	auxosc: auxosc@24M {
	100	compatible = "arm,syscon-icst525";
	101	#clock-cells = <0>;
	102	lock-offset = <0x14>;
	103	vco-offset = <0x1c>;
	104	clocks = <&cm24mhz>;
	105	};
b7929852 LW	106	};
b7929852 LW	107
e67ae6be	108	syscon {
f2b54191	109	compatible = "arm,integrator-ap-syscon", "syscon";
e67ae6be	110	reg = <0x11000000 0x100>;
a6720258 LW	111	interrupt-parent = <&pic>;
	112	/* These are the logical module IRQs */
	113	interrupts = <9>, <10>, <11>, <12>;
49eb1efa LW	114
	115	/*
	116	* SYSCLK clocks PCIv3 bridge, system controller and the
	117	* logic modules.
	118	*/
	119	sysclk: apsys@24M {
	120	compatible = "arm,syscon-icst525-integratorap-sys";
	121	#clock-cells = <0>;
	122	lock-offset = <0x1c>;
	123	vco-offset = <0x04>;
	124	clocks = <&xtal24mhz>;
	125	};
	126
	127	/* One-bit control for the PCI bus clock (33 or 25 MHz) */
	128	pciclk: pciclk@24M {
	129	compatible = "arm,syscon-icst525-integratorap-pci";
	130	#clock-cells = <0>;
	131	lock-offset = <0x1c>;
	132	vco-offset = <0x04>;
	133	clocks = <&xtal24mhz>;
	134	};
e67ae6be LW	135	};
e67ae6be LW	136
4980f9bc LW	137	timer0: timer@13000000 {
4980f9bc LW	138	compatible = "arm,integrator-timer";
b7929852	139	clocks = <&xtal24mhz>;
4980f9bc LW	140	};
	141
	142	timer1: timer@13000100 {
	143	compatible = "arm,integrator-timer";
b7929852	144	clocks = <&xtal24mhz>;
4980f9bc LW	145	};
	146
	147	timer2: timer@13000200 {
	148	compatible = "arm,integrator-timer";
b7929852	149	clocks = <&xtal24mhz>;
4980f9bc LW	150	};
	151
	152	pic: pic@14000000 {
	153	valid-mask = <0x003fffff>;
	154	};
4672cddf	155
f55b2b56 LW	156	pci: pciv3@62000000 {
	157	compatible = "v3,v360epc-pci";
	158	#interrupt-cells = <1>;
	159	#size-cells = <2>;
	160	#address-cells = <3>;
	161	reg = <0x62000000 0x10000>;
	162	interrupt-parent = <&pic>;
	163	interrupts = <17>; /* Bus error IRQ */
	164	ranges = <0x00000000 0 0x61000000 /* config space */
	165	0x61000000 0 0x00100000 /* 16 MiB @ 61000000 */
56ce3ffb	166	0x01000000 0 0x0 /* I/O space */
f55b2b56	167	0x60000000 0 0x00100000 /* 16 MiB @ 60000000 */
56ce3ffb	168	0x02000000 0 0x00000000 /* non-prefectable memory */
f55b2b56	169	0x40000000 0 0x10000000 /* 256 MiB @ 40000000 */
56ce3ffb	170	0x42000000 0 0x10000000 /* prefetchable memory */
f55b2b56 LW	171	0x50000000 0 0x10000000>; /* 256 MiB @ 50000000 */
	172	interrupt-map-mask = <0xf800 0 0 0x7>;
	173	interrupt-map = <
	174	/* IDSEL 9 */
	175	0x4800 0 0 1 &pic 13 /* INT A on slot 9 is irq 13 */
	176	0x4800 0 0 2 &pic 14 /* INT B on slot 9 is irq 14 */
	177	0x4800 0 0 3 &pic 15 /* INT C on slot 9 is irq 15 */
	178	0x4800 0 0 4 &pic 16 /* INT D on slot 9 is irq 16 */
	179	/* IDSEL 10 */
	180	0x5000 0 0 1 &pic 14 /* INT A on slot 10 is irq 14 */
	181	0x5000 0 0 2 &pic 15 /* INT B on slot 10 is irq 15 */
	182	0x5000 0 0 3 &pic 16 /* INT C on slot 10 is irq 16 */
	183	0x5000 0 0 4 &pic 13 /* INT D on slot 10 is irq 13 */
	184	/* IDSEL 11 */
	185	0x5800 0 0 1 &pic 15 /* INT A on slot 11 is irq 15 */
	186	0x5800 0 0 2 &pic 16 /* INT B on slot 11 is irq 16 */
	187	0x5800 0 0 3 &pic 13 /* INT C on slot 11 is irq 13 */
	188	0x5800 0 0 4 &pic 14 /* INT D on slot 11 is irq 14 */
	189	/* IDSEL 12 */
	190	0x6000 0 0 1 &pic 16 /* INT A on slot 12 is irq 16 */
	191	0x6000 0 0 2 &pic 13 /* INT B on slot 12 is irq 13 */
	192	0x6000 0 0 3 &pic 14 /* INT C on slot 12 is irq 14 */
	193	0x6000 0 0 4 &pic 15 /* INT D on slot 12 is irq 15 */
	194	>;
	195	};
	196
4672cddf LW	197	fpga {
	198	/*
	199	* The Integator/AP predates the idea to have magic numbers
	200	* identifying the PrimeCell in hardware, thus we have to
	201	* supply these from the device tree.
	202	*/
	203	rtc: rtc@15000000 {
	204	compatible = "arm,pl030", "arm,primecell";
	205	arm,primecell-periphid = <0x00041030>;
b7929852 LW	206	clocks = <&pclk>;
b7929852 LW	207	clock-names = "apb_pclk";
4672cddf LW	208	};
	209
	210	uart0: uart@16000000 {
	211	compatible = "arm,pl010", "arm,primecell";
	212	arm,primecell-periphid = <0x00041010>;
b7929852 LW	213	clocks = <&uartclk>, <&pclk>;
b7929852 LW	214	clock-names = "uartclk", "apb_pclk";
4672cddf LW	215	};
	216
	217	uart1: uart@17000000 {
	218	compatible = "arm,pl010", "arm,primecell";
	219	arm,primecell-periphid = <0x00041010>;
b7929852 LW	220	clocks = <&uartclk>, <&pclk>;
b7929852 LW	221	clock-names = "uartclk", "apb_pclk";
4672cddf LW	222	};
	223
	224	kmi0: kmi@18000000 {
	225	compatible = "arm,pl050", "arm,primecell";
	226	arm,primecell-periphid = <0x00041050>;
b7929852 LW	227	clocks = <&xtal24mhz>, <&pclk>;
b7929852 LW	228	clock-names = "KMIREFCLK", "apb_pclk";
4672cddf LW	229	};
	230
	231	kmi1: kmi@19000000 {
	232	compatible = "arm,pl050", "arm,primecell";
	233	arm,primecell-periphid = <0x00041050>;
b7929852 LW	234	clocks = <&xtal24mhz>, <&pclk>;
b7929852 LW	235	clock-names = "KMIREFCLK", "apb_pclk";
4672cddf LW	236	};
4672cddf LW	237	};
4980f9bc	238	};