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ARM: dts: imx: Fix Ethernet PHY reset polarity
[linux-2.6-block.git] / arch / arm / boot / dts / imx7d-sdb.dts
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5db106bc
FL		 1/*
2 * Copyright (C) 2015 Freescale Semiconductor, Inc.
3 *
4 * This file is dual-licensed: you can use it either under the terms
5 * of the GPL or the X11 license, at your option. Note that this dual
6 * licensing only applies to this file, and not this project as a
7 * whole.
8 *
9 * a) This file is free software; you can redistribute it and/or
10 * modify it under the terms of the GNU General Public License as
11 * published by the Free Software Foundation; either version 2 of the
12 * License, or (at your option) any later version.
13 *
14 * This file is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 * GNU General Public License for more details.
18 *
19 * Or, alternatively,
20 *
21 * b) Permission is hereby granted, free of charge, to any person
22 * obtaining a copy of this software and associated documentation
23 * files (the "Software"), to deal in the Software without
24 * restriction, including without limitation the rights to use,
25 * copy, modify, merge, publish, distribute, sublicense, and/or
26 * sell copies of the Software, and to permit persons to whom the
27 * Software is furnished to do so, subject to the following
28 * conditions:
29 *
30 * The above copyright notice and this permission notice shall be
31 * included in all copies or substantial portions of the Software.
32 *
33 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
34 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
35 * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
36 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
37 * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
38 * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
39 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
40 * OTHER DEALINGS IN THE SOFTWARE.
41 */
42
43/dts-v1/;
44
a67970a2 45#include "imx7d.dtsi"
5db106bc
FL		 46
47/ {
48 model = "Freescale i.MX7 SabreSD Board";
49 compatible = "fsl,imx7d-sdb", "fsl,imx7d";
50
51 memory {
52 reg = <0x80000000 0x80000000>;
53 };
54
184f39b5
AS		 55 spi4 {
56 compatible = "spi-gpio";
57 pinctrl-names = "default";
58 pinctrl-0 = <&pinctrl_spi4>;
59 gpio-sck = <&gpio1 13 GPIO_ACTIVE_HIGH>;
60 gpio-mosi = <&gpio1 9 GPIO_ACTIVE_HIGH>;
61 cs-gpios = <&gpio1 12 GPIO_ACTIVE_HIGH>;
62 num-chipselects = <1>;
63 #address-cells = <1>;
64 #size-cells = <0>;
65
66 extended_io: gpio-expander@0 {
67 compatible = "fairchild,74hc595";
68 gpio-controller;
69 #gpio-cells = <2>;
70 reg = <0>;
71 registers-number = <1>;
72 spi-max-frequency = <100000>;
73 };
74 };
75
5db106bc
FL		 76 regulators {
77 compatible = "simple-bus";
78 #address-cells = <1>;
79 #size-cells = <0>;
80
81 reg_usb_otg1_vbus: regulator@0 {
82 compatible = "regulator-fixed";
83 reg = <0>;
84 regulator-name = "usb_otg1_vbus";
85 regulator-min-microvolt = <5000000>;
86 regulator-max-microvolt = <5000000>;
87 gpio = <&gpio1 5 GPIO_ACTIVE_HIGH>;
88 enable-active-high;
89 };
90
91 reg_usb_otg2_vbus: regulator@1 {
92 compatible = "regulator-fixed";
93 reg = <1>;
94 regulator-name = "usb_otg2_vbus";
95 regulator-min-microvolt = <5000000>;
96 regulator-max-microvolt = <5000000>;
97 gpio = <&gpio4 7 GPIO_ACTIVE_HIGH>;
98 enable-active-high;
99 };
100
101 reg_can2_3v3: regulator@2 {
102 compatible = "regulator-fixed";
103 reg = <2>;
104 regulator-name = "can2-3v3";
105 regulator-min-microvolt = <3300000>;
106 regulator-max-microvolt = <3300000>;
107 gpio = <&gpio1 7 GPIO_ACTIVE_LOW>;
108 };
109
110 reg_vref_1v8: regulator@3 {
111 compatible = "regulator-fixed";
112 reg = <3>;
113 regulator-name = "vref-1v8";
114 regulator-min-microvolt = <1800000>;
115 regulator-max-microvolt = <1800000>;
116 };
117 };
118};
119
64b83432
HC		 120&adc1 {
121 vref-supply = <&reg_vref_1v8>;
122 status = "okay";
123};
124
125&adc2 {
126 vref-supply = <&reg_vref_1v8>;
127 status = "okay";
128};
129
5db106bc
FL		 130&cpu0 {
131 arm-supply = <&sw1a_reg>;
132};
133
d09e6bea 134&ecspi3 {
d09e6bea
DD		 135 pinctrl-names = "default";
136 pinctrl-0 = <&pinctrl_ecspi3>;
137 cs-gpios = <&gpio5 9 GPIO_ACTIVE_HIGH>;
138 status = "okay";
139
140 tsc2046@0 {
141 compatible = "ti,tsc2046";
142 reg = <0>;
143 spi-max-frequency = <1000000>;
144 pinctrl-names ="default";
145 pinctrl-0 = <&pinctrl_tsc2046_pendown>;
146 interrupt-parent = <&gpio2>;
147 interrupts = <29 0>;
148 pendown-gpio = <&gpio2 29 GPIO_ACTIVE_HIGH>;
149 ti,x-min = /bits/ 16 <0>;
150 ti,x-max = /bits/ 16 <0>;
151 ti,y-min = /bits/ 16 <0>;
152 ti,y-max = /bits/ 16 <0>;
153 ti,pressure-max = /bits/ 16 <0>;
f7d3586f 154 ti,x-plate-ohms = /bits/ 16 <400>;
d09e6bea
DD		 155 wakeup-source;
156 };
157};
158
47bcc8c0
FD		 159&fec1 {
160 pinctrl-names = "default";
161 pinctrl-0 = <&pinctrl_enet1>;
162 assigned-clocks = <&clks IMX7D_ENET1_TIME_ROOT_SRC>,
163 <&clks IMX7D_ENET1_TIME_ROOT_CLK>;
164 assigned-clock-parents = <&clks IMX7D_PLL_ENET_MAIN_100M_CLK>;
165 assigned-clock-rates = <0>, <100000000>;
166 phy-mode = "rgmii";
167 phy-handle = <&ethphy0>;
168 fsl,magic-packet;
169 status = "okay";
170
171 mdio {
172 #address-cells = <1>;
173 #size-cells = <0>;
174
175 ethphy0: ethernet-phy@0 {
176 reg = <0>;
177 };
178
179 ethphy1: ethernet-phy@1 {
180 reg = <1>;
181 };
182 };
183};
184
185&fec2 {
186 pinctrl-names = "default";
187 pinctrl-0 = <&pinctrl_enet2>;
188 assigned-clocks = <&clks IMX7D_ENET2_TIME_ROOT_SRC>,
189 <&clks IMX7D_ENET2_TIME_ROOT_CLK>;
190 assigned-clock-parents = <&clks IMX7D_PLL_ENET_MAIN_100M_CLK>;
191 assigned-clock-rates = <0>, <100000000>;
192 phy-mode = "rgmii";
193 phy-handle = <&ethphy1>;
194 fsl,magic-packet;
195 status = "okay";
196};
197
5db106bc
FL		 198&i2c1 {
199 pinctrl-names = "default";
200 pinctrl-0 = <&pinctrl_i2c1>;
201 status = "okay";
202
203 pmic: pfuze3000@08 {
204 compatible = "fsl,pfuze3000";
205 reg = <0x08>;
206
207 regulators {
208 sw1a_reg: sw1a {
209 regulator-min-microvolt = <700000>;
210 regulator-max-microvolt = <1475000>;
211 regulator-boot-on;
212 regulator-always-on;
213 regulator-ramp-delay = <6250>;
214 };
215
216 /* use sw1c_reg to align with pfuze100/pfuze200 */
217 sw1c_reg: sw1b {
218 regulator-min-microvolt = <700000>;
219 regulator-max-microvolt = <1475000>;
220 regulator-boot-on;
221 regulator-always-on;
222 regulator-ramp-delay = <6250>;
223 };
224
225 sw2_reg: sw2 {
226 regulator-min-microvolt = <1500000>;
227 regulator-max-microvolt = <1850000>;
228 regulator-boot-on;
229 regulator-always-on;
230 };
231
232 sw3a_reg: sw3 {
233 regulator-min-microvolt = <900000>;
234 regulator-max-microvolt = <1650000>;
235 regulator-boot-on;
236 regulator-always-on;
237 };
238
239 swbst_reg: swbst {
240 regulator-min-microvolt = <5000000>;
241 regulator-max-microvolt = <5150000>;
242 };
243
244 snvs_reg: vsnvs {
245 regulator-min-microvolt = <1000000>;
246 regulator-max-microvolt = <3000000>;
247 regulator-boot-on;
248 regulator-always-on;
249 };
250
251 vref_reg: vrefddr {
252 regulator-boot-on;
253 regulator-always-on;
254 };
255
256 vgen1_reg: vldo1 {
257 regulator-min-microvolt = <1800000>;
258 regulator-max-microvolt = <3300000>;
259 regulator-always-on;
260 };
261
262 vgen2_reg: vldo2 {
263 regulator-min-microvolt = <800000>;
264 regulator-max-microvolt = <1550000>;
265 };
266
267 vgen3_reg: vccsd {
268 regulator-min-microvolt = <2850000>;
269 regulator-max-microvolt = <3300000>;
270 regulator-always-on;
271 };
272
273 vgen4_reg: v33 {
274 regulator-min-microvolt = <2850000>;
275 regulator-max-microvolt = <3300000>;
276 regulator-always-on;
277 };
278
279 vgen5_reg: vldo3 {
280 regulator-min-microvolt = <1800000>;
281 regulator-max-microvolt = <3300000>;
282 regulator-always-on;
283 };
284
285 vgen6_reg: vldo4 {
286 regulator-min-microvolt = <1800000>;
287 regulator-max-microvolt = <3300000>;
288 regulator-always-on;
289 };
290 };
291 };
292};
293
294&i2c2 {
295 pinctrl-names = "default";
296 pinctrl-0 = <&pinctrl_i2c2>;
297 status = "okay";
298};
299
300&i2c3 {
301 pinctrl-names = "default";
302 pinctrl-0 = <&pinctrl_i2c3>;
303 status = "okay";
304};
305
306&i2c4 {
307 pinctrl-names = "default";
308 pinctrl-0 = <&pinctrl_i2c4>;
309 status = "okay";
310
311 codec: wm8960@1a {
312 compatible = "wlf,wm8960";
313 reg = <0x1a>;
314 clocks = <&clks IMX7D_AUDIO_MCLK_ROOT_CLK>;
315 clock-names = "mclk";
316 wlf,shared-lrclk;
317 };
318};
319
41969055
DD		 320&lcdif {
321 pinctrl-names = "default";
322 pinctrl-0 = <&pinctrl_lcdif>;
323 display = <&display0>;
324 status = "okay";
325
326 display0: display {
327 bits-per-pixel = <16>;
328 bus-width = <24>;
329
330 display-timings {
331 native-mode = <&timing0>;
332
333 timing0: timing0 {
334 clock-frequency = <9200000>;
335 hactive = <480>;
336 vactive = <272>;
337 hfront-porch = <8>;
338 hback-porch = <4>;
339 hsync-len = <41>;
340 vback-porch = <2>;
341 vfront-porch = <4>;
342 vsync-len = <10>;
343 hsync-active = <0>;
344 vsync-active = <0>;
345 de-active = <1>;
346 pixelclk-active = <0>;
347 };
348 };
349 };
350};
351
34adfaa3
AS		 352&pcie {
353 reset-gpio = <&extended_io 1 GPIO_ACTIVE_LOW>;
354 status = "okay";
355};
356
41969055
DD		 357&pwm1 {
358 pinctrl-names = "default";
359 pinctrl-0 = <&pinctrl_pwm1>;
360 status = "okay";
361};
362
5db106bc
FL		 363&uart1 {
364 pinctrl-names = "default";
365 pinctrl-0 = <&pinctrl_uart1>;
366 assigned-clocks = <&clks IMX7D_UART1_ROOT_SRC>;
367 assigned-clock-parents = <&clks IMX7D_PLL_SYS_MAIN_240M_CLK>;
368 status = "okay";
369};
370
a81fd34d
FE		 371&usbotg1 {
372 vbus-supply = <&reg_usb_otg1_vbus>;
373 status = "okay";
374};
375
376&usbotg2 {
377 vbus-supply = <&reg_usb_otg2_vbus>;
378 dr_mode = "host";
379 status = "okay";
380};
381
5db106bc
FL		 382&usdhc1 {
383 pinctrl-names = "default";
384 pinctrl-0 = <&pinctrl_usdhc1>;
1cd55947
DA		 385 cd-gpios = <&gpio5 0 GPIO_ACTIVE_LOW>;
386 wp-gpios = <&gpio5 1 GPIO_ACTIVE_HIGH>;
26cefdd1 387 wakeup-source;
5db106bc
FL		 388 keep-power-in-suspend;
389 status = "okay";
390};
391
f651d781
HC		 392&usdhc3 {
393 pinctrl-names = "default", "state_100mhz", "state_200mhz";
394 pinctrl-0 = <&pinctrl_usdhc3>;
395 pinctrl-1 = <&pinctrl_usdhc3_100mhz>;
396 pinctrl-2 = <&pinctrl_usdhc3_200mhz>;
397 assigned-clocks = <&clks IMX7D_USDHC3_ROOT_CLK>;
398 assigned-clock-rates = <400000000>;
399 bus-width = <8>;
400 fsl,tuning-step = <2>;
401 non-removable;
402 status = "okay";
403};
404
51fd0323
FE		 405&wdog1 {
406 pinctrl-names = "default";
407 pinctrl-0 = <&pinctrl_wdog>;
408 fsl,ext-reset-output;
409};
410
5db106bc
FL		 411&iomuxc {
412 pinctrl-names = "default";
413 pinctrl-0 = <&pinctrl_hog>;
414
415 imx7d-sdb {
d09e6bea
DD		 416 pinctrl_ecspi3: ecspi3grp {
417 fsl,pins = <
418 MX7D_PAD_SAI2_TX_SYNC__ECSPI3_MISO 0x2
419 MX7D_PAD_SAI2_TX_BCLK__ECSPI3_MOSI 0x2
420 MX7D_PAD_SAI2_RX_DATA__ECSPI3_SCLK 0x2
421 MX7D_PAD_SD2_CD_B__GPIO5_IO9 0x59
422 >;
423 };
424
47bcc8c0
FD		 425 pinctrl_enet1: enet1grp {
426 fsl,pins = <
427 MX7D_PAD_GPIO1_IO10__ENET1_MDIO 0x3
428 MX7D_PAD_GPIO1_IO11__ENET1_MDC 0x3
429 MX7D_PAD_ENET1_RGMII_TXC__ENET1_RGMII_TXC 0x1
430 MX7D_PAD_ENET1_RGMII_TD0__ENET1_RGMII_TD0 0x1
431 MX7D_PAD_ENET1_RGMII_TD1__ENET1_RGMII_TD1 0x1
432 MX7D_PAD_ENET1_RGMII_TD2__ENET1_RGMII_TD2 0x1
433 MX7D_PAD_ENET1_RGMII_TD3__ENET1_RGMII_TD3 0x1
434 MX7D_PAD_ENET1_RGMII_TX_CTL__ENET1_RGMII_TX_CTL 0x1
435 MX7D_PAD_ENET1_RGMII_RXC__ENET1_RGMII_RXC 0x1
436 MX7D_PAD_ENET1_RGMII_RD0__ENET1_RGMII_RD0 0x1
437 MX7D_PAD_ENET1_RGMII_RD1__ENET1_RGMII_RD1 0x1
438 MX7D_PAD_ENET1_RGMII_RD2__ENET1_RGMII_RD2 0x1
439 MX7D_PAD_ENET1_RGMII_RD3__ENET1_RGMII_RD3 0x1
440 MX7D_PAD_ENET1_RGMII_RX_CTL__ENET1_RGMII_RX_CTL 0x1
441 >;
442 };
443
444 pinctrl_enet2: enet2grp {
445 fsl,pins = <
446 MX7D_PAD_EPDC_GDSP__ENET2_RGMII_TXC 0x1
447 MX7D_PAD_EPDC_SDCE2__ENET2_RGMII_TD0 0x1
448 MX7D_PAD_EPDC_SDCE3__ENET2_RGMII_TD1 0x1
449 MX7D_PAD_EPDC_GDCLK__ENET2_RGMII_TD2 0x1
450 MX7D_PAD_EPDC_GDOE__ENET2_RGMII_TD3 0x1
451 MX7D_PAD_EPDC_GDRL__ENET2_RGMII_TX_CTL 0x1
452 MX7D_PAD_EPDC_SDCE1__ENET2_RGMII_RXC 0x1
453 MX7D_PAD_EPDC_SDCLK__ENET2_RGMII_RD0 0x1
454 MX7D_PAD_EPDC_SDLE__ENET2_RGMII_RD1 0x1
455 MX7D_PAD_EPDC_SDOE__ENET2_RGMII_RD2 0x1
456 MX7D_PAD_EPDC_SDSHR__ENET2_RGMII_RD3 0x1
457 MX7D_PAD_EPDC_SDCE0__ENET2_RGMII_RX_CTL 0x1
458 >;
459 };
460
5db106bc
FL		 461 pinctrl_hog: hoggrp {
462 fsl,pins = <
463 MX7D_PAD_UART3_CTS_B__GPIO4_IO7 0x14
464 MX7D_PAD_ECSPI2_SS0__GPIO4_IO23 0x34 /* bt reg on */
465 >;
466 };
467
468 pinctrl_i2c1: i2c1grp {
469 fsl,pins = <
470 MX7D_PAD_I2C1_SDA__I2C1_SDA 0x4000007f
471 MX7D_PAD_I2C1_SCL__I2C1_SCL 0x4000007f
472 >;
473 };
474
475 pinctrl_i2c2: i2c2grp {
476 fsl,pins = <
477 MX7D_PAD_I2C2_SDA__I2C2_SDA 0x4000007f
478 MX7D_PAD_I2C2_SCL__I2C2_SCL 0x4000007f
479 >;
480 };
481
482 pinctrl_i2c3: i2c3grp {
483 fsl,pins = <
484 MX7D_PAD_I2C3_SDA__I2C3_SDA 0x4000007f
485 MX7D_PAD_I2C3_SCL__I2C3_SCL 0x4000007f
486 >;
487 };
488
489 pinctrl_i2c4: i2c4grp {
490 fsl,pins = <
491 MX7D_PAD_SAI1_RX_BCLK__I2C4_SDA 0x4000007f
492 MX7D_PAD_SAI1_RX_SYNC__I2C4_SCL 0x4000007f
493 >;
494 };
495
41969055
DD		 496 pinctrl_lcdif: lcdifgrp {
497 fsl,pins = <
498 MX7D_PAD_LCD_DATA00__LCD_DATA0 0x79
499 MX7D_PAD_LCD_DATA01__LCD_DATA1 0x79
500 MX7D_PAD_LCD_DATA02__LCD_DATA2 0x79
501 MX7D_PAD_LCD_DATA03__LCD_DATA3 0x79
502 MX7D_PAD_LCD_DATA04__LCD_DATA4 0x79
503 MX7D_PAD_LCD_DATA05__LCD_DATA5 0x79
504 MX7D_PAD_LCD_DATA06__LCD_DATA6 0x79
505 MX7D_PAD_LCD_DATA07__LCD_DATA7 0x79
506 MX7D_PAD_LCD_DATA08__LCD_DATA8 0x79
507 MX7D_PAD_LCD_DATA09__LCD_DATA9 0x79
508 MX7D_PAD_LCD_DATA10__LCD_DATA10 0x79
509 MX7D_PAD_LCD_DATA11__LCD_DATA11 0x79
510 MX7D_PAD_LCD_DATA12__LCD_DATA12 0x79
511 MX7D_PAD_LCD_DATA13__LCD_DATA13 0x79
512 MX7D_PAD_LCD_DATA14__LCD_DATA14 0x79
513 MX7D_PAD_LCD_DATA15__LCD_DATA15 0x79
514 MX7D_PAD_LCD_DATA16__LCD_DATA16 0x79
515 MX7D_PAD_LCD_DATA17__LCD_DATA17 0x79
516 MX7D_PAD_LCD_DATA18__LCD_DATA18 0x79
517 MX7D_PAD_LCD_DATA19__LCD_DATA19 0x79
518 MX7D_PAD_LCD_DATA20__LCD_DATA20 0x79
519 MX7D_PAD_LCD_DATA21__LCD_DATA21 0x79
520 MX7D_PAD_LCD_DATA22__LCD_DATA22 0x79
521 MX7D_PAD_LCD_DATA23__LCD_DATA23 0x79
522 MX7D_PAD_LCD_CLK__LCD_CLK 0x79
523 MX7D_PAD_LCD_ENABLE__LCD_ENABLE 0x79
524 MX7D_PAD_LCD_VSYNC__LCD_VSYNC 0x79
525 MX7D_PAD_LCD_HSYNC__LCD_HSYNC 0x79
526 MX7D_PAD_LCD_RESET__LCD_RESET 0x79
527 >;
528 };
529
d09e6bea
DD		 530 pinctrl_tsc2046_pendown: tsc2046_pendown {
531 fsl,pins = <
532 MX7D_PAD_EPDC_BDR1__GPIO2_IO29 0x59
533 >;
534 };
535
5db106bc
FL		 536 pinctrl_uart1: uart1grp {
537 fsl,pins = <
538 MX7D_PAD_UART1_TX_DATA__UART1_DCE_TX 0x79
539 MX7D_PAD_UART1_RX_DATA__UART1_DCE_RX 0x79
540 >;
541 };
542
543 pinctrl_uart5: uart5grp {
544 fsl,pins = <
545 MX7D_PAD_SAI1_TX_BCLK__UART5_DCE_TX 0x79
546 MX7D_PAD_SAI1_RX_DATA__UART5_DCE_RX 0x79
547 MX7D_PAD_SAI1_TX_SYNC__UART5_DCE_CTS 0x79
548 MX7D_PAD_SAI1_TX_DATA__UART5_DCE_RTS 0x79
549 >;
550 };
551
552 pinctrl_uart6: uart6grp {
553 fsl,pins = <
554 MX7D_PAD_ECSPI1_MOSI__UART6_DCE_TX 0x79
555 MX7D_PAD_ECSPI1_SCLK__UART6_DCE_RX 0x79
556 MX7D_PAD_ECSPI1_SS0__UART6_DCE_CTS 0x79
557 MX7D_PAD_ECSPI1_MISO__UART6_DCE_RTS 0x79
558 >;
559 };
560
561 pinctrl_usdhc1: usdhc1grp {
562 fsl,pins = <
563 MX7D_PAD_SD1_CMD__SD1_CMD 0x59
564 MX7D_PAD_SD1_CLK__SD1_CLK 0x19
565 MX7D_PAD_SD1_DATA0__SD1_DATA0 0x59
566 MX7D_PAD_SD1_DATA1__SD1_DATA1 0x59
567 MX7D_PAD_SD1_DATA2__SD1_DATA2 0x59
568 MX7D_PAD_SD1_DATA3__SD1_DATA3 0x59
569 MX7D_PAD_SD1_CD_B__GPIO5_IO0 0x59 /* CD */
570 MX7D_PAD_SD1_WP__GPIO5_IO1 0x59 /* WP */
571 MX7D_PAD_SD1_RESET_B__GPIO5_IO2 0x59 /* vmmc */
572 >;
573 };
574
575 pinctrl_usdhc2: usdhc2grp {
576 fsl,pins = <
577 MX7D_PAD_SD2_CMD__SD2_CMD 0x59
578 MX7D_PAD_SD2_CLK__SD2_CLK 0x19
579 MX7D_PAD_SD2_DATA0__SD2_DATA0 0x59
580 MX7D_PAD_SD2_DATA1__SD2_DATA1 0x59
581 MX7D_PAD_SD2_DATA2__SD2_DATA2 0x59
582 MX7D_PAD_SD2_DATA3__SD2_DATA3 0x59
583 MX7D_PAD_ECSPI2_MOSI__GPIO4_IO21 0x59 /* WL_REG_ON */
584 >;
585 };
586
587 pinctrl_usdhc2_100mhz: usdhc2grp_100mhz {
588 fsl,pins = <
589 MX7D_PAD_SD2_CMD__SD2_CMD 0x5a
590 MX7D_PAD_SD2_CLK__SD2_CLK 0x1a
591 MX7D_PAD_SD2_DATA0__SD2_DATA0 0x5a
592 MX7D_PAD_SD2_DATA1__SD2_DATA1 0x5a
593 MX7D_PAD_SD2_DATA2__SD2_DATA2 0x5a
594 MX7D_PAD_SD2_DATA3__SD2_DATA3 0x5a
595 >;
596 };
597
598 pinctrl_usdhc2_200mhz: usdhc2grp_200mhz {
599 fsl,pins = <
600 MX7D_PAD_SD2_CMD__SD2_CMD 0x5b
601 MX7D_PAD_SD2_CLK__SD2_CLK 0x1b
602 MX7D_PAD_SD2_DATA0__SD2_DATA0 0x5b
603 MX7D_PAD_SD2_DATA1__SD2_DATA1 0x5b
604 MX7D_PAD_SD2_DATA2__SD2_DATA2 0x5b
605 MX7D_PAD_SD2_DATA3__SD2_DATA3 0x5b
606 >;
607 };
608
609
610 pinctrl_usdhc3: usdhc3grp {
611 fsl,pins = <
612 MX7D_PAD_SD3_CMD__SD3_CMD 0x59
613 MX7D_PAD_SD3_CLK__SD3_CLK 0x19
614 MX7D_PAD_SD3_DATA0__SD3_DATA0 0x59
615 MX7D_PAD_SD3_DATA1__SD3_DATA1 0x59
616 MX7D_PAD_SD3_DATA2__SD3_DATA2 0x59
617 MX7D_PAD_SD3_DATA3__SD3_DATA3 0x59
618 MX7D_PAD_SD3_DATA4__SD3_DATA4 0x59
619 MX7D_PAD_SD3_DATA5__SD3_DATA5 0x59
620 MX7D_PAD_SD3_DATA6__SD3_DATA6 0x59
621 MX7D_PAD_SD3_DATA7__SD3_DATA7 0x59
622 MX7D_PAD_SD3_STROBE__SD3_STROBE 0x19
623 >;
624 };
625
626 pinctrl_usdhc3_100mhz: usdhc3grp_100mhz {
627 fsl,pins = <
628 MX7D_PAD_SD3_CMD__SD3_CMD 0x5a
629 MX7D_PAD_SD3_CLK__SD3_CLK 0x1a
630 MX7D_PAD_SD3_DATA0__SD3_DATA0 0x5a
631 MX7D_PAD_SD3_DATA1__SD3_DATA1 0x5a
632 MX7D_PAD_SD3_DATA2__SD3_DATA2 0x5a
633 MX7D_PAD_SD3_DATA3__SD3_DATA3 0x5a
634 MX7D_PAD_SD3_DATA4__SD3_DATA4 0x5a
635 MX7D_PAD_SD3_DATA5__SD3_DATA5 0x5a
636 MX7D_PAD_SD3_DATA6__SD3_DATA6 0x5a
637 MX7D_PAD_SD3_DATA7__SD3_DATA7 0x5a
638 MX7D_PAD_SD3_STROBE__SD3_STROBE 0x1a
639 >;
640 };
641
642 pinctrl_usdhc3_200mhz: usdhc3grp_200mhz {
643 fsl,pins = <
644 MX7D_PAD_SD3_CMD__SD3_CMD 0x5b
645 MX7D_PAD_SD3_CLK__SD3_CLK 0x1b
646 MX7D_PAD_SD3_DATA0__SD3_DATA0 0x5b
647 MX7D_PAD_SD3_DATA1__SD3_DATA1 0x5b
648 MX7D_PAD_SD3_DATA2__SD3_DATA2 0x5b
649 MX7D_PAD_SD3_DATA3__SD3_DATA3 0x5b
650 MX7D_PAD_SD3_DATA4__SD3_DATA4 0x5b
651 MX7D_PAD_SD3_DATA5__SD3_DATA5 0x5b
652 MX7D_PAD_SD3_DATA6__SD3_DATA6 0x5b
653 MX7D_PAD_SD3_DATA7__SD3_DATA7 0x5b
654 MX7D_PAD_SD3_STROBE__SD3_STROBE 0x1b
655 >;
656 };
9a20aa26
SH		 657 };
658};
5db106bc 659
9a20aa26
SH		 660&iomuxc_lpsr {
661 pinctrl_wdog: wdoggrp {
662 fsl,pins = <
37de44f2 663 MX7D_PAD_LPSR_GPIO1_IO00__WDOG1_WDOG_B 0x74
9a20aa26
SH		 664 >;
665 };
666
667 pinctrl_pwm1: pwm1grp {
668 fsl,pins = <
213e51ca 669 MX7D_PAD_LPSR_GPIO1_IO01__PWM1_OUT 0x110b0
9a20aa26 670 >;
184f39b5
AS		 671
672 pinctrl_spi4: spi4grp {
673 fsl,pins = <
674 MX7D_PAD_GPIO1_IO09__GPIO1_IO9 0x59
675 MX7D_PAD_GPIO1_IO12__GPIO1_IO12 0x59
676 MX7D_PAD_GPIO1_IO13__GPIO1_IO13 0x59
677 >;
678 };
5db106bc
FL		 679 };
680};
Linux 6.x block layer and io_uring tree(s)