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1 | /* |
2 | * Copyright 2016 Boundary Devices, Inc. | |
3 | * | |
4 | * This file is dual-licensed: you can use it either under the terms | |
5 | * of the GPL or the X11 license, at your option. Note that this dual | |
6 | * licensing only applies to this file, and not this project as a | |
7 | * whole. | |
8 | * | |
9 | * a) This file is free software; you can redistribute it and/or | |
10 | * modify it under the terms of the GNU General Public License as | |
11 | * published by the Free Software Foundation; either version 2 of the | |
12 | * License, or (at your option) any later version. | |
13 | * | |
14 | * This file is distributed in the hope that it will be useful, | |
15 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
16 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
17 | * GNU General Public License for more details. | |
18 | * | |
19 | * Or, alternatively, | |
20 | * | |
21 | * b) Permission is hereby granted, free of charge, to any person | |
22 | * obtaining a copy of this software and associated documentation | |
23 | * files (the "Software"), to deal in the Software without | |
24 | * restriction, including without limitation the rights to use, | |
25 | * copy, modify, merge, publish, distribute, sublicense, and/or | |
26 | * sell copies of the Software, and to permit persons to whom the | |
27 | * Software is furnished to do so, subject to the following | |
28 | * conditions: | |
29 | * | |
30 | * The above copyright notice and this permission notice shall be | |
31 | * included in all copies or substantial portions of the Software. | |
32 | * | |
33 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, | |
34 | * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES | |
35 | * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND | |
36 | * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT | |
37 | * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, | |
38 | * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING | |
39 | * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR | |
40 | * OTHER DEALINGS IN THE SOFTWARE. | |
41 | */ | |
42 | ||
43 | /dts-v1/; | |
44 | ||
45 | #include <dt-bindings/input/input.h> | |
46 | #include "imx7d.dtsi" | |
47 | ||
48 | / { | |
49 | model = "Boundary Devices i.MX7 Nitrogen7 Board"; | |
50 | compatible = "boundary,imx7d-nitrogen7", "fsl,imx7d"; | |
51 | ||
52 | aliases { | |
53 | fb_lcd = &lcdif; | |
54 | t_lcd = &t_lcd; | |
55 | }; | |
56 | ||
57 | memory { | |
58 | reg = <0x80000000 0x40000000>; | |
59 | }; | |
60 | ||
61 | backlight-j9 { | |
62 | compatible = "gpio-backlight"; | |
63 | pinctrl-names = "default"; | |
64 | pinctrl-0 = <&pinctrl_backlight_j9>; | |
65 | gpios = <&gpio1 7 GPIO_ACTIVE_HIGH>; | |
66 | default-on; | |
67 | }; | |
68 | ||
69 | backlight-j20 { | |
70 | compatible = "pwm-backlight"; | |
71 | pwms = <&pwm1 0 5000000>; | |
72 | brightness-levels = <0 4 8 16 32 64 128 255>; | |
73 | default-brightness-level = <6>; | |
74 | status = "okay"; | |
75 | }; | |
76 | ||
77 | reg_usb_otg1_vbus: regulator-usb-otg1-vbus { | |
78 | compatible = "regulator-fixed"; | |
79 | regulator-name = "usb_otg1_vbus"; | |
80 | regulator-min-microvolt = <5000000>; | |
81 | regulator-max-microvolt = <5000000>; | |
82 | gpio = <&gpio1 5 GPIO_ACTIVE_HIGH>; | |
83 | enable-active-high; | |
84 | }; | |
85 | ||
86 | reg_usb_otg2_vbus: regulator-usb-otg2-vbus { | |
87 | compatible = "regulator-fixed"; | |
88 | regulator-name = "usb_otg2_vbus"; | |
89 | regulator-min-microvolt = <5000000>; | |
90 | regulator-max-microvolt = <5000000>; | |
91 | gpio = <&gpio4 7 GPIO_ACTIVE_HIGH>; | |
92 | enable-active-high; | |
93 | }; | |
94 | ||
95 | reg_can2_3v3: regulator-can2-3v3 { | |
96 | compatible = "regulator-fixed"; | |
97 | regulator-name = "can2-3v3"; | |
98 | regulator-min-microvolt = <3300000>; | |
99 | regulator-max-microvolt = <3300000>; | |
100 | gpio = <&gpio2 14 GPIO_ACTIVE_LOW>; | |
101 | }; | |
102 | ||
103 | reg_vref_1v8: regulator-vref-1v8 { | |
104 | compatible = "regulator-fixed"; | |
105 | regulator-name = "vref-1v8"; | |
106 | regulator-min-microvolt = <1800000>; | |
107 | regulator-max-microvolt = <1800000>; | |
108 | }; | |
109 | ||
110 | reg_vref_3v3: regulator-vref-3v3 { | |
111 | compatible = "regulator-fixed"; | |
112 | regulator-name = "vref-3v3"; | |
113 | regulator-min-microvolt = <3300000>; | |
114 | regulator-max-microvolt = <3300000>; | |
115 | }; | |
116 | ||
117 | reg_wlan: regulator-wlan { | |
118 | compatible = "regulator-fixed"; | |
119 | regulator-min-microvolt = <3300000>; | |
120 | regulator-max-microvolt = <3300000>; | |
121 | clocks = <&clks IMX7D_CLKO2_ROOT_DIV>; | |
122 | clock-names = "slow"; | |
123 | regulator-name = "reg_wlan"; | |
124 | startup-delay-us = <70000>; | |
125 | gpio = <&gpio4 21 GPIO_ACTIVE_HIGH>; | |
126 | enable-active-high; | |
127 | }; | |
128 | }; | |
129 | ||
130 | &adc1 { | |
131 | vref-supply = <®_vref_1v8>; | |
132 | status = "okay"; | |
133 | }; | |
134 | ||
135 | &adc2 { | |
136 | vref-supply = <®_vref_1v8>; | |
137 | status = "okay"; | |
138 | }; | |
139 | ||
140 | &clks { | |
141 | assigned-clocks = <&clks IMX7D_CLKO2_ROOT_SRC>, | |
142 | <&clks IMX7D_CLKO2_ROOT_DIV>; | |
143 | assigned-clock-parents = <&clks IMX7D_CKIL>; | |
144 | assigned-clock-rates = <0>, <32768>; | |
145 | }; | |
146 | ||
147 | &cpu0 { | |
148 | arm-supply = <&sw1a_reg>; | |
149 | }; | |
150 | ||
151 | &fec1 { | |
152 | pinctrl-names = "default"; | |
153 | pinctrl-0 = <&pinctrl_enet1>; | |
154 | assigned-clocks = <&clks IMX7D_ENET1_TIME_ROOT_SRC>, | |
155 | <&clks IMX7D_ENET1_TIME_ROOT_CLK>; | |
156 | assigned-clock-parents = <&clks IMX7D_PLL_ENET_MAIN_100M_CLK>; | |
157 | assigned-clock-rates = <0>, <100000000>; | |
158 | phy-mode = "rgmii"; | |
159 | phy-handle = <ðphy0>; | |
160 | fsl,magic-packet; | |
161 | status = "okay"; | |
162 | ||
163 | mdio { | |
164 | #address-cells = <1>; | |
165 | #size-cells = <0>; | |
166 | ||
167 | ethphy0: ethernet-phy@4 { | |
168 | reg = <4>; | |
169 | }; | |
170 | }; | |
171 | }; | |
172 | ||
173 | &flexcan2 { | |
174 | pinctrl-names = "default"; | |
175 | pinctrl-0 = <&pinctrl_flexcan2>; | |
176 | xceiver-supply = <®_can2_3v3>; | |
177 | status = "okay"; | |
178 | }; | |
179 | ||
180 | &i2c1 { | |
181 | pinctrl-names = "default"; | |
182 | pinctrl-0 = <&pinctrl_i2c1>; | |
183 | status = "okay"; | |
184 | ||
185 | pmic: pfuze3000@08 { | |
186 | compatible = "fsl,pfuze3000"; | |
187 | reg = <0x08>; | |
188 | ||
189 | regulators { | |
190 | sw1a_reg: sw1a { | |
191 | regulator-min-microvolt = <700000>; | |
192 | regulator-max-microvolt = <1475000>; | |
193 | regulator-boot-on; | |
194 | regulator-always-on; | |
195 | regulator-ramp-delay = <6250>; | |
196 | }; | |
197 | ||
198 | /* use sw1c_reg to align with pfuze100/pfuze200 */ | |
199 | sw1c_reg: sw1b { | |
200 | regulator-min-microvolt = <700000>; | |
201 | regulator-max-microvolt = <1475000>; | |
202 | regulator-boot-on; | |
203 | regulator-always-on; | |
204 | regulator-ramp-delay = <6250>; | |
205 | }; | |
206 | ||
207 | sw2_reg: sw2 { | |
208 | regulator-min-microvolt = <1500000>; | |
209 | regulator-max-microvolt = <1850000>; | |
210 | regulator-boot-on; | |
211 | regulator-always-on; | |
212 | }; | |
213 | ||
214 | sw3a_reg: sw3 { | |
215 | regulator-min-microvolt = <900000>; | |
216 | regulator-max-microvolt = <1650000>; | |
217 | regulator-boot-on; | |
218 | regulator-always-on; | |
219 | }; | |
220 | ||
221 | swbst_reg: swbst { | |
222 | regulator-min-microvolt = <5000000>; | |
223 | regulator-max-microvolt = <5150000>; | |
224 | }; | |
225 | ||
226 | snvs_reg: vsnvs { | |
227 | regulator-min-microvolt = <1000000>; | |
228 | regulator-max-microvolt = <3000000>; | |
229 | regulator-boot-on; | |
230 | regulator-always-on; | |
231 | }; | |
232 | ||
233 | vref_reg: vrefddr { | |
234 | regulator-boot-on; | |
235 | regulator-always-on; | |
236 | }; | |
237 | ||
238 | vgen1_reg: vldo1 { | |
239 | regulator-min-microvolt = <1800000>; | |
240 | regulator-max-microvolt = <3300000>; | |
241 | regulator-always-on; | |
242 | }; | |
243 | ||
244 | vgen2_reg: vldo2 { | |
245 | regulator-min-microvolt = <800000>; | |
246 | regulator-max-microvolt = <1550000>; | |
247 | regulator-always-on; | |
248 | }; | |
249 | ||
250 | vgen3_reg: vccsd { | |
251 | regulator-min-microvolt = <2850000>; | |
252 | regulator-max-microvolt = <3300000>; | |
253 | regulator-always-on; | |
254 | }; | |
255 | ||
256 | vgen4_reg: v33 { | |
257 | regulator-min-microvolt = <2850000>; | |
258 | regulator-max-microvolt = <3300000>; | |
259 | regulator-always-on; | |
260 | }; | |
261 | ||
262 | vgen5_reg: vldo3 { | |
263 | regulator-min-microvolt = <1800000>; | |
264 | regulator-max-microvolt = <3300000>; | |
265 | regulator-always-on; | |
266 | }; | |
267 | ||
268 | vgen6_reg: vldo4 { | |
269 | regulator-min-microvolt = <1800000>; | |
270 | regulator-max-microvolt = <3300000>; | |
271 | regulator-always-on; | |
272 | }; | |
273 | }; | |
274 | }; | |
275 | }; | |
276 | ||
277 | &i2c2 { | |
278 | pinctrl-names = "default"; | |
279 | pinctrl-0 = <&pinctrl_i2c2>; | |
280 | status = "okay"; | |
281 | ||
282 | rtc@68 { | |
283 | compatible = "rv4162"; | |
284 | pinctrl-names = "default"; | |
285 | pinctrl-0 = <&pinctrl_i2c2_rv4162>; | |
286 | reg = <0x68>; | |
287 | interrupts-extended = <&gpio2 15 IRQ_TYPE_LEVEL_LOW>; | |
288 | }; | |
289 | }; | |
290 | ||
291 | &i2c3 { | |
292 | pinctrl-names = "default"; | |
293 | pinctrl-0 = <&pinctrl_i2c3>; | |
294 | status = "okay"; | |
295 | ||
296 | touch@48 { | |
297 | compatible = "ti,tsc2004"; | |
298 | reg = <0x48>; | |
299 | pinctrl-names = "default"; | |
300 | pinctrl-0 = <&pinctrl_i2c3_tsc2004>; | |
301 | interrupts-extended = <&gpio3 4 IRQ_TYPE_EDGE_FALLING>; | |
302 | wakeup-gpios = <&gpio3 4 GPIO_ACTIVE_LOW>; | |
303 | }; | |
304 | }; | |
305 | ||
306 | &i2c4 { | |
307 | pinctrl-names = "default"; | |
308 | pinctrl-0 = <&pinctrl_i2c4>; | |
309 | status = "okay"; | |
310 | ||
311 | codec: wm8960@1a { | |
312 | compatible = "wlf,wm8960"; | |
313 | reg = <0x1a>; | |
314 | clocks = <&clks IMX7D_AUDIO_MCLK_ROOT_CLK>; | |
315 | clock-names = "mclk"; | |
316 | wlf,shared-lrclk; | |
317 | }; | |
318 | }; | |
319 | ||
320 | &lcdif { | |
321 | pinctrl-names = "default"; | |
322 | pinctrl-0 = <&pinctrl_lcdif_dat | |
323 | &pinctrl_lcdif_ctrl>; | |
324 | lcd-supply = <®_vref_3v3>; | |
325 | display = <&display0>; | |
326 | status = "okay"; | |
327 | ||
328 | display0: lcd-display { | |
329 | bits-per-pixel = <16>; | |
330 | bus-width = <18>; | |
331 | ||
332 | display-timings { | |
333 | native-mode = <&t_lcd>; | |
334 | t_lcd: t_lcd_default { | |
335 | /* default to Okaya display */ | |
336 | clock-frequency = <30000000>; | |
337 | hactive = <800>; | |
338 | vactive = <480>; | |
339 | hfront-porch = <40>; | |
340 | hback-porch = <40>; | |
341 | hsync-len = <48>; | |
342 | vback-porch = <29>; | |
343 | vfront-porch = <13>; | |
344 | vsync-len = <3>; | |
345 | hsync-active = <0>; | |
346 | vsync-active = <0>; | |
347 | de-active = <1>; | |
348 | pixelclk-active = <0>; | |
349 | }; | |
350 | }; | |
351 | }; | |
352 | }; | |
353 | ||
354 | &pwm1 { | |
355 | pinctrl-names = "default"; | |
356 | pinctrl-0 = <&pinctrl_pwm1>; | |
357 | status = "okay"; | |
358 | }; | |
359 | ||
360 | &pwm2 { | |
361 | pinctrl-names = "default"; | |
362 | pinctrl-0 = <&pinctrl_pwm2>; | |
363 | status = "okay"; | |
364 | }; | |
365 | ||
366 | &uart1 { | |
367 | pinctrl-names = "default"; | |
368 | pinctrl-0 = <&pinctrl_uart1>; | |
369 | assigned-clocks = <&clks IMX7D_UART1_ROOT_SRC>; | |
370 | assigned-clock-parents = <&clks IMX7D_OSC_24M_CLK>; | |
371 | status = "okay"; | |
372 | }; | |
373 | ||
374 | &uart2 { | |
375 | pinctrl-names = "default"; | |
376 | pinctrl-0 = <&pinctrl_uart2>; | |
377 | assigned-clocks = <&clks IMX7D_UART2_ROOT_SRC>; | |
378 | assigned-clock-parents = <&clks IMX7D_OSC_24M_CLK>; | |
379 | status = "okay"; | |
380 | }; | |
381 | ||
382 | &uart3 { | |
383 | pinctrl-names = "default"; | |
384 | pinctrl-0 = <&pinctrl_uart3>; | |
385 | assigned-clocks = <&clks IMX7D_UART3_ROOT_SRC>; | |
386 | assigned-clock-parents = <&clks IMX7D_OSC_24M_CLK>; | |
387 | status = "okay"; | |
388 | }; | |
389 | ||
390 | &uart6 { | |
391 | pinctrl-names = "default"; | |
392 | pinctrl-0 = <&pinctrl_uart6>; | |
393 | assigned-clocks = <&clks IMX7D_UART6_ROOT_SRC>; | |
394 | assigned-clock-parents = <&clks IMX7D_PLL_SYS_MAIN_240M_CLK>; | |
2e7c416c | 395 | uart-has-rtscts; |
56354959 GB |
396 | status = "okay"; |
397 | }; | |
398 | ||
399 | &usbotg1 { | |
400 | vbus-supply = <®_usb_otg1_vbus>; | |
401 | pinctrl-names = "default"; | |
402 | pinctrl-0 = <&pinctrl_usbotg1>; | |
403 | status = "okay"; | |
404 | }; | |
405 | ||
406 | &usbotg2 { | |
407 | vbus-supply = <®_usb_otg2_vbus>; | |
408 | pinctrl-names = "default"; | |
409 | pinctrl-0 = <&pinctrl_usbotg2>; | |
410 | dr_mode = "host"; | |
411 | status = "okay"; | |
412 | }; | |
413 | ||
414 | &usdhc1 { | |
415 | pinctrl-names = "default"; | |
416 | pinctrl-0 = <&pinctrl_usdhc1>; | |
417 | cd-gpios = <&gpio5 0 GPIO_ACTIVE_LOW>; | |
418 | vmmc-supply = <&vgen3_reg>; | |
419 | bus-width = <4>; | |
420 | fsl,tuning-step = <2>; | |
421 | wakeup-source; | |
422 | keep-power-in-suspend; | |
423 | status = "okay"; | |
424 | }; | |
425 | ||
426 | &usdhc2 { | |
427 | #address-cells = <1>; | |
428 | #size-cells = <0>; | |
429 | pinctrl-names = "default"; | |
430 | pinctrl-0 = <&pinctrl_usdhc2>; | |
431 | bus-width = <4>; | |
432 | non-removable; | |
433 | vmmc-supply = <®_wlan>; | |
434 | cap-power-off-card; | |
435 | keep-power-in-suspend; | |
436 | status = "okay"; | |
437 | ||
438 | wlcore: wlcore@2 { | |
439 | compatible = "ti,wl1271"; | |
440 | reg = <2>; | |
441 | interrupt-parent = <&gpio4>; | |
442 | interrupts = <20 IRQ_TYPE_LEVEL_HIGH>; | |
443 | ref-clock-frequency = <38400000>; | |
444 | }; | |
445 | }; | |
446 | ||
447 | &usdhc3 { | |
448 | pinctrl-names = "default"; | |
449 | pinctrl-0 = <&pinctrl_usdhc3>; | |
450 | assigned-clocks = <&clks IMX7D_USDHC3_ROOT_CLK>; | |
451 | assigned-clock-rates = <400000000>; | |
452 | bus-width = <8>; | |
453 | fsl,tuning-step = <2>; | |
454 | non-removable; | |
455 | status = "okay"; | |
456 | }; | |
457 | ||
458 | &wdog1 { | |
459 | pinctrl-names = "default"; | |
460 | pinctrl-0 = <&pinctrl_wdog1>; | |
461 | status = "okay"; | |
462 | }; | |
463 | ||
464 | &iomuxc { | |
465 | pinctrl-names = "default"; | |
466 | pinctrl-0 = <&pinctrl_hog_1 &pinctrl_j2>; | |
467 | ||
468 | pinctrl_hog_1: hoggrp-1 { | |
469 | fsl,pins = < | |
470 | MX7D_PAD_SD3_RESET_B__GPIO6_IO11 0x5d | |
471 | MX7D_PAD_GPIO1_IO13__GPIO1_IO13 0x7d | |
472 | MX7D_PAD_ECSPI2_MISO__GPIO4_IO22 0x7d | |
473 | >; | |
474 | }; | |
475 | ||
476 | pinctrl_enet1: enet1grp { | |
477 | fsl,pins = < | |
478 | MX7D_PAD_GPIO1_IO10__ENET1_MDIO 0x3 | |
479 | MX7D_PAD_GPIO1_IO11__ENET1_MDC 0x3 | |
480 | MX7D_PAD_GPIO1_IO12__CCM_ENET_REF_CLK1 0x3 | |
481 | MX7D_PAD_ENET1_RGMII_TXC__ENET1_RGMII_TXC 0x71 | |
482 | MX7D_PAD_ENET1_RGMII_TD0__ENET1_RGMII_TD0 0x71 | |
483 | MX7D_PAD_ENET1_RGMII_TD1__ENET1_RGMII_TD1 0x71 | |
484 | MX7D_PAD_ENET1_RGMII_TD2__ENET1_RGMII_TD2 0x71 | |
485 | MX7D_PAD_ENET1_RGMII_TD3__ENET1_RGMII_TD3 0x71 | |
486 | MX7D_PAD_ENET1_RGMII_TX_CTL__ENET1_RGMII_TX_CTL 0x71 | |
487 | MX7D_PAD_ENET1_RGMII_RXC__ENET1_RGMII_RXC 0x71 | |
488 | MX7D_PAD_ENET1_RGMII_RD0__ENET1_RGMII_RD0 0x11 | |
489 | MX7D_PAD_ENET1_RGMII_RD1__ENET1_RGMII_RD1 0x11 | |
490 | MX7D_PAD_ENET1_RGMII_RD2__ENET1_RGMII_RD2 0x11 | |
491 | MX7D_PAD_ENET1_RGMII_RD3__ENET1_RGMII_RD3 0x71 | |
492 | MX7D_PAD_ENET1_RGMII_RX_CTL__ENET1_RGMII_RX_CTL 0x11 | |
493 | MX7D_PAD_SD3_STROBE__GPIO6_IO10 0x75 | |
494 | >; | |
495 | }; | |
496 | ||
497 | pinctrl_flexcan2: flexcan2grp { | |
498 | fsl,pins = < | |
499 | MX7D_PAD_GPIO1_IO14__FLEXCAN2_RX 0x7d | |
500 | MX7D_PAD_GPIO1_IO15__FLEXCAN2_TX 0x7d | |
501 | MX7D_PAD_EPDC_DATA14__GPIO2_IO14 0x7d | |
502 | >; | |
503 | }; | |
504 | ||
505 | pinctrl_i2c1: i2c1grp { | |
506 | fsl,pins = < | |
507 | MX7D_PAD_I2C1_SDA__I2C1_SDA 0x4000007f | |
508 | MX7D_PAD_I2C1_SCL__I2C1_SCL 0x4000007f | |
509 | >; | |
510 | }; | |
511 | ||
512 | pinctrl_i2c2: i2c2grp { | |
513 | fsl,pins = < | |
514 | MX7D_PAD_I2C2_SDA__I2C2_SDA 0x4000007f | |
515 | MX7D_PAD_I2C2_SCL__I2C2_SCL 0x4000007f | |
516 | >; | |
517 | }; | |
518 | ||
519 | pinctrl_i2c2_rv4162: i2c2-rv4162grp { | |
520 | fsl,pins = < | |
521 | MX7D_PAD_EPDC_DATA15__GPIO2_IO15 0x7d | |
522 | >; | |
523 | }; | |
524 | ||
525 | pinctrl_i2c3: i2c3grp { | |
526 | fsl,pins = < | |
527 | MX7D_PAD_I2C3_SDA__I2C3_SDA 0x4000007f | |
528 | MX7D_PAD_I2C3_SCL__I2C3_SCL 0x4000007f | |
529 | >; | |
530 | }; | |
531 | ||
532 | pinctrl_i2c3_tsc2004: i2c3tsc2004grp { | |
533 | fsl,pins = < | |
534 | MX7D_PAD_LCD_RESET__GPIO3_IO4 0x79 | |
535 | MX7D_PAD_SD2_WP__GPIO5_IO10 0x7d | |
536 | >; | |
537 | }; | |
538 | ||
539 | pinctrl_i2c4: i2c4grp { | |
540 | fsl,pins = < | |
541 | MX7D_PAD_I2C4_SDA__I2C4_SDA 0x4000007f | |
542 | MX7D_PAD_I2C4_SCL__I2C4_SCL 0x4000007f | |
543 | >; | |
544 | }; | |
545 | ||
546 | pinctrl_j2: j2grp { | |
547 | fsl,pins = < | |
548 | MX7D_PAD_SAI1_TX_DATA__GPIO6_IO15 0x7d | |
549 | MX7D_PAD_EPDC_BDR0__GPIO2_IO28 0x7d | |
550 | MX7D_PAD_SAI1_RX_DATA__GPIO6_IO12 0x7d | |
551 | MX7D_PAD_EPDC_BDR1__GPIO2_IO29 0x7d | |
552 | MX7D_PAD_SD1_WP__GPIO5_IO1 0x7d | |
553 | MX7D_PAD_EPDC_SDSHR__GPIO2_IO19 0x7d | |
554 | MX7D_PAD_SD1_RESET_B__GPIO5_IO2 0x7d | |
555 | MX7D_PAD_SD2_RESET_B__GPIO5_IO11 0x7d | |
556 | MX7D_PAD_EPDC_DATA07__GPIO2_IO7 0x7d | |
557 | MX7D_PAD_EPDC_DATA08__GPIO2_IO8 0x7d | |
558 | MX7D_PAD_EPDC_DATA09__GPIO2_IO9 0x7d | |
559 | MX7D_PAD_EPDC_DATA10__GPIO2_IO10 0x7d | |
560 | MX7D_PAD_EPDC_DATA11__GPIO2_IO11 0x7d | |
561 | MX7D_PAD_EPDC_DATA12__GPIO2_IO12 0x7d | |
562 | MX7D_PAD_SAI1_TX_SYNC__GPIO6_IO14 0x7d | |
563 | MX7D_PAD_EPDC_DATA13__GPIO2_IO13 0x7d | |
564 | MX7D_PAD_SAI1_TX_BCLK__GPIO6_IO13 0x7d | |
565 | MX7D_PAD_SD2_CD_B__GPIO5_IO9 0x7d | |
566 | MX7D_PAD_EPDC_GDCLK__GPIO2_IO24 0x7d | |
567 | MX7D_PAD_SAI2_RX_DATA__GPIO6_IO21 0x7d | |
568 | MX7D_PAD_EPDC_GDOE__GPIO2_IO25 0x7d | |
569 | MX7D_PAD_EPDC_GDRL__GPIO2_IO26 0x7d | |
570 | MX7D_PAD_SAI2_TX_DATA__GPIO6_IO22 0x7d | |
571 | MX7D_PAD_EPDC_SDCE0__GPIO2_IO20 0x7d | |
572 | MX7D_PAD_SAI2_TX_BCLK__GPIO6_IO20 0x7d | |
573 | MX7D_PAD_EPDC_SDCE1__GPIO2_IO21 0x7d | |
574 | MX7D_PAD_SAI2_TX_SYNC__GPIO6_IO19 0x7d | |
575 | MX7D_PAD_EPDC_SDCE2__GPIO2_IO22 0x7d | |
576 | MX7D_PAD_EPDC_SDCE3__GPIO2_IO23 0x7d | |
577 | MX7D_PAD_EPDC_GDSP__GPIO2_IO27 0x7d | |
578 | MX7D_PAD_EPDC_SDCLK__GPIO2_IO16 0x7d | |
579 | MX7D_PAD_EPDC_SDLE__GPIO2_IO17 0x7d | |
580 | MX7D_PAD_EPDC_SDOE__GPIO2_IO18 0x7d | |
581 | MX7D_PAD_EPDC_PWR_COM__GPIO2_IO30 0x7d | |
582 | MX7D_PAD_EPDC_PWR_STAT__GPIO2_IO31 0x7d | |
583 | >; | |
584 | }; | |
585 | ||
586 | pinctrl_lcdif_dat: lcdifdatgrp { | |
587 | fsl,pins = < | |
588 | MX7D_PAD_LCD_DATA00__LCD_DATA0 0x79 | |
589 | MX7D_PAD_LCD_DATA01__LCD_DATA1 0x79 | |
590 | MX7D_PAD_LCD_DATA02__LCD_DATA2 0x79 | |
591 | MX7D_PAD_LCD_DATA03__LCD_DATA3 0x79 | |
592 | MX7D_PAD_LCD_DATA04__LCD_DATA4 0x79 | |
593 | MX7D_PAD_LCD_DATA05__LCD_DATA5 0x79 | |
594 | MX7D_PAD_LCD_DATA06__LCD_DATA6 0x79 | |
595 | MX7D_PAD_LCD_DATA07__LCD_DATA7 0x79 | |
596 | MX7D_PAD_LCD_DATA08__LCD_DATA8 0x79 | |
597 | MX7D_PAD_LCD_DATA09__LCD_DATA9 0x79 | |
598 | MX7D_PAD_LCD_DATA10__LCD_DATA10 0x79 | |
599 | MX7D_PAD_LCD_DATA11__LCD_DATA11 0x79 | |
600 | MX7D_PAD_LCD_DATA12__LCD_DATA12 0x79 | |
601 | MX7D_PAD_LCD_DATA13__LCD_DATA13 0x79 | |
602 | MX7D_PAD_LCD_DATA14__LCD_DATA14 0x79 | |
603 | MX7D_PAD_LCD_DATA15__LCD_DATA15 0x79 | |
604 | MX7D_PAD_LCD_DATA16__LCD_DATA16 0x79 | |
605 | MX7D_PAD_LCD_DATA17__LCD_DATA17 0x79 | |
606 | MX7D_PAD_LCD_DATA18__LCD_DATA18 0x79 | |
607 | MX7D_PAD_LCD_DATA19__LCD_DATA19 0x79 | |
608 | MX7D_PAD_LCD_DATA20__LCD_DATA20 0x79 | |
609 | MX7D_PAD_LCD_DATA21__LCD_DATA21 0x79 | |
610 | MX7D_PAD_LCD_DATA22__LCD_DATA22 0x79 | |
611 | MX7D_PAD_LCD_DATA23__LCD_DATA23 0x79 | |
612 | >; | |
613 | }; | |
614 | ||
615 | pinctrl_lcdif_ctrl: lcdifctrlgrp { | |
616 | fsl,pins = < | |
617 | MX7D_PAD_LCD_CLK__LCD_CLK 0x79 | |
618 | MX7D_PAD_LCD_ENABLE__LCD_ENABLE 0x79 | |
619 | MX7D_PAD_LCD_VSYNC__LCD_VSYNC 0x79 | |
620 | MX7D_PAD_LCD_HSYNC__LCD_HSYNC 0x79 | |
621 | >; | |
622 | }; | |
623 | ||
624 | pinctrl_pwm2: pwm2grp { | |
625 | fsl,pins = < | |
626 | MX7D_PAD_GPIO1_IO09__PWM2_OUT 0x7d | |
627 | >; | |
628 | }; | |
629 | ||
630 | pinctrl_uart1: uart1grp { | |
631 | fsl,pins = < | |
632 | MX7D_PAD_UART1_TX_DATA__UART1_DCE_TX 0x79 | |
633 | MX7D_PAD_UART1_RX_DATA__UART1_DCE_RX 0x79 | |
634 | >; | |
635 | }; | |
636 | ||
637 | pinctrl_uart2: uart2grp { | |
638 | fsl,pins = < | |
639 | MX7D_PAD_UART2_TX_DATA__UART2_DCE_TX 0x79 | |
640 | MX7D_PAD_UART2_RX_DATA__UART2_DCE_RX 0x79 | |
641 | >; | |
642 | }; | |
643 | ||
644 | pinctrl_uart3: uart3grp { | |
645 | fsl,pins = < | |
646 | MX7D_PAD_UART3_TX_DATA__UART3_DCE_TX 0x79 | |
647 | MX7D_PAD_UART3_RX_DATA__UART3_DCE_RX 0x79 | |
648 | MX7D_PAD_EPDC_DATA04__GPIO2_IO4 0x7d | |
649 | >; | |
650 | }; | |
651 | ||
652 | pinctrl_uart6: uart6grp { | |
653 | fsl,pins = < | |
654 | MX7D_PAD_ECSPI1_MOSI__UART6_DCE_TX 0x79 | |
655 | MX7D_PAD_ECSPI1_SCLK__UART6_DCE_RX 0x79 | |
656 | MX7D_PAD_ECSPI1_SS0__UART6_DCE_CTS 0x79 | |
657 | MX7D_PAD_ECSPI1_MISO__UART6_DCE_RTS 0x79 | |
658 | >; | |
659 | }; | |
660 | ||
661 | pinctrl_usbotg2: usbotg2grp { | |
662 | fsl,pins = < | |
663 | MX7D_PAD_UART3_RTS_B__USB_OTG2_OC 0x7d | |
664 | MX7D_PAD_UART3_CTS_B__GPIO4_IO7 0x14 | |
665 | >; | |
666 | }; | |
667 | ||
668 | pinctrl_usdhc1: usdhc1grp { | |
669 | fsl,pins = < | |
670 | MX7D_PAD_SD1_CMD__SD1_CMD 0x59 | |
671 | MX7D_PAD_SD1_CLK__SD1_CLK 0x19 | |
672 | MX7D_PAD_SD1_DATA0__SD1_DATA0 0x59 | |
673 | MX7D_PAD_SD1_DATA1__SD1_DATA1 0x59 | |
674 | MX7D_PAD_SD1_DATA2__SD1_DATA2 0x59 | |
675 | MX7D_PAD_SD1_DATA3__SD1_DATA3 0x59 | |
676 | MX7D_PAD_GPIO1_IO08__SD1_VSELECT 0x75 | |
677 | MX7D_PAD_SD1_CD_B__GPIO5_IO0 0x75 | |
678 | >; | |
679 | }; | |
680 | ||
681 | pinctrl_usdhc2: usdhc2grp { | |
682 | fsl,pins = < | |
683 | MX7D_PAD_SD2_CMD__SD2_CMD 0x59 | |
684 | MX7D_PAD_SD2_CLK__SD2_CLK 0x19 | |
685 | MX7D_PAD_SD2_DATA0__SD2_DATA0 0x59 | |
686 | MX7D_PAD_SD2_DATA1__SD2_DATA1 0x59 | |
687 | MX7D_PAD_SD2_DATA2__SD2_DATA2 0x59 | |
688 | MX7D_PAD_SD2_DATA3__SD2_DATA3 0x59 | |
689 | MX7D_PAD_ECSPI2_SCLK__GPIO4_IO20 0x59 | |
690 | MX7D_PAD_ECSPI2_MOSI__GPIO4_IO21 0x59 | |
691 | >; | |
692 | }; | |
693 | ||
694 | pinctrl_usdhc3: usdhc3grp { | |
695 | fsl,pins = < | |
696 | MX7D_PAD_SD3_CMD__SD3_CMD 0x59 | |
697 | MX7D_PAD_SD3_CLK__SD3_CLK 0x19 | |
698 | MX7D_PAD_SD3_DATA0__SD3_DATA0 0x59 | |
699 | MX7D_PAD_SD3_DATA1__SD3_DATA1 0x59 | |
700 | MX7D_PAD_SD3_DATA2__SD3_DATA2 0x59 | |
701 | MX7D_PAD_SD3_DATA3__SD3_DATA3 0x59 | |
702 | MX7D_PAD_SD3_DATA4__SD3_DATA4 0x59 | |
703 | MX7D_PAD_SD3_DATA5__SD3_DATA5 0x59 | |
704 | MX7D_PAD_SD3_DATA6__SD3_DATA6 0x59 | |
705 | MX7D_PAD_SD3_DATA7__SD3_DATA7 0x59 | |
706 | >; | |
707 | }; | |
708 | }; | |
709 | ||
710 | &iomuxc_lpsr { | |
711 | pinctrl-names = "default"; | |
712 | pinctrl-0 = <&pinctrl_hog_2>; | |
713 | ||
714 | pinctrl_hog_2: hoggrp-2 { | |
715 | fsl,pins = < | |
716 | MX7D_PAD_GPIO1_IO02__GPIO1_IO2 0x7d | |
717 | MX7D_PAD_GPIO1_IO03__CCM_CLKO2 0x7d | |
718 | >; | |
719 | }; | |
720 | ||
721 | pinctrl_backlight_j9: backlightj9grp { | |
722 | fsl,pins = < | |
723 | MX7D_PAD_GPIO1_IO07__GPIO1_IO7 0x7d | |
724 | >; | |
725 | }; | |
726 | ||
727 | pinctrl_pwm1: pwm1grp { | |
728 | fsl,pins = < | |
729 | MX7D_PAD_GPIO1_IO01__PWM1_OUT 0x7d | |
730 | >; | |
731 | }; | |
732 | ||
733 | pinctrl_usbotg1: usbotg1grp { | |
734 | fsl,pins = < | |
735 | MX7D_PAD_GPIO1_IO04__USB_OTG1_OC 0x7d | |
736 | MX7D_PAD_GPIO1_IO05__GPIO1_IO5 0x14 | |
737 | >; | |
738 | }; | |
739 | ||
740 | pinctrl_wdog1: wdog1grp { | |
741 | fsl,pins = < | |
742 | MX7D_PAD_GPIO1_IO00__WDOD1_WDOG_B 0x75 | |
743 | >; | |
744 | }; | |
745 | }; |