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5434c913 LW |
1 | /* |
2 | * Copyright 2015 Lothar Waßmann <LW@KARO-electronics.de> | |
3 | * | |
4 | * This file is dual-licensed: you can use it either under the terms | |
5 | * of the GPL or the X11 license, at your option. Note that this dual | |
6 | * licensing only applies to this file, and not this project as a | |
7 | * whole. | |
8 | * | |
9 | * a) This file is free software; you can redistribute it and/or | |
10 | * modify it under the terms of the GNU General Public License | |
11 | * version 2 as published by the Free Software Foundation. | |
12 | * | |
13 | * This file is distributed in the hope that it will be useful, | |
14 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
15 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
16 | * GNU General Public License for more details. | |
17 | * | |
18 | * Or, alternatively, | |
19 | * | |
20 | * b) Permission is hereby granted, free of charge, to any person | |
21 | * obtaining a copy of this software and associated documentation | |
22 | * files (the "Software"), to deal in the Software without | |
23 | * restriction, including without limitation the rights to use, | |
24 | * copy, modify, merge, publish, distribute, sublicense, and/or | |
25 | * sell copies of the Software, and to permit persons to whom the | |
26 | * Software is furnished to do so, subject to the following | |
27 | * conditions: | |
28 | * | |
29 | * The above copyright notice and this permission notice shall be | |
30 | * included in all copies or substantial portions of the Software. | |
31 | * | |
32 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, | |
33 | * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES | |
34 | * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND | |
35 | * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT | |
36 | * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, | |
37 | * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING | |
38 | * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR | |
39 | * OTHER DEALINGS IN THE SOFTWARE. | |
40 | */ | |
41 | ||
42 | #include <dt-bindings/gpio/gpio.h> | |
43 | #include <dt-bindings/interrupt-controller/irq.h> | |
44 | #include <dt-bindings/pwm/pwm.h> | |
45 | ||
46 | / { | |
47 | aliases { | |
48 | can0 = &can2; | |
49 | can1 = &can1; | |
50 | display = &display; | |
51 | i2c0 = &i2c2; | |
52 | i2c1 = &i2c_gpio; | |
53 | i2c2 = &i2c1; | |
54 | i2c3 = &i2c3; | |
55 | i2c4 = &i2c4; | |
56 | lcdif_23bit_pins_a = &pinctrl_disp0_1; | |
57 | lcdif_24bit_pins_a = &pinctrl_disp0_2; | |
58 | pwm0 = &pwm5; | |
59 | reg_can_xcvr = ®_can_xcvr; | |
60 | serial2 = &uart5; | |
61 | serial4 = &uart3; | |
62 | spi0 = &ecspi2; | |
63 | spi1 = &spi_gpio; | |
64 | stk5led = &user_led; | |
65 | usbh1 = &usbotg2; | |
66 | usbotg = &usbotg1; | |
67 | }; | |
68 | ||
69 | chosen { | |
70 | stdout-path = &uart1; | |
71 | }; | |
72 | ||
73 | memory { | |
74 | reg = <0 0>; /* will be filled by U-Boot */ | |
75 | }; | |
76 | ||
77 | clocks { | |
78 | mclk: mclk { | |
79 | compatible = "fixed-clock"; | |
80 | #clock-cells = <0>; | |
81 | clock-frequency = <26000000>; | |
82 | }; | |
83 | }; | |
84 | ||
85 | backlight: backlight { | |
86 | compatible = "pwm-backlight"; | |
87 | pinctrl-names = "default"; | |
88 | pinctrl-0 = <&pinctrl_lcd_rst>; | |
89 | enable-gpios = <&gpio3 4 GPIO_ACTIVE_HIGH>; | |
90 | pwms = <&pwm5 0 500000 PWM_POLARITY_INVERTED>; | |
91 | power-supply = <®_lcd_pwr>; | |
92 | /* | |
93 | * a poor man's way to create a 1:1 relationship between | |
94 | * the PWM value and the actual duty cycle | |
95 | */ | |
96 | brightness-levels = < 0 1 2 3 4 5 6 7 8 9 | |
97 | 10 11 12 13 14 15 16 17 18 19 | |
98 | 20 21 22 23 24 25 26 27 28 29 | |
99 | 30 31 32 33 34 35 36 37 38 39 | |
100 | 40 41 42 43 44 45 46 47 48 49 | |
101 | 50 51 52 53 54 55 56 57 58 59 | |
102 | 60 61 62 63 64 65 66 67 68 69 | |
103 | 70 71 72 73 74 75 76 77 78 79 | |
104 | 80 81 82 83 84 85 86 87 88 89 | |
105 | 90 91 92 93 94 95 96 97 98 99 | |
106 | 100>; | |
107 | default-brightness-level = <50>; | |
108 | }; | |
109 | ||
110 | i2c_gpio: i2c-gpio { | |
111 | compatible = "i2c-gpio"; | |
112 | #address-cells = <1>; | |
113 | #size-cells = <0>; | |
114 | pinctrl-names = "default"; | |
115 | pinctrl-0 = <&pinctrl_i2c_gpio>; | |
116 | gpios = < | |
117 | &gpio5 1 GPIO_ACTIVE_HIGH /* SDA */ | |
118 | &gpio5 0 GPIO_ACTIVE_HIGH /* SCL */ | |
119 | >; | |
120 | clock-frequency = <400000>; | |
121 | status = "okay"; | |
122 | ||
123 | ds1339: rtc@68 { | |
124 | compatible = "dallas,ds1339"; | |
125 | reg = <0x68>; | |
126 | status = "disabled"; | |
127 | }; | |
128 | }; | |
129 | ||
130 | leds { | |
131 | compatible = "gpio-leds"; | |
132 | ||
133 | user_led: user { | |
134 | label = "Heartbeat"; | |
135 | pinctrl-names = "default"; | |
136 | pinctrl-0 = <&pinctrl_led>; | |
137 | gpios = <&gpio5 9 GPIO_ACTIVE_HIGH>; | |
138 | linux,default-trigger = "heartbeat"; | |
139 | }; | |
140 | }; | |
141 | ||
142 | reg_3v3_etn: regulator-3v3etn { | |
143 | compatible = "regulator-fixed"; | |
144 | regulator-name = "3V3_ETN"; | |
145 | regulator-min-microvolt = <3300000>; | |
146 | regulator-max-microvolt = <3300000>; | |
147 | pinctrl-names = "default"; | |
148 | pinctrl-0 = <&pinctrl_etnphy_power>; | |
149 | gpio = <&gpio5 7 GPIO_ACTIVE_HIGH>; | |
150 | enable-active-high; | |
151 | }; | |
152 | ||
153 | reg_2v5: regulator-2v5 { | |
154 | compatible = "regulator-fixed"; | |
155 | regulator-name = "2V5"; | |
156 | regulator-min-microvolt = <2500000>; | |
157 | regulator-max-microvolt = <2500000>; | |
158 | regulator-always-on; | |
159 | }; | |
160 | ||
161 | reg_3v3: regulator-3v3 { | |
162 | compatible = "regulator-fixed"; | |
163 | regulator-name = "3V3"; | |
164 | regulator-min-microvolt = <3300000>; | |
165 | regulator-max-microvolt = <3300000>; | |
166 | regulator-always-on; | |
167 | }; | |
168 | ||
169 | reg_can_xcvr: regulator-canxcvr { | |
170 | compatible = "regulator-fixed"; | |
171 | regulator-name = "CAN XCVR"; | |
172 | regulator-min-microvolt = <3300000>; | |
173 | regulator-max-microvolt = <3300000>; | |
174 | pinctrl-names = "default"; | |
175 | pinctrl-0 = <&pinctrl_flexcan_xcvr>; | |
8b7be72b | 176 | gpio = <&gpio3 5 GPIO_ACTIVE_LOW>; |
5434c913 LW |
177 | }; |
178 | ||
179 | reg_lcd_pwr: regulator-lcdpwr { | |
180 | compatible = "regulator-fixed"; | |
181 | regulator-name = "LCD POWER"; | |
182 | regulator-min-microvolt = <3300000>; | |
183 | regulator-max-microvolt = <3300000>; | |
184 | pinctrl-names = "default"; | |
185 | pinctrl-0 = <&pinctrl_lcd_pwr>; | |
186 | gpio = <&gpio5 4 GPIO_ACTIVE_HIGH>; | |
187 | enable-active-high; | |
188 | regulator-boot-on; | |
189 | regulator-always-on; | |
190 | }; | |
191 | ||
192 | reg_usbh1_vbus: regulator-usbh1vbus { | |
193 | compatible = "regulator-fixed"; | |
194 | regulator-name = "usbh1_vbus"; | |
195 | regulator-min-microvolt = <5000000>; | |
196 | regulator-max-microvolt = <5000000>; | |
197 | pinctrl-names = "default"; | |
198 | pinctrl-0 = <&pinctrl_usbh1_vbus &pinctrl_usbh1_oc>; | |
199 | gpio = <&gpio1 2 GPIO_ACTIVE_HIGH>; | |
200 | enable-active-high; | |
201 | }; | |
202 | ||
203 | reg_usbotg_vbus: regulator-usbotgvbus { | |
204 | compatible = "regulator-fixed"; | |
205 | regulator-name = "usbotg_vbus"; | |
206 | regulator-min-microvolt = <5000000>; | |
207 | regulator-max-microvolt = <5000000>; | |
208 | pinctrl-names = "default"; | |
209 | pinctrl-0 = <&pinctrl_usbotg_vbus &pinctrl_usbotg_oc>; | |
210 | gpio = <&gpio1 26 GPIO_ACTIVE_HIGH>; | |
211 | enable-active-high; | |
212 | }; | |
213 | ||
214 | spi_gpio: spi-gpio { | |
215 | #address-cells = <1>; | |
216 | #size-cells = <0>; | |
217 | compatible = "spi-gpio"; | |
218 | pinctrl-names = "default"; | |
219 | pinctrl-0 = <&pinctrl_spi_gpio>; | |
220 | gpio-mosi = <&gpio1 30 GPIO_ACTIVE_HIGH>; | |
221 | gpio-miso = <&gpio1 31 GPIO_ACTIVE_HIGH>; | |
222 | gpio-sck = <&gpio1 28 GPIO_ACTIVE_HIGH>; | |
223 | num-chipselects = <2>; | |
224 | cs-gpios = < | |
225 | &gpio1 29 GPIO_ACTIVE_HIGH | |
226 | &gpio1 10 GPIO_ACTIVE_HIGH | |
227 | >; | |
228 | status = "disabled"; | |
229 | ||
230 | spi@0 { | |
231 | compatible = "spidev"; | |
232 | reg = <0>; | |
233 | spi-max-frequency = <660000>; | |
234 | }; | |
235 | ||
236 | spi@1 { | |
237 | compatible = "spidev"; | |
238 | reg = <1>; | |
239 | spi-max-frequency = <660000>; | |
240 | }; | |
241 | }; | |
242 | ||
243 | sound { | |
244 | compatible = "karo,imx6ul-tx6ul-sgtl5000", | |
245 | "simple-audio-card"; | |
246 | simple-audio-card,name = "imx6ul-tx6ul-sgtl5000-audio"; | |
247 | simple-audio-card,format = "i2s"; | |
248 | simple-audio-card,bitclock-master = <&codec_dai>; | |
249 | simple-audio-card,frame-master = <&codec_dai>; | |
250 | simple-audio-card,widgets = | |
251 | "Microphone", "Mic Jack", | |
252 | "Line", "Line In", | |
253 | "Line", "Line Out", | |
254 | "Headphone", "Headphone Jack"; | |
255 | simple-audio-card,routing = | |
256 | "MIC_IN", "Mic Jack", | |
257 | "Mic Jack", "Mic Bias", | |
258 | "Headphone Jack", "HP_OUT"; | |
259 | ||
260 | cpu_dai: simple-audio-card,cpu { | |
261 | sound-dai = <&sai2>; | |
262 | }; | |
263 | ||
264 | codec_dai: simple-audio-card,codec { | |
265 | sound-dai = <&sgtl5000>; | |
266 | }; | |
267 | }; | |
268 | }; | |
269 | ||
270 | &can1 { | |
271 | pinctrl-names = "default"; | |
272 | pinctrl-0 = <&pinctrl_flexcan1>; | |
273 | xceiver-supply = <®_can_xcvr>; | |
274 | status = "okay"; | |
275 | }; | |
276 | ||
277 | &can2 { | |
278 | pinctrl-names = "default"; | |
279 | pinctrl-0 = <&pinctrl_flexcan2>; | |
280 | xceiver-supply = <®_can_xcvr>; | |
281 | status = "okay"; | |
282 | }; | |
283 | ||
284 | &ecspi2 { | |
285 | pinctrl-names = "default"; | |
286 | pinctrl-0 = <&pinctrl_ecspi2>; | |
5434c913 LW |
287 | cs-gpios = < |
288 | &gpio1 29 GPIO_ACTIVE_HIGH | |
289 | &gpio1 10 GPIO_ACTIVE_HIGH | |
290 | >; | |
291 | status = "disabled"; | |
292 | ||
293 | spidev0: spi@0 { | |
294 | compatible = "spidev"; | |
295 | reg = <0>; | |
296 | spi-max-frequency = <60000000>; | |
297 | }; | |
298 | ||
299 | spidev1: spi@1 { | |
300 | compatible = "spidev"; | |
301 | reg = <1>; | |
302 | spi-max-frequency = <60000000>; | |
303 | }; | |
304 | }; | |
305 | ||
306 | &fec1 { | |
307 | pinctrl-names = "default"; | |
308 | pinctrl-0 = <&pinctrl_enet1 &pinctrl_enet1_mdio &pinctrl_etnphy0_rst>; | |
309 | phy-mode = "rmii"; | |
12de44f5 | 310 | phy-reset-gpios = <&gpio5 6 GPIO_ACTIVE_LOW>; |
5434c913 LW |
311 | phy-supply = <®_3v3_etn>; |
312 | phy-handle = <&etnphy0>; | |
313 | status = "okay"; | |
314 | ||
315 | mdio { | |
316 | #address-cells = <1>; | |
317 | #size-cells = <0>; | |
318 | ||
319 | etnphy0: ethernet-phy@0 { | |
320 | compatible = "ethernet-phy-ieee802.3-c22"; | |
321 | reg = <0>; | |
322 | pinctrl-names = "default"; | |
323 | pinctrl-0 = <&pinctrl_etnphy0_int>; | |
324 | interrupt-parent = <&gpio5>; | |
325 | interrupts = <5 IRQ_TYPE_EDGE_FALLING>; | |
326 | status = "okay"; | |
327 | }; | |
328 | ||
329 | etnphy1: ethernet-phy@2 { | |
330 | compatible = "ethernet-phy-ieee802.3-c22"; | |
331 | reg = <2>; | |
332 | pinctrl-names = "default"; | |
333 | pinctrl-0 = <&pinctrl_etnphy1_int>; | |
334 | interrupt-parent = <&gpio4>; | |
335 | interrupts = <27 IRQ_TYPE_EDGE_FALLING>; | |
336 | status = "okay"; | |
337 | }; | |
338 | }; | |
339 | }; | |
340 | ||
341 | &fec2 { | |
342 | pinctrl-names = "default"; | |
343 | pinctrl-0 = <&pinctrl_enet2 &pinctrl_etnphy1_rst>; | |
344 | phy-mode = "rmii"; | |
12de44f5 | 345 | phy-reset-gpios = <&gpio4 28 GPIO_ACTIVE_LOW>; |
5434c913 LW |
346 | phy-supply = <®_3v3_etn>; |
347 | phy-handle = <&etnphy1>; | |
348 | status = "disabled"; | |
349 | }; | |
350 | ||
351 | &gpmi { | |
352 | pinctrl-names = "default"; | |
353 | pinctrl-0 = <&pinctrl_gpmi_nand>; | |
354 | nand-on-flash-bbt; | |
355 | fsl,no-blockmark-swap; | |
356 | status = "okay"; | |
357 | }; | |
358 | ||
359 | &i2c2 { | |
360 | pinctrl-names = "default"; | |
361 | pinctrl-0 = <&pinctrl_i2c2>; | |
362 | clock-frequency = <400000>; | |
363 | status = "okay"; | |
364 | ||
365 | sgtl5000: codec@0a { | |
366 | compatible = "fsl,sgtl5000"; | |
367 | reg = <0x0a>; | |
368 | #sound-dai-cells = <0>; | |
369 | VDDA-supply = <®_2v5>; | |
370 | VDDIO-supply = <®_3v3>; | |
371 | clocks = <&mclk>; | |
372 | }; | |
373 | ||
374 | polytouch: polytouch@38 { | |
375 | compatible = "edt,edt-ft5x06"; | |
376 | reg = <0x38>; | |
377 | pinctrl-names = "default"; | |
378 | pinctrl-0 = <&pinctrl_edt_ft5x06>; | |
379 | interrupt-parent = <&gpio5>; | |
380 | interrupts = <2 IRQ_TYPE_EDGE_FALLING>; | |
381 | reset-gpios = <&gpio5 3 GPIO_ACTIVE_LOW>; | |
382 | wake-gpios = <&gpio5 8 GPIO_ACTIVE_HIGH>; | |
383 | wakeup-source; | |
384 | }; | |
385 | ||
386 | touchscreen: touchscreen@48 { | |
387 | compatible = "ti,tsc2007"; | |
388 | reg = <0x48>; | |
389 | pinctrl-names = "default"; | |
390 | pinctrl-0 = <&pinctrl_tsc2007>; | |
391 | interrupt-parent = <&gpio3>; | |
392 | interrupts = <26 IRQ_TYPE_NONE>; | |
393 | gpios = <&gpio3 26 GPIO_ACTIVE_LOW>; | |
394 | ti,x-plate-ohms = <660>; | |
395 | wakeup-source; | |
396 | }; | |
397 | }; | |
398 | ||
399 | &kpp { | |
400 | pinctrl-names = "default"; | |
401 | pinctrl-0 = <&pinctrl_kpp>; | |
402 | /* sample keymap */ | |
403 | /* row/col 0..3 are mapped to KPP row/col 4..7 */ | |
404 | linux,keymap = < | |
405 | MATRIX_KEY(4, 4, KEY_POWER) | |
406 | MATRIX_KEY(4, 5, KEY_KP0) | |
407 | MATRIX_KEY(4, 6, KEY_KP1) | |
408 | MATRIX_KEY(4, 7, KEY_KP2) | |
409 | MATRIX_KEY(5, 4, KEY_KP3) | |
410 | MATRIX_KEY(5, 5, KEY_KP4) | |
411 | MATRIX_KEY(5, 6, KEY_KP5) | |
412 | MATRIX_KEY(5, 7, KEY_KP6) | |
413 | MATRIX_KEY(6, 4, KEY_KP7) | |
414 | MATRIX_KEY(6, 5, KEY_KP8) | |
415 | MATRIX_KEY(6, 6, KEY_KP9) | |
416 | >; | |
417 | status = "okay"; | |
418 | }; | |
419 | ||
420 | &lcdif { | |
421 | pinctrl-names = "default"; | |
422 | pinctrl-0 = <&pinctrl_disp0_1>; | |
423 | lcd-supply = <®_lcd_pwr>; | |
424 | display = <&display>; | |
425 | status = "okay"; | |
426 | ||
427 | display: display@di0 { | |
428 | bits-per-pixel = <32>; | |
429 | bus-width = <24>; | |
430 | status = "okay"; | |
431 | ||
432 | display-timings { | |
433 | VGA { | |
434 | clock-frequency = <25200000>; | |
435 | hactive = <640>; | |
436 | vactive = <480>; | |
437 | hback-porch = <48>; | |
438 | hsync-len = <96>; | |
439 | hfront-porch = <16>; | |
440 | vback-porch = <31>; | |
441 | vsync-len = <2>; | |
442 | vfront-porch = <12>; | |
443 | hsync-active = <0>; | |
444 | vsync-active = <0>; | |
445 | de-active = <1>; | |
446 | pixelclk-active = <1>; | |
447 | }; | |
448 | ||
449 | ETV570 { | |
450 | clock-frequency = <25200000>; | |
451 | hactive = <640>; | |
452 | vactive = <480>; | |
453 | hback-porch = <114>; | |
454 | hsync-len = <30>; | |
455 | hfront-porch = <16>; | |
456 | vback-porch = <32>; | |
457 | vsync-len = <3>; | |
458 | vfront-porch = <10>; | |
459 | hsync-active = <0>; | |
460 | vsync-active = <0>; | |
461 | de-active = <1>; | |
462 | pixelclk-active = <1>; | |
463 | }; | |
464 | ||
465 | ET0350 { | |
466 | clock-frequency = <6413760>; | |
467 | hactive = <320>; | |
468 | vactive = <240>; | |
469 | hback-porch = <34>; | |
470 | hsync-len = <34>; | |
471 | hfront-porch = <20>; | |
472 | vback-porch = <15>; | |
473 | vsync-len = <3>; | |
474 | vfront-porch = <4>; | |
475 | hsync-active = <0>; | |
476 | vsync-active = <0>; | |
477 | de-active = <1>; | |
478 | pixelclk-active = <1>; | |
479 | }; | |
480 | ||
481 | ET0430 { | |
482 | clock-frequency = <9009000>; | |
483 | hactive = <480>; | |
484 | vactive = <272>; | |
485 | hback-porch = <2>; | |
486 | hsync-len = <41>; | |
487 | hfront-porch = <2>; | |
488 | vback-porch = <2>; | |
489 | vsync-len = <10>; | |
490 | vfront-porch = <2>; | |
491 | hsync-active = <0>; | |
492 | vsync-active = <0>; | |
493 | de-active = <1>; | |
494 | pixelclk-active = <0>; | |
495 | }; | |
496 | ||
497 | ET0500 { | |
498 | clock-frequency = <33264000>; | |
499 | hactive = <800>; | |
500 | vactive = <480>; | |
501 | hback-porch = <88>; | |
502 | hsync-len = <128>; | |
503 | hfront-porch = <40>; | |
504 | vback-porch = <33>; | |
505 | vsync-len = <2>; | |
506 | vfront-porch = <10>; | |
507 | hsync-active = <0>; | |
508 | vsync-active = <0>; | |
509 | de-active = <1>; | |
510 | pixelclk-active = <1>; | |
511 | }; | |
512 | ||
513 | ET0700 { /* same as ET0500 */ | |
514 | clock-frequency = <33264000>; | |
515 | hactive = <800>; | |
516 | vactive = <480>; | |
517 | hback-porch = <88>; | |
518 | hsync-len = <128>; | |
519 | hfront-porch = <40>; | |
520 | vback-porch = <33>; | |
521 | vsync-len = <2>; | |
522 | vfront-porch = <10>; | |
523 | hsync-active = <0>; | |
524 | vsync-active = <0>; | |
525 | de-active = <1>; | |
526 | pixelclk-active = <1>; | |
527 | }; | |
528 | ||
529 | ETQ570 { | |
530 | clock-frequency = <6596040>; | |
531 | hactive = <320>; | |
532 | vactive = <240>; | |
533 | hback-porch = <38>; | |
534 | hsync-len = <30>; | |
535 | hfront-porch = <30>; | |
536 | vback-porch = <16>; | |
537 | vsync-len = <3>; | |
538 | vfront-porch = <4>; | |
539 | hsync-active = <0>; | |
540 | vsync-active = <0>; | |
541 | de-active = <1>; | |
542 | pixelclk-active = <1>; | |
543 | }; | |
544 | }; | |
545 | }; | |
546 | }; | |
547 | ||
548 | &pwm5 { | |
549 | pinctrl-names = "default"; | |
550 | pinctrl-0 = <&pinctrl_pwm5>; | |
551 | #pwm-cells = <3>; | |
552 | status = "okay"; | |
553 | }; | |
554 | ||
555 | &sai2 { | |
556 | pinctrl-names = "default"; | |
557 | pinctrl-0 = <&pinctrl_sai2>; | |
558 | status = "okay"; | |
559 | }; | |
560 | ||
561 | &uart1 { | |
562 | pinctrl-names = "default"; | |
563 | pinctrl-0 = <&pinctrl_uart1 &pinctrl_uart1_rtscts>; | |
2e7c416c | 564 | uart-has-rtscts; |
5434c913 LW |
565 | status = "okay"; |
566 | }; | |
567 | ||
568 | &uart2 { | |
569 | pinctrl-names = "default"; | |
570 | pinctrl-0 = <&pinctrl_uart2 &pinctrl_uart2_rtscts>; | |
2e7c416c | 571 | uart-has-rtscts; |
5434c913 LW |
572 | status = "okay"; |
573 | }; | |
574 | ||
575 | &uart5 { | |
576 | pinctrl-names = "default"; | |
577 | pinctrl-0 = <&pinctrl_uart5 &pinctrl_uart5_rtscts>; | |
2e7c416c | 578 | uart-has-rtscts; |
5434c913 LW |
579 | status = "okay"; |
580 | }; | |
581 | ||
582 | &usbotg1 { | |
583 | vbus-supply = <®_usbotg_vbus>; | |
584 | dr_mode = "peripheral"; | |
585 | disable-over-current; | |
586 | status = "okay"; | |
587 | }; | |
588 | ||
589 | &usbotg2 { | |
590 | vbus-supply = <®_usbh1_vbus>; | |
591 | dr_mode = "host"; | |
592 | disable-over-current; | |
593 | status = "okay"; | |
594 | }; | |
595 | ||
596 | &usdhc1 { | |
597 | pinctrl-names = "default"; | |
598 | pinctrl-0 = <&pinctrl_usdhc1 &pinctrl_usdhc1_cd>; | |
599 | bus-width = <4>; | |
600 | no-1-8-v; | |
601 | cd-gpios = <&gpio4 14 GPIO_ACTIVE_LOW>; | |
602 | fsl,wp-controller; | |
603 | status = "okay"; | |
604 | }; | |
605 | ||
606 | &iomuxc { | |
607 | pinctrl-names = "default"; | |
608 | pinctrl-0 = <&pinctrl_hog>; | |
609 | ||
610 | pinctrl_hog: hoggrp { | |
611 | }; | |
612 | ||
613 | pinctrl_led: ledgrp { | |
614 | fsl,pins = < | |
615 | MX6UL_PAD_SNVS_TAMPER9__GPIO5_IO09 0x0b0b0 /* LED */ | |
616 | >; | |
617 | }; | |
618 | ||
619 | pinctrl_disp0_1: disp0grp-1 { | |
620 | fsl,pins = < | |
621 | MX6UL_PAD_LCD_CLK__LCDIF_CLK 0x10 /* LSCLK */ | |
622 | MX6UL_PAD_LCD_ENABLE__LCDIF_ENABLE 0x10 /* OE_ACD */ | |
623 | MX6UL_PAD_LCD_HSYNC__LCDIF_HSYNC 0x10 /* HSYNC */ | |
624 | MX6UL_PAD_LCD_VSYNC__LCDIF_VSYNC 0x10 /* VSYNC */ | |
625 | /* PAD DISP0_DAT0 is used for the Flexcan transceiver control on STK5-v5 */ | |
626 | MX6UL_PAD_LCD_DATA01__LCDIF_DATA01 0x10 | |
627 | MX6UL_PAD_LCD_DATA02__LCDIF_DATA02 0x10 | |
628 | MX6UL_PAD_LCD_DATA03__LCDIF_DATA03 0x10 | |
629 | MX6UL_PAD_LCD_DATA04__LCDIF_DATA04 0x10 | |
630 | MX6UL_PAD_LCD_DATA05__LCDIF_DATA05 0x10 | |
631 | MX6UL_PAD_LCD_DATA06__LCDIF_DATA06 0x10 | |
632 | MX6UL_PAD_LCD_DATA07__LCDIF_DATA07 0x10 | |
633 | MX6UL_PAD_LCD_DATA08__LCDIF_DATA08 0x10 | |
634 | MX6UL_PAD_LCD_DATA09__LCDIF_DATA09 0x10 | |
635 | MX6UL_PAD_LCD_DATA10__LCDIF_DATA10 0x10 | |
636 | MX6UL_PAD_LCD_DATA11__LCDIF_DATA11 0x10 | |
637 | MX6UL_PAD_LCD_DATA12__LCDIF_DATA12 0x10 | |
638 | MX6UL_PAD_LCD_DATA13__LCDIF_DATA13 0x10 | |
639 | MX6UL_PAD_LCD_DATA14__LCDIF_DATA14 0x10 | |
640 | MX6UL_PAD_LCD_DATA15__LCDIF_DATA15 0x10 | |
641 | MX6UL_PAD_LCD_DATA16__LCDIF_DATA16 0x10 | |
642 | MX6UL_PAD_LCD_DATA17__LCDIF_DATA17 0x10 | |
643 | MX6UL_PAD_LCD_DATA18__LCDIF_DATA18 0x10 | |
644 | MX6UL_PAD_LCD_DATA19__LCDIF_DATA19 0x10 | |
645 | MX6UL_PAD_LCD_DATA20__LCDIF_DATA20 0x10 | |
646 | MX6UL_PAD_LCD_DATA21__LCDIF_DATA21 0x10 | |
647 | MX6UL_PAD_LCD_DATA22__LCDIF_DATA22 0x10 | |
648 | MX6UL_PAD_LCD_DATA23__LCDIF_DATA23 0x10 | |
649 | >; | |
650 | }; | |
651 | ||
652 | pinctrl_disp0_2: disp0grp-2 { | |
653 | fsl,pins = < | |
654 | MX6UL_PAD_LCD_CLK__LCDIF_CLK 0x10 /* LSCLK */ | |
655 | MX6UL_PAD_LCD_ENABLE__LCDIF_ENABLE 0x10 /* OE_ACD */ | |
656 | MX6UL_PAD_LCD_HSYNC__LCDIF_HSYNC 0x10 /* HSYNC */ | |
657 | MX6UL_PAD_LCD_VSYNC__LCDIF_VSYNC 0x10 /* VSYNC */ | |
658 | MX6UL_PAD_LCD_DATA00__LCDIF_DATA00 0x10 | |
659 | MX6UL_PAD_LCD_DATA01__LCDIF_DATA01 0x10 | |
660 | MX6UL_PAD_LCD_DATA02__LCDIF_DATA02 0x10 | |
661 | MX6UL_PAD_LCD_DATA03__LCDIF_DATA03 0x10 | |
662 | MX6UL_PAD_LCD_DATA04__LCDIF_DATA04 0x10 | |
663 | MX6UL_PAD_LCD_DATA05__LCDIF_DATA05 0x10 | |
664 | MX6UL_PAD_LCD_DATA06__LCDIF_DATA06 0x10 | |
665 | MX6UL_PAD_LCD_DATA07__LCDIF_DATA07 0x10 | |
666 | MX6UL_PAD_LCD_DATA08__LCDIF_DATA08 0x10 | |
667 | MX6UL_PAD_LCD_DATA09__LCDIF_DATA09 0x10 | |
668 | MX6UL_PAD_LCD_DATA10__LCDIF_DATA10 0x10 | |
669 | MX6UL_PAD_LCD_DATA11__LCDIF_DATA11 0x10 | |
670 | MX6UL_PAD_LCD_DATA12__LCDIF_DATA12 0x10 | |
671 | MX6UL_PAD_LCD_DATA13__LCDIF_DATA13 0x10 | |
672 | MX6UL_PAD_LCD_DATA14__LCDIF_DATA14 0x10 | |
673 | MX6UL_PAD_LCD_DATA15__LCDIF_DATA15 0x10 | |
674 | MX6UL_PAD_LCD_DATA16__LCDIF_DATA16 0x10 | |
675 | MX6UL_PAD_LCD_DATA17__LCDIF_DATA17 0x10 | |
676 | MX6UL_PAD_LCD_DATA18__LCDIF_DATA18 0x10 | |
677 | MX6UL_PAD_LCD_DATA19__LCDIF_DATA19 0x10 | |
678 | MX6UL_PAD_LCD_DATA20__LCDIF_DATA20 0x10 | |
679 | MX6UL_PAD_LCD_DATA21__LCDIF_DATA21 0x10 | |
680 | MX6UL_PAD_LCD_DATA22__LCDIF_DATA22 0x10 | |
681 | MX6UL_PAD_LCD_DATA23__LCDIF_DATA23 0x10 | |
682 | >; | |
683 | }; | |
684 | ||
685 | pinctrl_ecspi2: ecspi2grp { | |
686 | fsl,pins = < | |
687 | MX6UL_PAD_UART4_RX_DATA__GPIO1_IO29 0x0b0b0 /* CSPI_SS */ | |
688 | MX6UL_PAD_JTAG_MOD__GPIO1_IO10 0x0b0b0 /* CSPI_SS */ | |
689 | MX6UL_PAD_UART5_TX_DATA__ECSPI2_MOSI 0x0b0b0 /* CSPI_MOSI */ | |
690 | MX6UL_PAD_UART5_RX_DATA__ECSPI2_MISO 0x0b0b0 /* CSPI_MISO */ | |
691 | MX6UL_PAD_UART4_TX_DATA__ECSPI2_SCLK 0x0b0b0 /* CSPI_SCLK */ | |
692 | >; | |
693 | }; | |
694 | ||
695 | pinctrl_edt_ft5x06: edt-ft5x06grp { | |
696 | fsl,pins = < | |
697 | MX6UL_PAD_SNVS_TAMPER2__GPIO5_IO02 0x1b0b0 /* Interrupt */ | |
698 | MX6UL_PAD_SNVS_TAMPER3__GPIO5_IO03 0x1b0b0 /* Reset */ | |
699 | MX6UL_PAD_SNVS_TAMPER8__GPIO5_IO08 0x1b0b0 /* Wake */ | |
700 | >; | |
701 | }; | |
702 | ||
703 | pinctrl_enet1: enet1grp { | |
704 | fsl,pins = < | |
705 | MX6UL_PAD_ENET1_RX_DATA0__ENET1_RDATA00 0x000b0 | |
706 | MX6UL_PAD_ENET1_RX_DATA1__ENET1_RDATA01 0x000b0 | |
707 | MX6UL_PAD_ENET1_RX_EN__ENET1_RX_EN 0x000b0 | |
708 | MX6UL_PAD_ENET1_RX_ER__ENET1_RX_ER 0x000b0 | |
709 | MX6UL_PAD_ENET1_TX_EN__ENET1_TX_EN 0x000b0 | |
710 | MX6UL_PAD_ENET1_TX_DATA0__ENET1_TDATA00 0x000b0 | |
711 | MX6UL_PAD_ENET1_TX_DATA1__ENET1_TDATA01 0x000b0 | |
712 | MX6UL_PAD_ENET1_TX_CLK__ENET1_REF_CLK1 0x400000b1 | |
713 | >; | |
714 | }; | |
715 | ||
716 | pinctrl_enet2: enet2grp { | |
717 | fsl,pins = < | |
718 | MX6UL_PAD_ENET2_RX_DATA0__ENET2_RDATA00 0x000b0 | |
719 | MX6UL_PAD_ENET2_RX_DATA1__ENET2_RDATA01 0x000b0 | |
720 | MX6UL_PAD_ENET2_RX_EN__ENET2_RX_EN 0x000b0 | |
721 | MX6UL_PAD_ENET2_RX_ER__ENET2_RX_ER 0x000b0 | |
722 | MX6UL_PAD_ENET2_TX_EN__ENET2_TX_EN 0x000b0 | |
723 | MX6UL_PAD_ENET2_TX_DATA0__ENET2_TDATA00 0x000b0 | |
724 | MX6UL_PAD_ENET2_TX_DATA1__ENET2_TDATA01 0x000b0 | |
725 | MX6UL_PAD_ENET2_TX_CLK__ENET2_REF_CLK2 0x400000b1 | |
726 | >; | |
727 | }; | |
728 | ||
729 | pinctrl_enet1_mdio: enet1-mdiogrp { | |
730 | fsl,pins = < | |
731 | MX6UL_PAD_GPIO1_IO07__ENET1_MDC 0x0b0b0 | |
732 | MX6UL_PAD_GPIO1_IO06__ENET1_MDIO 0x1b0b0 | |
733 | >; | |
734 | }; | |
735 | ||
736 | pinctrl_etnphy_power: etnphy-pwrgrp { | |
737 | fsl,pins = < | |
738 | MX6UL_PAD_SNVS_TAMPER7__GPIO5_IO07 0x0b0b0 /* ETN PHY POWER */ | |
739 | >; | |
740 | }; | |
741 | ||
742 | pinctrl_etnphy0_int: etnphy-intgrp-0 { | |
743 | fsl,pins = < | |
744 | MX6UL_PAD_SNVS_TAMPER5__GPIO5_IO05 0x0b0b0 /* ETN PHY INT */ | |
745 | >; | |
746 | }; | |
747 | ||
748 | pinctrl_etnphy0_rst: etnphy-rstgrp-0 { | |
749 | fsl,pins = < | |
750 | MX6UL_PAD_SNVS_TAMPER6__GPIO5_IO06 0x0b0b0 /* ETN PHY RESET */ | |
751 | >; | |
752 | }; | |
753 | ||
754 | pinctrl_etnphy1_int: etnphy-intgrp-1 { | |
755 | fsl,pins = < | |
756 | MX6UL_PAD_CSI_DATA06__GPIO4_IO27 0x0b0b0 /* ETN PHY INT */ | |
757 | >; | |
758 | }; | |
759 | ||
760 | pinctrl_etnphy1_rst: etnphy-rstgrp-1 { | |
761 | fsl,pins = < | |
762 | MX6UL_PAD_CSI_DATA07__GPIO4_IO28 0x0b0b0 /* ETN PHY RESET */ | |
763 | >; | |
764 | }; | |
765 | ||
766 | pinctrl_flexcan1: flexcan1grp { | |
767 | fsl,pins = < | |
768 | MX6UL_PAD_UART3_CTS_B__FLEXCAN1_TX 0x0b0b0 | |
769 | MX6UL_PAD_UART3_RTS_B__FLEXCAN1_RX 0x0b0b0 | |
770 | >; | |
771 | }; | |
772 | ||
773 | pinctrl_flexcan2: flexcan2grp { | |
774 | fsl,pins = < | |
775 | MX6UL_PAD_UART2_CTS_B__FLEXCAN2_TX 0x0b0b0 | |
776 | MX6UL_PAD_UART2_RTS_B__FLEXCAN2_RX 0x0b0b0 | |
777 | >; | |
778 | }; | |
779 | ||
780 | pinctrl_flexcan_xcvr: flexcan-xcvrgrp { | |
781 | fsl,pins = < | |
782 | MX6UL_PAD_LCD_DATA00__GPIO3_IO05 0x0b0b0 /* Flexcan XCVR enable */ | |
783 | >; | |
784 | }; | |
785 | ||
786 | pinctrl_gpmi_nand: gpminandgrp { | |
787 | fsl,pins = < | |
788 | MX6UL_PAD_NAND_CLE__RAWNAND_CLE 0x0b0b1 | |
789 | MX6UL_PAD_NAND_ALE__RAWNAND_ALE 0x0b0b1 | |
790 | MX6UL_PAD_NAND_WP_B__RAWNAND_WP_B 0x0b0b1 | |
791 | MX6UL_PAD_NAND_READY_B__RAWNAND_READY_B 0x0b000 | |
792 | MX6UL_PAD_NAND_CE0_B__RAWNAND_CE0_B 0x0b0b1 | |
793 | MX6UL_PAD_NAND_RE_B__RAWNAND_RE_B 0x0b0b1 | |
794 | MX6UL_PAD_NAND_WE_B__RAWNAND_WE_B 0x0b0b1 | |
795 | MX6UL_PAD_NAND_DATA00__RAWNAND_DATA00 0x0b0b1 | |
796 | MX6UL_PAD_NAND_DATA01__RAWNAND_DATA01 0x0b0b1 | |
797 | MX6UL_PAD_NAND_DATA02__RAWNAND_DATA02 0x0b0b1 | |
798 | MX6UL_PAD_NAND_DATA03__RAWNAND_DATA03 0x0b0b1 | |
799 | MX6UL_PAD_NAND_DATA04__RAWNAND_DATA04 0x0b0b1 | |
800 | MX6UL_PAD_NAND_DATA05__RAWNAND_DATA05 0x0b0b1 | |
801 | MX6UL_PAD_NAND_DATA06__RAWNAND_DATA06 0x0b0b1 | |
802 | MX6UL_PAD_NAND_DATA07__RAWNAND_DATA07 0x0b0b1 | |
803 | >; | |
804 | }; | |
805 | ||
806 | pinctrl_i2c_gpio: i2c-gpiogrp { | |
807 | fsl,pins = < | |
808 | MX6UL_PAD_SNVS_TAMPER0__GPIO5_IO00 0x4001b8b1 /* I2C SCL */ | |
809 | MX6UL_PAD_SNVS_TAMPER1__GPIO5_IO01 0x4001b8b1 /* I2C SDA */ | |
810 | >; | |
811 | }; | |
812 | ||
813 | pinctrl_i2c2: i2c2grp { | |
814 | fsl,pins = < | |
815 | MX6UL_PAD_GPIO1_IO00__I2C2_SCL 0x4001b8b1 | |
816 | MX6UL_PAD_GPIO1_IO01__I2C2_SDA 0x4001b8b1 | |
817 | >; | |
818 | }; | |
819 | ||
820 | pinctrl_kpp: kppgrp { | |
821 | fsl,pins = < | |
822 | MX6UL_PAD_ENET2_RX_DATA1__KPP_COL04 0x1b0b0 | |
823 | MX6UL_PAD_ENET2_TX_DATA0__KPP_COL05 0x1b0b0 | |
824 | MX6UL_PAD_ENET2_TX_EN__KPP_COL06 0x1b0b0 | |
825 | MX6UL_PAD_ENET2_RX_ER__KPP_COL07 0x1b0b0 | |
826 | MX6UL_PAD_ENET2_RX_DATA0__KPP_ROW04 0x1b0b0 | |
827 | MX6UL_PAD_ENET2_RX_EN__KPP_ROW05 0x1b0b0 | |
828 | MX6UL_PAD_ENET2_TX_DATA1__KPP_ROW06 0x1b0b0 | |
829 | MX6UL_PAD_ENET2_TX_CLK__KPP_ROW07 0x1b0b0 | |
830 | >; | |
831 | }; | |
832 | ||
833 | pinctrl_lcd_pwr: lcd-pwrgrp { | |
834 | fsl,pins = < | |
835 | MX6UL_PAD_SNVS_TAMPER4__GPIO5_IO04 0x0b0b0 /* LCD Power Enable */ | |
836 | >; | |
837 | }; | |
838 | ||
839 | pinctrl_lcd_rst: lcd-rstgrp { | |
840 | fsl,pins = < | |
841 | MX6UL_PAD_LCD_RESET__GPIO3_IO04 0x0b0b0 /* LCD Reset */ | |
842 | >; | |
843 | }; | |
844 | ||
845 | pinctrl_pwm5: pwm5grp { | |
846 | fsl,pins = < | |
847 | MX6UL_PAD_NAND_DQS__PWM5_OUT 0x0b0b0 | |
848 | >; | |
849 | }; | |
850 | ||
851 | pinctrl_sai2: sai2grp { | |
852 | fsl,pins = < | |
853 | MX6UL_PAD_JTAG_TCK__SAI2_RX_DATA 0x0b0b0 /* SSI1_RXD */ | |
854 | MX6UL_PAD_JTAG_TRST_B__SAI2_TX_DATA 0x0b0b0 /* SSI1_TXD */ | |
855 | MX6UL_PAD_JTAG_TDI__SAI2_TX_BCLK 0x0b0b0 /* SSI1_CLK */ | |
856 | MX6UL_PAD_JTAG_TDO__SAI2_TX_SYNC 0x0b0b0 /* SSI1_FS */ | |
857 | >; | |
858 | }; | |
859 | ||
860 | pinctrl_spi_gpio: spi-gpiogrp { | |
861 | fsl,pins = < | |
862 | MX6UL_PAD_UART4_RX_DATA__GPIO1_IO29 0x0b0b0 /* CSPI_SS */ | |
863 | MX6UL_PAD_JTAG_MOD__GPIO1_IO10 0x0b0b0 /* CSPI_SS */ | |
864 | MX6UL_PAD_UART5_TX_DATA__GPIO1_IO30 0x0b0b0 /* CSPI_MOSI */ | |
865 | MX6UL_PAD_UART5_RX_DATA__GPIO1_IO31 0x0b0b0 /* CSPI_MISO */ | |
866 | MX6UL_PAD_UART4_TX_DATA__GPIO1_IO28 0x0b0b0 /* CSPI_SCLK */ | |
867 | >; | |
868 | }; | |
869 | ||
870 | pinctrl_tsc2007: tsc2007grp { | |
871 | fsl,pins = < | |
872 | MX6UL_PAD_JTAG_TMS__GPIO1_IO11 0x1b0b0 /* Interrupt */ | |
873 | >; | |
874 | }; | |
875 | ||
876 | pinctrl_uart1: uart1grp { | |
877 | fsl,pins = < | |
878 | MX6UL_PAD_UART1_TX_DATA__UART1_DCE_TX 0x0b0b0 | |
879 | MX6UL_PAD_UART1_RX_DATA__UART1_DCE_RX 0x0b0b0 | |
880 | >; | |
881 | }; | |
882 | ||
883 | pinctrl_uart1_rtscts: uart1-rtsctsgrp { | |
884 | fsl,pins = < | |
885 | MX6UL_PAD_UART1_RTS_B__UART1_DCE_RTS 0x0b0b0 | |
886 | MX6UL_PAD_UART1_CTS_B__UART1_DCE_CTS 0x0b0b0 | |
887 | >; | |
888 | }; | |
889 | ||
890 | pinctrl_uart2: uart2grp { | |
891 | fsl,pins = < | |
892 | MX6UL_PAD_UART2_TX_DATA__UART2_DCE_TX 0x0b0b0 | |
893 | MX6UL_PAD_UART2_RX_DATA__UART2_DCE_RX 0x0b0b0 | |
894 | >; | |
895 | }; | |
896 | ||
897 | pinctrl_uart2_rtscts: uart2-rtsctsgrp { | |
898 | fsl,pins = < | |
899 | MX6UL_PAD_UART3_RX_DATA__UART2_DCE_RTS 0x0b0b0 | |
900 | MX6UL_PAD_UART3_TX_DATA__UART2_DCE_CTS 0x0b0b0 | |
901 | >; | |
902 | }; | |
903 | ||
904 | pinctrl_uart5: uart5grp { | |
905 | fsl,pins = < | |
906 | MX6UL_PAD_GPIO1_IO04__UART5_DCE_TX 0x0b0b0 | |
907 | MX6UL_PAD_GPIO1_IO05__UART5_DCE_RX 0x0b0b0 | |
908 | >; | |
909 | }; | |
910 | ||
911 | pinctrl_uart5_rtscts: uart5-rtsctsgrp { | |
912 | fsl,pins = < | |
913 | MX6UL_PAD_GPIO1_IO08__UART5_DCE_RTS 0x0b0b0 | |
914 | MX6UL_PAD_GPIO1_IO09__UART5_DCE_CTS 0x0b0b0 | |
915 | >; | |
916 | }; | |
917 | ||
918 | pinctrl_usbh1_oc: usbh1-ocgrp { | |
919 | fsl,pins = < | |
920 | MX6UL_PAD_GPIO1_IO03__GPIO1_IO03 0x17059 /* USBH1_OC */ | |
921 | >; | |
922 | }; | |
923 | ||
924 | pinctrl_usbh1_vbus: usbh1-vbusgrp { | |
925 | fsl,pins = < | |
926 | MX6UL_PAD_GPIO1_IO02__GPIO1_IO02 0x0b0b0 /* USBH1_VBUSEN */ | |
927 | >; | |
928 | }; | |
929 | ||
930 | pinctrl_usbotg_oc: usbotg-ocgrp { | |
931 | fsl,pins = < | |
932 | MX6UL_PAD_UART3_RTS_B__GPIO1_IO27 0x17059 /* USBOTG_OC */ | |
933 | >; | |
934 | }; | |
935 | ||
936 | pinctrl_usbotg_vbus: usbotg-vbusgrp { | |
937 | fsl,pins = < | |
938 | MX6UL_PAD_UART3_CTS_B__GPIO1_IO26 0x1b0b0 /* USBOTG_VBUSEN */ | |
939 | >; | |
940 | }; | |
941 | ||
942 | pinctrl_usdhc1: usdhc1grp { | |
943 | fsl,pins = < | |
944 | MX6UL_PAD_SD1_CMD__USDHC1_CMD 0x070b1 | |
945 | MX6UL_PAD_SD1_CLK__USDHC1_CLK 0x07099 | |
946 | MX6UL_PAD_SD1_DATA0__USDHC1_DATA0 0x070b1 | |
947 | MX6UL_PAD_SD1_DATA1__USDHC1_DATA1 0x070b1 | |
948 | MX6UL_PAD_SD1_DATA2__USDHC1_DATA2 0x070b1 | |
949 | MX6UL_PAD_SD1_DATA3__USDHC1_DATA3 0x070b1 | |
950 | >; | |
951 | }; | |
952 | ||
953 | pinctrl_usdhc1_cd: usdhc1cdgrp { | |
954 | fsl,pins = < | |
955 | MX6UL_PAD_NAND_CE1_B__GPIO4_IO14 0x170b0 /* SD1 CD */ | |
956 | >; | |
957 | }; | |
958 | ||
959 | pinctrl_usdhc2: usdhc2grp { | |
960 | fsl,pins = < | |
961 | MX6UL_PAD_NAND_WE_B__USDHC2_CMD 0x070b1 | |
962 | MX6UL_PAD_NAND_RE_B__USDHC2_CLK 0x070b1 | |
963 | MX6UL_PAD_NAND_DATA00__USDHC2_DATA0 0x070b1 | |
964 | MX6UL_PAD_NAND_DATA01__USDHC2_DATA1 0x070b1 | |
965 | MX6UL_PAD_NAND_DATA02__USDHC2_DATA2 0x070b1 | |
966 | MX6UL_PAD_NAND_DATA03__USDHC2_DATA3 0x070b1 | |
967 | /* eMMC RESET */ | |
968 | MX6UL_PAD_NAND_ALE__USDHC2_RESET_B 0x170b0 | |
969 | >; | |
970 | }; | |
971 | }; |