[linux-2.6-block.git] / arch / arm / boot / dts / imx6ul-geam.dts

/*
 * Copyright (C) 2016 Amarula Solutions B.V.
 * Copyright (C) 2016 Engicam S.r.l.
 *
 * This file is dual-licensed: you can use it either under the terms
 * of the GPL or the X11 license, at your option. Note that this dual
 * licensing only applies to this file, and not this project as a
 * whole.
 *
 *  a) This file is free software; you can redistribute it and/or
 *     modify it under the terms of the GNU General Public License
 *     version 2 as published by the Free Software Foundation.
 *
 *     This file is distributed in the hope that it will be useful,
 *     but WITHOUT ANY WARRANTY; without even the implied warranty of
 *     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 *     GNU General Public License for more details.
 *
 * Or, alternatively,
 *
 *  b) Permission is hereby granted, free of charge, to any person
 *     obtaining a copy of this software and associated documentation
 *     files (the "Software"), to deal in the Software without
 *     restriction, including without limitation the rights to use,
 *     copy, modify, merge, publish, distribute, sublicense, and/or
 *     sell copies of the Software, and to permit persons to whom the
 *     Software is furnished to do so, subject to the following
 *     conditions:
 *
 *     The above copyright notice and this permission notice shall be
 *     included in all copies or substantial portions of the Software.
 *
 *     THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
 *     EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
 *     OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
 *     NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
 *     HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
 *     WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
 *     FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
 *     OTHER DEALINGS IN THE SOFTWARE.
 */

/dts-v1/;

#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/input/input.h>
#include "imx6ul.dtsi"

/ {
	model = "Engicam GEAM6UL Starter Kit";
	compatible = "engicam,imx6ul-geam", "fsl,imx6ul";

	memory@80000000 {
		reg = <0x80000000 0x08000000>;
	};

	backlight {
		compatible = "pwm-backlight";
		pwms = <&pwm8 0 100000>;
		brightness-levels = < 0  1  2  3  4  5  6  7  8  9
				     10 11 12 13 14 15 16 17 18 19
				     20 21 22 23 24 25 26 27 28 29
				     30 31 32 33 34 35 36 37 38 39
				     40 41 42 43 44 45 46 47 48 49
				     50 51 52 53 54 55 56 57 58 59
				     60 61 62 63 64 65 66 67 68 69
				     70 71 72 73 74 75 76 77 78 79
				     80 81 82 83 84 85 86 87 88 89
				     90 91 92 93 94 95 96 97 98 99
				    100>;
		default-brightness-level = <100>;
	};

	chosen {
		stdout-path = &uart1;
	};

	reg_1p8v: regulator-1p8v {
		compatible = "regulator-fixed";
		regulator-name = "1P8V";
		regulator-min-microvolt = <1800000>;
		regulator-max-microvolt = <1800000>;
		regulator-always-on;
		regulator-boot-on;
	};

	reg_3p3v: regulator-3p3v {
		compatible = "regulator-fixed";
		regulator-name = "3P3V";
		regulator-min-microvolt = <3300000>;
		regulator-max-microvolt = <3300000>;
		regulator-always-on;
		regulator-boot-on;
	};

	sound {
		compatible = "simple-audio-card";
		simple-audio-card,name = "imx6ul-geam-sgtl5000";
		simple-audio-card,format = "i2s";
		simple-audio-card,bitclock-master = <&dailink_master>;
		simple-audio-card,frame-master = <&dailink_master>;
		simple-audio-card,widgets =
			"Microphone", "Mic Jack",
			"Line", "Line In",
			"Line", "Line Out",
			"Headphone", "Headphone Jack";
		simple-audio-card,routing =
			"MIC_IN", "Mic Jack",
			"Mic Jack", "Mic Bias",
			"Headphone Jack", "HP_OUT";

		simple-audio-card,cpu {
			sound-dai = <&sai2>;
		};

		dailink_master: simple-audio-card,codec {
			sound-dai = <&sgtl5000>;
			clocks = <&clks IMX6UL_CLK_SAI2>;
		};
	};
};

&can1 {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_flexcan1>;
	xceiver-supply = <&reg_3p3v>;
	status = "okay";
};

&can2 {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_flexcan2>;
	xceiver-supply = <&reg_3p3v>;
	status = "okay";
};

&fec1 {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_enet1>;
	phy-mode = "rmii";
	phy-handle = <&ethphy0>;
	status = "okay";
};

&fec2 {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_enet2>;
	phy-mode = "rmii";
	phy-handle = <&ethphy1>;
	status = "okay";

	mdio {
		#address-cells = <1>;
		#size-cells = <0>;

		ethphy0: ethernet-phy@0 {
			compatible = "ethernet-phy-ieee802.3-c22";
			reg = <0>;
		};

		ethphy1: ethernet-phy@1 {
			compatible = "ethernet-phy-ieee802.3-c22";
			reg = <1>;
		};
	};
};

&gpmi {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_gpmi_nand>;
	nand-on-flash-bbt;
	status = "okay";
};

&i2c1 {
	clock-frequency = <100000>;
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_i2c1>;
	status = "okay";

	sgtl5000: codec@a {
		compatible = "fsl,sgtl5000";
		reg = <0x0a>;
		#sound-dai-cells = <0>;
		clocks = <&clks IMX6UL_CLK_OSC>;
		clock-names = "mclk";
		VDDA-supply = <&reg_3p3v>;
		VDDIO-supply = <&reg_3p3v>;
		VDDD-supply = <&reg_1p8v>;
	};
};

&i2c2 {
	clock_frequency = <100000>;
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_i2c2>;
	status = "okay";
};

&lcdif {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_lcdif_dat
		     &pinctrl_lcdif_ctrl>;
	display = <&display0>;
	status = "okay";

	display0: display {
		bits-per-pixel = <16>;
		bus-width = <18>;

		display-timings {
			native-mode = <&timing0>;
			timing0: timing0 {
				clock-frequency = <28000000>;
				hactive = <800>;
				vactive = <480>;
				hfront-porch = <30>;
				hback-porch = <30>;
				hsync-len = <64>;
				vback-porch = <5>;
				vfront-porch = <5>;
				vsync-len = <20>;
				hsync-active = <0>;
				vsync-active = <0>;
				de-active = <1>;
				pixelclk-active = <0>;
			};
		};
	};
};

&pwm8 {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_pwm8>;
	status = "okay";
};

&tsc {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_tsc>;
	xnur-gpio = <&gpio1 3 GPIO_ACTIVE_LOW>;
};

&sai2 {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_sai2>;
	status = "okay";
};

&tsc {
	measure-delay-time = <0x1ffff>;
	pre-charge-time = <0x1fff>;
	status = "okay";
};

&uart1 {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_uart1>;
	status = "okay";
};

&uart2 {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_uart2>;
	status = "okay";
};

&usbotg1 {
	dr_mode = "peripheral";
	status = "okay";
};

&usbotg2 {
	dr_mode = "host";
	status = "okay";
};

&usdhc1 {
	pinctrl-names = "default", "state_100mhz", "state_200mhz";
	pinctrl-0 = <&pinctrl_usdhc1>;
	pinctrl-1 = <&pinctrl_usdhc1_100mhz>;
	pinctrl-2 = <&pinctrl_usdhc1_200mhz>;
	bus-width = <4>;
	cd-gpios = <&gpio1 19 GPIO_ACTIVE_LOW>;
	no-1-8-v;
	status = "okay";
};

&iomuxc {
	pinctrl_enet1: enet1grp {
		fsl,pins = <
			MX6UL_PAD_ENET1_RX_EN__ENET1_RX_EN	0x1b0b0
			MX6UL_PAD_ENET1_RX_DATA0__ENET1_RDATA00	0x1b0b0
			MX6UL_PAD_ENET1_RX_DATA1__ENET1_RDATA01	0x1b0b0
			MX6UL_PAD_ENET1_TX_EN__ENET1_TX_EN	0x1b0b0
			MX6UL_PAD_ENET1_TX_DATA0__ENET1_TDATA00	0x1b0b0
			MX6UL_PAD_ENET1_TX_DATA1__ENET1_TDATA01	0x1b0b0
			MX6UL_PAD_ENET1_TX_CLK__ENET1_REF_CLK1	0x4001b031
		>;
	};

	pinctrl_enet2: enet2grp {
		fsl,pins = <
			MX6UL_PAD_GPIO1_IO07__ENET2_MDC		0x1b0b0
			MX6UL_PAD_GPIO1_IO06__ENET2_MDIO	0x1b0b0
			MX6UL_PAD_ENET2_RX_EN__ENET2_RX_EN	0x1b0b0
			MX6UL_PAD_ENET2_RX_ER__GPIO2_IO15	0x1b0b0		/* ENET_nRST */
			MX6UL_PAD_ENET2_RX_DATA0__ENET2_RDATA00	0x1b0b0
			MX6UL_PAD_ENET2_RX_DATA1__ENET2_RDATA01	0x1b0b0
			MX6UL_PAD_ENET2_TX_EN__ENET2_TX_EN	0x1b0b0
			MX6UL_PAD_ENET2_TX_DATA0__ENET2_TDATA00	0x1b0b0
			MX6UL_PAD_ENET2_TX_DATA1__ENET2_TDATA01	0x1b0b0
			MX6UL_PAD_GPIO1_IO05__ENET2_REF_CLK2	0x4001b031
		>;
	};

	pinctrl_flexcan1: flexcan1grp {
		fsl,pins = <
			MX6UL_PAD_UART3_RTS_B__FLEXCAN1_RX	0x1b020
			MX6UL_PAD_UART3_CTS_B__FLEXCAN1_TX	0x1b020
		>;
	};

	pinctrl_flexcan2: flexcan2grp {
		fsl,pins = <
			MX6UL_PAD_UART2_RTS_B__FLEXCAN2_RX	0x1b020
			MX6UL_PAD_UART2_CTS_B__FLEXCAN2_TX	0x1b020
		>;
	};

	pinctrl_gpmi_nand: gpmi-nand {
		fsl,pins = <
			MX6UL_PAD_NAND_CLE__RAWNAND_CLE         0xb0b1
			MX6UL_PAD_NAND_ALE__RAWNAND_ALE         0xb0b1
			MX6UL_PAD_NAND_WP_B__RAWNAND_WP_B       0xb0b1
			MX6UL_PAD_NAND_READY_B__RAWNAND_READY_B 0xb000
			MX6UL_PAD_NAND_CE0_B__RAWNAND_CE0_B     0xb0b1
			MX6UL_PAD_NAND_RE_B__RAWNAND_RE_B       0xb0b1
			MX6UL_PAD_NAND_WE_B__RAWNAND_WE_B       0xb0b1
			MX6UL_PAD_NAND_DATA00__RAWNAND_DATA00   0xb0b1
			MX6UL_PAD_NAND_DATA01__RAWNAND_DATA01   0xb0b1
			MX6UL_PAD_NAND_DATA02__RAWNAND_DATA02   0xb0b1
			MX6UL_PAD_NAND_DATA03__RAWNAND_DATA03   0xb0b1
			MX6UL_PAD_NAND_DATA04__RAWNAND_DATA04   0xb0b1
			MX6UL_PAD_NAND_DATA05__RAWNAND_DATA05   0xb0b1
			MX6UL_PAD_NAND_DATA06__RAWNAND_DATA06   0xb0b1
			MX6UL_PAD_NAND_DATA07__RAWNAND_DATA07   0xb0b1
		>;
	};

	pinctrl_i2c1: i2c1grp {
		fsl,pins = <
			MX6UL_PAD_UART4_TX_DATA__I2C1_SCL 0x4001b8b0
			MX6UL_PAD_UART4_RX_DATA__I2C1_SDA 0x4001b8b0
		>;
	};

	pinctrl_i2c2: i2c2grp {
			fsl,pins = <
			MX6UL_PAD_UART5_TX_DATA__I2C2_SCL 0x4001b8b0
			MX6UL_PAD_UART5_RX_DATA__I2C2_SDA 0x4001b8b0
		>;
	};

	pinctrl_lcdif_ctrl: lcdifctrlgrp {
		fsl,pins = <
			MX6UL_PAD_LCD_CLK__LCDIF_CLK	    0x79
			MX6UL_PAD_LCD_ENABLE__LCDIF_ENABLE  0x79
			MX6UL_PAD_LCD_HSYNC__LCDIF_HSYNC    0x79
			MX6UL_PAD_LCD_VSYNC__LCDIF_VSYNC    0x79
		>;
	};

	pinctrl_lcdif_dat: lcdifdatgrp {
		fsl,pins = <
			MX6UL_PAD_LCD_DATA00__LCDIF_DATA00  0x79
			MX6UL_PAD_LCD_DATA01__LCDIF_DATA01  0x79
			MX6UL_PAD_LCD_DATA02__LCDIF_DATA02  0x79
			MX6UL_PAD_LCD_DATA03__LCDIF_DATA03  0x79
			MX6UL_PAD_LCD_DATA04__LCDIF_DATA04  0x79
			MX6UL_PAD_LCD_DATA05__LCDIF_DATA05  0x79
			MX6UL_PAD_LCD_DATA06__LCDIF_DATA06  0x79
			MX6UL_PAD_LCD_DATA07__LCDIF_DATA07  0x79
			MX6UL_PAD_LCD_DATA08__LCDIF_DATA08  0x79
			MX6UL_PAD_LCD_DATA09__LCDIF_DATA09  0x79
			MX6UL_PAD_LCD_DATA10__LCDIF_DATA10  0x79
			MX6UL_PAD_LCD_DATA11__LCDIF_DATA11  0x79
			MX6UL_PAD_LCD_DATA12__LCDIF_DATA12  0x79
			MX6UL_PAD_LCD_DATA13__LCDIF_DATA13  0x79
			MX6UL_PAD_LCD_DATA14__LCDIF_DATA14  0x79
			MX6UL_PAD_LCD_DATA15__LCDIF_DATA15  0x79
			MX6UL_PAD_LCD_DATA16__LCDIF_DATA16  0x79
			MX6UL_PAD_LCD_DATA17__LCDIF_DATA17  0x79
		>;
	};

	pinctrl_pwm8: pwm8grp {
		fsl,pins = <
			MX6UL_PAD_ENET1_RX_ER__PWM8_OUT   0x110b0
		>;
	};

	pinctrl_tsc: tscgrp {
		fsl,pin = <
			MX6UL_PAD_GPIO1_IO01__GPIO1_IO01	0xb0
			MX6UL_PAD_GPIO1_IO02__GPIO1_IO02	0xb0
			MX6UL_PAD_GPIO1_IO03__GPIO1_IO03	0xb0
			MX6UL_PAD_GPIO1_IO04__GPIO1_IO04	0xb0
		>;
	};

	pinctrl_sai2: sai2grp {
		fsl,pins = <
			MX6UL_PAD_JTAG_TCK__SAI2_RX_DATA	0x130b0
			MX6UL_PAD_JTAG_TMS__CCM_CLKO1		0x4001b031
			MX6UL_PAD_JTAG_TDI__SAI2_TX_BCLK	0x17088
			MX6UL_PAD_JTAG_TDO__SAI2_TX_SYNC	0x17088
			MX6UL_PAD_JTAG_TRST_B__SAI2_TX_DATA	0x120b0
		>;
	};

	pinctrl_uart1: uart1grp {
		fsl,pins = <
			MX6UL_PAD_UART1_TX_DATA__UART1_DCE_TX 0x1b0b1
			MX6UL_PAD_UART1_RX_DATA__UART1_DCE_RX 0x1b0b1
		>;
	};

	pinctrl_uart2: uart2grp {
		fsl,pins = <
			MX6UL_PAD_UART2_TX_DATA__UART2_DCE_TX	0x1b0b1
			MX6UL_PAD_UART2_RX_DATA__UART2_DCE_RX	0x1b0b1
			MX6UL_PAD_UART3_RX_DATA__UART2_DCE_RTS	0x1b0b1
			MX6UL_PAD_UART3_TX_DATA__UART2_DCE_CTS	0x1b0b1
		>;
	};

	pinctrl_usdhc1: usdhc1grp {
		fsl,pins = <
			MX6UL_PAD_SD1_CMD__USDHC1_CMD     0x17059
			MX6UL_PAD_SD1_CLK__USDHC1_CLK     0x10059
			MX6UL_PAD_SD1_DATA0__USDHC1_DATA0 0x17059
			MX6UL_PAD_SD1_DATA1__USDHC1_DATA1 0x17059
			MX6UL_PAD_SD1_DATA2__USDHC1_DATA2 0x17059
			MX6UL_PAD_SD1_DATA3__USDHC1_DATA3 0x17059
		>;
	};

	pinctrl_usdhc1_100mhz: usdhc1grp100mhz {
		fsl,pins = <
			MX6UL_PAD_SD1_CMD__USDHC1_CMD     0x170b9
			MX6UL_PAD_SD1_CLK__USDHC1_CLK     0x100b9
			MX6UL_PAD_SD1_DATA0__USDHC1_DATA0 0x170b9
			MX6UL_PAD_SD1_DATA1__USDHC1_DATA1 0x170b9
			MX6UL_PAD_SD1_DATA2__USDHC1_DATA2 0x170b9
			MX6UL_PAD_SD1_DATA3__USDHC1_DATA3 0x170b9
		>;
	};

	pinctrl_usdhc1_200mhz: usdhc1grp200mhz {
		fsl,pins = <
			MX6UL_PAD_SD1_CMD__USDHC1_CMD     0x170f9
			MX6UL_PAD_SD1_CLK__USDHC1_CLK     0x100f9
			MX6UL_PAD_SD1_DATA0__USDHC1_DATA0 0x170f9
			MX6UL_PAD_SD1_DATA1__USDHC1_DATA1 0x170f9
			MX6UL_PAD_SD1_DATA2__USDHC1_DATA2 0x170f9
			MX6UL_PAD_SD1_DATA3__USDHC1_DATA3 0x170f9
		>;
	};

	pinctrl_usdhc2: usdhc2grp {
		fsl,pins = <
			MX6UL_PAD_CSI_VSYNC__USDHC2_CLK     0x17070
			MX6UL_PAD_CSI_HSYNC__USDHC2_CMD     0x10070
			MX6UL_PAD_CSI_DATA00__USDHC2_DATA0  0x17070
			MX6UL_PAD_CSI_DATA01__USDHC2_DATA1  0x17070
			MX6UL_PAD_CSI_DATA02__USDHC2_DATA2  0x17070
			MX6UL_PAD_CSI_DATA03__USDHC2_DATA3  0x17070
		>;
	};
};
Commit	Line	Data
a58e4e60 MT	1	/*
	2	* Copyright (C) 2016 Amarula Solutions B.V.
	3	* Copyright (C) 2016 Engicam S.r.l.
	4	*
	5	* This file is dual-licensed: you can use it either under the terms
	6	* of the GPL or the X11 license, at your option. Note that this dual
	7	* licensing only applies to this file, and not this project as a
	8	* whole.
	9	*
	10	* a) This file is free software; you can redistribute it and/or
	11	* modify it under the terms of the GNU General Public License
	12	* version 2 as published by the Free Software Foundation.
	13	*
13283626	14	* This file is distributed in the hope that it will be useful,
a58e4e60 MT	15	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	16	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	17	* GNU General Public License for more details.
	18	*
13283626	19	* Or, alternatively,
a58e4e60 MT	20	*
	21	* b) Permission is hereby granted, free of charge, to any person
	22	* obtaining a copy of this software and associated documentation
	23	* files (the "Software"), to deal in the Software without
13283626	24	* restriction, including without limitation the rights to use,
a58e4e60 MT	25	* copy, modify, merge, publish, distribute, sublicense, and/or
	26	* sell copies of the Software, and to permit persons to whom the
	27	* Software is furnished to do so, subject to the following
	28	* conditions:
	29	*
	30	* The above copyright notice and this permission notice shall be
	31	* included in all copies or substantial portions of the Software.
	32	*
13283626	33	* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
a58e4e60 MT	34	* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
	35	* OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
	36	* NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
13283626	37	* HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
a58e4e60 MT	38	* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
	39	* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
	40	* OTHER DEALINGS IN THE SOFTWARE.
	41	*/
	42
	43	/dts-v1/;
	44
	45	#include <dt-bindings/gpio/gpio.h>
440fc309 JT	46	#include <dt-bindings/input/input.h>
440fc309 JT	47	#include "imx6ul.dtsi"
a58e4e60 MT	48
a58e4e60 MT	49	/ {
182de5eb	50	model = "Engicam GEAM6UL Starter Kit";
a58e4e60	51	compatible = "engicam,imx6ul-geam", "fsl,imx6ul";
440fc309	52
ad00e080	53	memory@80000000 {
440fc309 JT	54	reg = <0x80000000 0x08000000>;
	55	};
	56
	57	backlight {
	58	compatible = "pwm-backlight";
	59	pwms = <&pwm8 0 100000>;
	60	brightness-levels = < 0 1 2 3 4 5 6 7 8 9
	61	10 11 12 13 14 15 16 17 18 19
	62	20 21 22 23 24 25 26 27 28 29
	63	30 31 32 33 34 35 36 37 38 39
	64	40 41 42 43 44 45 46 47 48 49
	65	50 51 52 53 54 55 56 57 58 59
	66	60 61 62 63 64 65 66 67 68 69
	67	70 71 72 73 74 75 76 77 78 79
	68	80 81 82 83 84 85 86 87 88 89
	69	90 91 92 93 94 95 96 97 98 99
	70	100>;
	71	default-brightness-level = <100>;
	72	};
	73
	74	chosen {
	75	stdout-path = &uart1;
	76	};
	77
	78	reg_1p8v: regulator-1p8v {
	79	compatible = "regulator-fixed";
	80	regulator-name = "1P8V";
	81	regulator-min-microvolt = <1800000>;
	82	regulator-max-microvolt = <1800000>;
	83	regulator-always-on;
	84	regulator-boot-on;
	85	};
	86
	87	reg_3p3v: regulator-3p3v {
	88	compatible = "regulator-fixed";
	89	regulator-name = "3P3V";
	90	regulator-min-microvolt = <3300000>;
	91	regulator-max-microvolt = <3300000>;
	92	regulator-always-on;
	93	regulator-boot-on;
	94	};
84338d91 JT	95
	96	sound {
	97	compatible = "simple-audio-card";
	98	simple-audio-card,name = "imx6ul-geam-sgtl5000";
	99	simple-audio-card,format = "i2s";
	100	simple-audio-card,bitclock-master = <&dailink_master>;
	101	simple-audio-card,frame-master = <&dailink_master>;
	102	simple-audio-card,widgets =
	103	"Microphone", "Mic Jack",
	104	"Line", "Line In",
	105	"Line", "Line Out",
	106	"Headphone", "Headphone Jack";
	107	simple-audio-card,routing =
	108	"MIC_IN", "Mic Jack",
	109	"Mic Jack", "Mic Bias",
	110	"Headphone Jack", "HP_OUT";
	111
	112	simple-audio-card,cpu {
	113	sound-dai = <&sai2>;
	114	};
	115
	116	dailink_master: simple-audio-card,codec {
	117	sound-dai = <&sgtl5000>;
	118	clocks = <&clks IMX6UL_CLK_SAI2>;
	119	};
	120	};
a58e4e60 MT	121	};
	122
	123	&can1 {
440fc309 JT	124	pinctrl-names = "default";
	125	pinctrl-0 = <&pinctrl_flexcan1>;
	126	xceiver-supply = <&reg_3p3v>;
a58e4e60 MT	127	status = "okay";
	128	};
	129
	130	&can2 {
440fc309 JT	131	pinctrl-names = "default";
	132	pinctrl-0 = <&pinctrl_flexcan2>;
	133	xceiver-supply = <&reg_3p3v>;
	134	status = "okay";
	135	};
	136
	137	&fec1 {
	138	pinctrl-names = "default";
	139	pinctrl-0 = <&pinctrl_enet1>;
	140	phy-mode = "rmii";
	141	phy-handle = <&ethphy0>;
	142	status = "okay";
	143	};
	144
	145	&fec2 {
	146	pinctrl-names = "default";
	147	pinctrl-0 = <&pinctrl_enet2>;
	148	phy-mode = "rmii";
	149	phy-handle = <&ethphy1>;
	150	status = "okay";
	151
	152	mdio {
	153	#address-cells = <1>;
	154	#size-cells = <0>;
	155
	156	ethphy0: ethernet-phy@0 {
	157	compatible = "ethernet-phy-ieee802.3-c22";
	158	reg = <0>;
	159	};
	160
	161	ethphy1: ethernet-phy@1 {
	162	compatible = "ethernet-phy-ieee802.3-c22";
	163	reg = <1>;
	164	};
	165	};
	166	};
	167
	168	&gpmi {
	169	pinctrl-names = "default";
	170	pinctrl-0 = <&pinctrl_gpmi_nand>;
	171	nand-on-flash-bbt;
	172	status = "okay";
	173	};
	174
	175	&i2c1 {
	176	clock-frequency = <100000>;
	177	pinctrl-names = "default";
	178	pinctrl-0 = <&pinctrl_i2c1>;
	179	status = "okay";
84338d91 JT	180
	181	sgtl5000: codec@a {
	182	compatible = "fsl,sgtl5000";
	183	reg = <0x0a>;
b08d2fb5	184	#sound-dai-cells = <0>;
84338d91 JT	185	clocks = <&clks IMX6UL_CLK_OSC>;
	186	clock-names = "mclk";
	187	VDDA-supply = <&reg_3p3v>;
	188	VDDIO-supply = <&reg_3p3v>;
	189	VDDD-supply = <&reg_1p8v>;
	190	};
440fc309 JT	191	};
	192
	193	&i2c2 {
	194	clock_frequency = <100000>;
	195	pinctrl-names = "default";
	196	pinctrl-0 = <&pinctrl_i2c2>;
a58e4e60 MT	197	status = "okay";
	198	};
	199
	200	&lcdif {
440fc309 JT	201	pinctrl-names = "default";
	202	pinctrl-0 = <&pinctrl_lcdif_dat
	203	&pinctrl_lcdif_ctrl>;
a58e4e60 MT	204	display = <&display0>;
	205	status = "okay";
	206
	207	display0: display {
	208	bits-per-pixel = <16>;
	209	bus-width = <18>;
a58e4e60 MT	210
	211	display-timings {
	212	native-mode = <&timing0>;
	213	timing0: timing0 {
	214	clock-frequency = <28000000>;
	215	hactive = <800>;
	216	vactive = <480>;
	217	hfront-porch = <30>;
	218	hback-porch = <30>;
	219	hsync-len = <64>;
	220	vback-porch = <5>;
	221	vfront-porch = <5>;
	222	vsync-len = <20>;
	223	hsync-active = <0>;
	224	vsync-active = <0>;
	225	de-active = <1>;
	226	pixelclk-active = <0>;
	227	};
	228	};
	229	};
	230	};
	231
440fc309 JT	232	&pwm8 {
	233	pinctrl-names = "default";
	234	pinctrl-0 = <&pinctrl_pwm8>;
	235	status = "okay";
	236	};
	237
	238	&tsc {
	239	pinctrl-names = "default";
	240	pinctrl-0 = <&pinctrl_tsc>;
	241	xnur-gpio = <&gpio1 3 GPIO_ACTIVE_LOW>;
	242	};
	243
	244	&sai2 {
	245	pinctrl-names = "default";
	246	pinctrl-0 = <&pinctrl_sai2>;
	247	status = "okay";
	248	};
	249
a58e4e60 MT	250	&tsc {
	251	measure-delay-time = <0x1ffff>;
	252	pre-charge-time = <0x1fff>;
	253	status = "okay";
	254	};
440fc309 JT	255
	256	&uart1 {
	257	pinctrl-names = "default";
	258	pinctrl-0 = <&pinctrl_uart1>;
	259	status = "okay";
	260	};
	261
	262	&uart2 {
	263	pinctrl-names = "default";
	264	pinctrl-0 = <&pinctrl_uart2>;
	265	status = "okay";
	266	};
	267
	268	&usbotg1 {
	269	dr_mode = "peripheral";
	270	status = "okay";
	271	};
	272
	273	&usbotg2 {
	274	dr_mode = "host";
	275	status = "okay";
	276	};
	277
	278	&usdhc1 {
	279	pinctrl-names = "default", "state_100mhz", "state_200mhz";
	280	pinctrl-0 = <&pinctrl_usdhc1>;
	281	pinctrl-1 = <&pinctrl_usdhc1_100mhz>;
	282	pinctrl-2 = <&pinctrl_usdhc1_200mhz>;
	283	bus-width = <4>;
	284	cd-gpios = <&gpio1 19 GPIO_ACTIVE_LOW>;
	285	no-1-8-v;
	286	status = "okay";
	287	};
	288
	289	&iomuxc {
	290	pinctrl_enet1: enet1grp {
	291	fsl,pins = <
	292	MX6UL_PAD_ENET1_RX_EN__ENET1_RX_EN 0x1b0b0
	293	MX6UL_PAD_ENET1_RX_DATA0__ENET1_RDATA00 0x1b0b0
	294	MX6UL_PAD_ENET1_RX_DATA1__ENET1_RDATA01 0x1b0b0
	295	MX6UL_PAD_ENET1_TX_EN__ENET1_TX_EN 0x1b0b0
	296	MX6UL_PAD_ENET1_TX_DATA0__ENET1_TDATA00 0x1b0b0
	297	MX6UL_PAD_ENET1_TX_DATA1__ENET1_TDATA01 0x1b0b0
	298	MX6UL_PAD_ENET1_TX_CLK__ENET1_REF_CLK1 0x4001b031
	299	>;
	300	};
	301
	302	pinctrl_enet2: enet2grp {
	303	fsl,pins = <
	304	MX6UL_PAD_GPIO1_IO07__ENET2_MDC 0x1b0b0
	305	MX6UL_PAD_GPIO1_IO06__ENET2_MDIO 0x1b0b0
	306	MX6UL_PAD_ENET2_RX_EN__ENET2_RX_EN 0x1b0b0
	307	MX6UL_PAD_ENET2_RX_ER__GPIO2_IO15 0x1b0b0 /* ENET_nRST */
	308	MX6UL_PAD_ENET2_RX_DATA0__ENET2_RDATA00 0x1b0b0
	309	MX6UL_PAD_ENET2_RX_DATA1__ENET2_RDATA01 0x1b0b0
	310	MX6UL_PAD_ENET2_TX_EN__ENET2_TX_EN 0x1b0b0
	311	MX6UL_PAD_ENET2_TX_DATA0__ENET2_TDATA00 0x1b0b0
	312	MX6UL_PAD_ENET2_TX_DATA1__ENET2_TDATA01 0x1b0b0
	313	MX6UL_PAD_GPIO1_IO05__ENET2_REF_CLK2 0x4001b031
	314	>;
	315	};
	316
	317	pinctrl_flexcan1: flexcan1grp {
	318	fsl,pins = <
319	MX6UL_PAD_UART3_RTS_B__FLEXCAN1_RX 0x1b020
320	MX6UL_PAD_UART3_CTS_B__FLEXCAN1_TX 0x1b020
321	>;
322	};
323
324	pinctrl_flexcan2: flexcan2grp {
325	fsl,pins = <
326	MX6UL_PAD_UART2_RTS_B__FLEXCAN2_RX 0x1b020
327	MX6UL_PAD_UART2_CTS_B__FLEXCAN2_TX 0x1b020
328	>;
329	};
330
331	pinctrl_gpmi_nand: gpmi-nand {
332	fsl,pins = <
333	MX6UL_PAD_NAND_CLE__RAWNAND_CLE 0xb0b1
334	MX6UL_PAD_NAND_ALE__RAWNAND_ALE 0xb0b1
335	MX6UL_PAD_NAND_WP_B__RAWNAND_WP_B 0xb0b1
336	MX6UL_PAD_NAND_READY_B__RAWNAND_READY_B 0xb000
337	MX6UL_PAD_NAND_CE0_B__RAWNAND_CE0_B 0xb0b1
338	MX6UL_PAD_NAND_RE_B__RAWNAND_RE_B 0xb0b1
339	MX6UL_PAD_NAND_WE_B__RAWNAND_WE_B 0xb0b1
340	MX6UL_PAD_NAND_DATA00__RAWNAND_DATA00 0xb0b1
341	MX6UL_PAD_NAND_DATA01__RAWNAND_DATA01 0xb0b1
342	MX6UL_PAD_NAND_DATA02__RAWNAND_DATA02 0xb0b1
343	MX6UL_PAD_NAND_DATA03__RAWNAND_DATA03 0xb0b1
344	MX6UL_PAD_NAND_DATA04__RAWNAND_DATA04 0xb0b1
345	MX6UL_PAD_NAND_DATA05__RAWNAND_DATA05 0xb0b1
346	MX6UL_PAD_NAND_DATA06__RAWNAND_DATA06 0xb0b1
347	MX6UL_PAD_NAND_DATA07__RAWNAND_DATA07 0xb0b1
348	>;
349	};
350
351	pinctrl_i2c1: i2c1grp {
352	fsl,pins = <
353	MX6UL_PAD_UART4_TX_DATA__I2C1_SCL 0x4001b8b0
354	MX6UL_PAD_UART4_RX_DATA__I2C1_SDA 0x4001b8b0
355	>;
356	};
357
358	pinctrl_i2c2: i2c2grp {
359	fsl,pins = <
360	MX6UL_PAD_UART5_TX_DATA__I2C2_SCL 0x4001b8b0
361	MX6UL_PAD_UART5_RX_DATA__I2C2_SDA 0x4001b8b0
362	>;
363	};
364
365	pinctrl_lcdif_ctrl: lcdifctrlgrp {
366	fsl,pins = <
367	MX6UL_PAD_LCD_CLK__LCDIF_CLK 0x79
368	MX6UL_PAD_LCD_ENABLE__LCDIF_ENABLE 0x79
369	MX6UL_PAD_LCD_HSYNC__LCDIF_HSYNC 0x79
370	MX6UL_PAD_LCD_VSYNC__LCDIF_VSYNC 0x79
371	>;
372	};
373
374	pinctrl_lcdif_dat: lcdifdatgrp {
375	fsl,pins = <
376	MX6UL_PAD_LCD_DATA00__LCDIF_DATA00 0x79
377	MX6UL_PAD_LCD_DATA01__LCDIF_DATA01 0x79
378	MX6UL_PAD_LCD_DATA02__LCDIF_DATA02 0x79
379	MX6UL_PAD_LCD_DATA03__LCDIF_DATA03 0x79
380	MX6UL_PAD_LCD_DATA04__LCDIF_DATA04 0x79
381	MX6UL_PAD_LCD_DATA05__LCDIF_DATA05 0x79
382	MX6UL_PAD_LCD_DATA06__LCDIF_DATA06 0x79
383	MX6UL_PAD_LCD_DATA07__LCDIF_DATA07 0x79
384	MX6UL_PAD_LCD_DATA08__LCDIF_DATA08 0x79
385	MX6UL_PAD_LCD_DATA09__LCDIF_DATA09 0x79
386	MX6UL_PAD_LCD_DATA10__LCDIF_DATA10 0x79
387	MX6UL_PAD_LCD_DATA11__LCDIF_DATA11 0x79
388	MX6UL_PAD_LCD_DATA12__LCDIF_DATA12 0x79
389	MX6UL_PAD_LCD_DATA13__LCDIF_DATA13 0x79
390	MX6UL_PAD_LCD_DATA14__LCDIF_DATA14 0x79
391	MX6UL_PAD_LCD_DATA15__LCDIF_DATA15 0x79
392	MX6UL_PAD_LCD_DATA16__LCDIF_DATA16 0x79
393	MX6UL_PAD_LCD_DATA17__LCDIF_DATA17 0x79
394	>;
395	};
396
397	pinctrl_pwm8: pwm8grp {
398	fsl,pins = <
399	MX6UL_PAD_ENET1_RX_ER__PWM8_OUT 0x110b0
400	>;
401	};
402
403	pinctrl_tsc: tscgrp {
404	fsl,pin = <
405	MX6UL_PAD_GPIO1_IO01__GPIO1_IO01 0xb0
406	MX6UL_PAD_GPIO1_IO02__GPIO1_IO02 0xb0
407	MX6UL_PAD_GPIO1_IO03__GPIO1_IO03 0xb0
408	MX6UL_PAD_GPIO1_IO04__GPIO1_IO04 0xb0
409	>;
410	};
411
412	pinctrl_sai2: sai2grp {
413	fsl,pins = <
414	MX6UL_PAD_JTAG_TCK__SAI2_RX_DATA 0x130b0
415	MX6UL_PAD_JTAG_TMS__CCM_CLKO1 0x4001b031
416	MX6UL_PAD_JTAG_TDI__SAI2_TX_BCLK 0x17088
417	MX6UL_PAD_JTAG_TDO__SAI2_TX_SYNC 0x17088
418	MX6UL_PAD_JTAG_TRST_B__SAI2_TX_DATA 0x120b0
419	>;
420	};
421
422	pinctrl_uart1: uart1grp {
423	fsl,pins = <
424	MX6UL_PAD_UART1_TX_DATA__UART1_DCE_TX 0x1b0b1
425	MX6UL_PAD_UART1_RX_DATA__UART1_DCE_RX 0x1b0b1
426	>;
427	};
428
429	pinctrl_uart2: uart2grp {
430	fsl,pins = <
431	MX6UL_PAD_UART2_TX_DATA__UART2_DCE_TX 0x1b0b1
432	MX6UL_PAD_UART2_RX_DATA__UART2_DCE_RX 0x1b0b1
433	MX6UL_PAD_UART3_RX_DATA__UART2_DCE_RTS 0x1b0b1
434	MX6UL_PAD_UART3_TX_DATA__UART2_DCE_CTS 0x1b0b1
435	>;
436	};
437
438	pinctrl_usdhc1: usdhc1grp {
439	fsl,pins = <
440	MX6UL_PAD_SD1_CMD__USDHC1_CMD 0x17059
441	MX6UL_PAD_SD1_CLK__USDHC1_CLK 0x10059
442	MX6UL_PAD_SD1_DATA0__USDHC1_DATA0 0x17059
443	MX6UL_PAD_SD1_DATA1__USDHC1_DATA1 0x17059
444	MX6UL_PAD_SD1_DATA2__USDHC1_DATA2 0x17059
445	MX6UL_PAD_SD1_DATA3__USDHC1_DATA3 0x17059
446	>;
447	};
448
449	pinctrl_usdhc1_100mhz: usdhc1grp100mhz {
450	fsl,pins = <
451	MX6UL_PAD_SD1_CMD__USDHC1_CMD 0x170b9
452	MX6UL_PAD_SD1_CLK__USDHC1_CLK 0x100b9
453	MX6UL_PAD_SD1_DATA0__USDHC1_DATA0 0x170b9
454	MX6UL_PAD_SD1_DATA1__USDHC1_DATA1 0x170b9
455	MX6UL_PAD_SD1_DATA2__USDHC1_DATA2 0x170b9
456	MX6UL_PAD_SD1_DATA3__USDHC1_DATA3 0x170b9
457	>;
458	};
459
460	pinctrl_usdhc1_200mhz: usdhc1grp200mhz {
461	fsl,pins = <
462	MX6UL_PAD_SD1_CMD__USDHC1_CMD 0x170f9
463	MX6UL_PAD_SD1_CLK__USDHC1_CLK 0x100f9
464	MX6UL_PAD_SD1_DATA0__USDHC1_DATA0 0x170f9
465	MX6UL_PAD_SD1_DATA1__USDHC1_DATA1 0x170f9
466	MX6UL_PAD_SD1_DATA2__USDHC1_DATA2 0x170f9
467	MX6UL_PAD_SD1_DATA3__USDHC1_DATA3 0x170f9
468	>;
469	};
470
471	pinctrl_usdhc2: usdhc2grp {
472	fsl,pins = <
473	MX6UL_PAD_CSI_VSYNC__USDHC2_CLK 0x17070
474	MX6UL_PAD_CSI_HSYNC__USDHC2_CMD 0x10070
475	MX6UL_PAD_CSI_DATA00__USDHC2_DATA0 0x17070
476	MX6UL_PAD_CSI_DATA01__USDHC2_DATA1 0x17070
477	MX6UL_PAD_CSI_DATA02__USDHC2_DATA2 0x17070
478	MX6UL_PAD_CSI_DATA03__USDHC2_DATA3 0x17070
479	>;
480	};
481	};